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Read Chanel Technologies For Data Storage

Presented by: Yuan Xing Lee, VP of Engineering, LSI, Oct 2012

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Outline

Problem Statement

Recording Ecosystem

Anatomy of Read Channel

Major Inflection Points

New Challenges

Summary

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Problem Statement First Level Body Text, Arial Regular, 20pt.

• Second Level Bullet, Arial Regular, 18pt. - Third Level Bullet, Arial Regular, 16pt.

↑Density ↓SNR ↑Capability of Read Channel

More and more data bits are being packed onto medium causing signal-to-noise ratio (SNR) to continuously deteriorate;

SNR is primarily dictated by: down-track inter-symbol interference (ISI), cross-track inter-track interference (ITI) and flying height modulation, in conjunction with media/electronics noise;

Signal processing and coding in read channel are devised to tackle the above mentioned impairments;

The objective of read channel is to recover data bits error-free from noisy analog readback signal so to support areal density growth;

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Recording Ecosystem

Spindle Motor

Disk Formatter

R/W Channel

Buffer Management

Host Interface Servo Management

Motor Drivers

DRAM

Microprocessor Subsystem

HOST

SoC

Critical Components: Heads, Media, Mechanics, Preamp, Channel, HDC etc

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Anatomy of Read Channel

Advanced signal proc. & coding recover data from highly noisy conditions

VGA+MRA+CTF+PLL+ADC

Noisy analog readback signal

“Error-free” digital output

Gain + Timing + DC Loops

Equalizer & DDNP SOVA

LDPC

Loops

Analog Front-end Digital Signal Processor

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Major Inflection Points

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1990 1995 2000 2005 2010 2015

SNR

in d

B

Years

Major Inflection Points

1990 – 2000 Detection: peak detector --> PR4ML EPR4ML 16-state Viterbi GPR Noise Processing: noise whitening filter RLL: 2/7, 1/7 RLL 8/9 RLL, Inner ECC: 1-bit parity post-processing Outer ECC: Reed-Solomon

2000 -- 2010 Noise Processing: pattern-dependent filter RLL: 10-bit high-rate RLL, reverse concatenation, 4K Inner ECC: parity iterative decoding Outer ECC: Reed-Solomon LDPC Recording: PMR

Beyond 2010 Detection: ITI, 2D, off-track RLL: transition aware ECC: LDPC new iterative codes, new soft-decision codes Recording: SMR with super sectors, HAMR, BPM

Almost 10dB SNR gain in 2 decades: About 0.5dB per year!

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Process Technology Scaling

Moore's law: Number of transistors doubles about every two year!

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1995 2000 2005 2010 2015

nm

Years

Process Technology Scaling

Moore’s Law Allows to continuously add complex algorithms into a given die area within a given power envelope, generation after generation!

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New Challenges First Level Body Text, Arial Regular, 20pt.

• Second Level Bullet, Arial Regular, 18pt. - Third Level Bullet, Arial Regular, 16pt.

Opportunities for multiple dB!

Detection • Inter-track interference, off-track noise, 2D equalization/detection • Challenge: 2D data handling, computational complexity, area & latency overheads

Recording • SMR with super sectors, TDMR etc • Challenge: Data management, complexity, timing & position overheads, capacity, FH

control

Coding • Beyond binary LDPC: Search for new iterative codes, soft decision codes, 2D-like

codes • Challenge: multiple dBs away from theoretical limit, hard problems to solve in practical

implementation

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LSI Consistent Leadership In Introducing LDPC Technology

LSI Delivers Industry's First 40nm Read Channel to Hard Disk Drive Manufacturers MILPITAS, Calif., June 23, 2009/PRNewswire-FirstCall/ -- LSI Corporation (NYSE: LSI) today announced the TrueStore(R) RC9500, the industry's first 40-nanometer (nm) read channel. Now sampling to hard disk drive (HDD) manufacturers, the RC9500 is designed to support notebook through enterprise HDD form factors and capacity points. The RC9500's next-generation low-density parity check (LDPC) iterative decoding technology enables a greater than 10 percent increase in the data storage capacity of HDDs, reduces read channel power consumption and delivers industry-leading performance with data rates exceeding 4.0Gb/s.

LSI Announces Industry's First 28nm Read Channel for Hard Disk Drive Manufacturers MILPITAS, Calif. , Dec. 22, 2011 /PRNewswire/ -- LSI Corporation (NYSE: LSI - News) today announced that it is demonstrating to OEM customers the TrueStore®

RC5100 read channel for hard disk drives (HDD). The RC5100 is the industry's first 28nm read channel and features a new low-density parity check (LDPC) iterative decoding architecture, which enables HDD manufacturers to achieve increased areal density, higher yield and lower power consumption for HDDs.

LSI Sampling Industry’s First 28nm System-on-a-Chip to Accelerate Delivery of Higher-Capacity Hard Disk Drives MILPITAS, Calif., February 29, 2012 – LSI Corporation (NYSE: LSI) today announced it is sampling the industry’s first 28nm system-on-a-chip (SoC) for the desktop and mobile HDD market segments. The transition to 28nm SoC technology provides a cost-effective way to increase the amount of data that can be stored on a hard drive by enabling higher areal density and yield through superior signal-to-noise ratio performance.

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Summary First Level Body Text, Arial Regular, 20pt.

• Second Level Bullet, Arial Regular, 18pt. - Third Level Bullet, Arial Regular, 16pt.

Innovation will continue and more SNR gains are on the way

The power of signal processing and coding got untethered in circa1990 with advent of partial response channel with maximum likelihood detection (PR4ML)

Within two decades read channel garnered about 10dB of SNR gains

The recent and future developments encompass SMR and 2D related technologies to fuel capacity growth

Process technology finds ways to continue scale materializing complex algorithms into silicon

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