rc_phys

Design with RTL Compiler Physical Product Version 13.1 November 2013

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Design with RTL Compiler PhysicalPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8How to Use the Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Reporting Problems or Errors in Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Cadence Online Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Other Support Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Command-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Getting the Syntax for a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Getting the Syntax for an Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Searching for Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Searching For Commands When You Are Unsure of the Name . . . . . . . . . . . . . . . . 15

Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Using Physical Information in Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Flows, and Product and License Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Special Files for Physical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Physical Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . 22

2Simple PLE Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ContentsNovember 2013 3 Product Version 13.1 1999-2013 All Rights Reserved.

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Attributes Affecting the PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Design with RTL Compiler PhysicalReading the LEF Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Loading the Parasitic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Reviewing Consistency Between the LEF and Parasitic Files . . . . . . . . . . . . . . . . . . 31Checking the Physical Layout Estimation Information . . . . . . . . . . . . . . . . . . . . . . . . 31Setting the Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Reading the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Analyzing the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Sample Script for Simple PLE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3Generating PLE Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Generating the PLE Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Using the PLE Data in the Physical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Attributes Affecting the Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Setting up the Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Reading the LEF Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Loading the Parasitic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Reviewing Consistency Between the LEF and Parasitic Files . . . . . . . . . . . . . . . . . . 51Setting the Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Checking the Physical Layout Estimation Information . . . . . . . . . . . . . . . . . . . . . . . . 52Reading the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Loading Generated PLE Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Synthesizing with Rapid Placement Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Analyzing the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Sample Script for Spatial Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62November 2013 4 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical5RC-Physical Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Attributes Affecting the RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Setting up the RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Reading the LEF Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Loading the Parasitic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Reviewing Consistency Between the LEF and Parasitic Files . . . . . . . . . . . . . . . . . . 72Setting the Appropriate Synthesis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Loading the Encounter Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Checking the Physical Layout Estimation Information . . . . . . . . . . . . . . . . . . . . . . . . 73Reading the Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Loading Generated PLE Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Synthesizing, Estimating, and Optimizing for Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 79Analyzing the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Exporting Files for Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Sample Script for RC-P Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6Structured Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86SDF File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87SDP File Skeleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88alias Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88datapath Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88column Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89inst Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90row Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91SDP File Syntax Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

SDP Information in the Design Information Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . 93SDP Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98November 2013 5 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler PhysicalATerminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107November 2013 6 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler PhysicalPreface

About This Manual on page 8

Additional References on page 8

How to Use the Documentation Set on page 9

Customer Support on page 11

Messages on page 12

Man Pages on page 13

Command-Line Help on page 14

Documentation Conventions on page 16November 2013 7 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical

Preface

About This ManualThis manual describes how to use physical infromation in RTL Compiler.

Additional ReferencesThe following sources are helpful references, but are not included with the product documentation:

TclTutor, a computer aided instruction package for learning the Tcl language:http://www.msen.com/~clif/TclTutor.html.

TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley Publishing Company

IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std.1364-1995)

IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std. 1364-2001)

IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1987) IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1993)Note: For information on purchasing IEEE specifications go to http://shop.ieee.org/store/ and click on Standards.November 2013 8 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

How to Use the Documentation Set

INSTALLATION AND CONFIGURATION

NEW FEATURES AND SOLUTIONS TO PROBLEMS

Cadence Installation Guide

Cadence License Manager

README File

Whats New in Encounter RTL Compiler

README File

Known Problems and Solutions in Encounter RTL Compiler

Using Encounter RTL Compiler

HDL Modeling in Encounter RTL Compiler

Datapath Synthesis in Encounter RTL

Compiler

Setting Constraints and Performing Timing Analysis in Encounter

RTL Compiler

Low Power in Encounter RTL

Compiler

Design for Test in Encounter RTL

Compiler

TASKS AND CONCEPTS

REFERENCES

Attribute Reference for Encounter RTL

Compiler

GUI Guide for Encounter RTL

Compiler

ChipWare in Encounter RTL

Compiler

Command Reference for Encounter RTL

Compiler

Quick Reference for Encounter RTL

Compiler

Command Reference for Encounter RTL

Compiler

Getting Started with Encounter RTL Compiler

Library Guide for Encounter RTL Compiler

ChipWare Developer in Encounter RTL CompilerNovember 2013 9 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Reporting Problems or Errors in ManualsThe Cadence Help online documentation, lets you view, search, and print Cadence product documentation. You can access Cadence Help by typing cdnshelp from your Cadence tools hierarchy.

Contact Cadence Customer Support to file a PCR if you find:

An error in the manual

An omission of information in a manual

A problem using the Cadence Help documentation systemNovember 2013 10 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Customer SupportCadence offers live and online support, as well as customer education and training programs.

Cadence Online Support

The Cadence online support website offers answers to your most common technical questions. It lets you search more than 40,000 FAQs, notifications, software updates, and technical solutions documents that give you step-by-step instructions on how to solve known problems. It also gives you product-specific e-mail notifications, software updates, case tracking, up-to-date release information, full site search capabilities, software update ordering, and much more.

For more information on Cadence online support go to:

http://support.cadence.com

Other Support Offerings Support centersProvide live customer support from Cadence experts who can

answer many questions related to products and platforms.

Software downloadsProvide you with the latest versions of Cadence products.

Education servicesOffers instructor-led classes, self-paced Internet, and virtual classroom.

University software program supportProvides you with the latest information to answer your technical questions.

For more information on these support offerings go to:

http://www.cadence.com/supportNovember 2013 11 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

MessagesFrom within RTL Compiler there are two ways to get information about messages.

Use the report messages command.

For example:rc:/> report messagesThis returns the detailed information for each message output in your current RTL Compiler run. It also includes a summary of how many times each message was issued.

Use the man command.

Note: You can only use the man command for messages within RTL Compiler.

For example, to get more information about the "TIM-11" message, type the following command:rc:/> man TIM-11

If you do not get the details that you need or do not understand a message, either contact Cadence Customer Support to file a PCR or email the message ID you would like improved to:

[email protected] 2013 12 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Man PagesIn addition to the Command and Attribute References, you can also access information about the commands and attributes using the man pages in RTL Compiler. Man pages contain the same content as the Command and Attribute References. To use the man pages from the UNIX shell:

1. Set your environment to view the correct directory:setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man

2. Enter the name of the command or attribute that you want either in RTL Compiler or within the UNIX shell. For example:

man check_dft_rules

man cell_leakage_power

You can also use the more command, which behaves like its UNIX counterpart. If the output of a manpage is too small to be displayed completely on the screen, use the more command to break up the output. Use the spacebar to page forward, like the UNIX more command.rc:/> more man synthesizeNovember 2013 13 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Command-Line HelpYou can get quick syntax help for commands and attributes at the RTL Compiler command-line prompt. There are also enhanced search capabilities so you can more easily search for the command or attribute that you need.

Note: The command syntax representation in this document does not necessarily match the information that you get when you type help command_name. In many cases, the order of the arguments is different. Furthermore, the syntax in this document includes all of the dependencies, where the help information does this only to a certain degree.

If you have any suggestions for improving the command-line help, please e-mail them to:

[email protected]

Getting the Syntax for a Command

Type the help command followed by the command name.

For example:rc:/> help path_delay

This returns the syntax for the path_delay command.

Getting the Syntax for an Attribute

Type the following:rc:/> get_attribute attribute name * -help

For example:rc:/> get_attribute max_transition * -help

This returns the syntax for the max_transition attribute.November 2013 14 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Searching for Attributes

You can get a list of all the available attributes by typing the following command:rc:/> get_attribute * * -help

You can type a sequence of letters after the set_attribute command and press Tab to get a list of all attributes that contain those letters.rc:/> set_attr liambiguous "li": lib_lef_consistency_check_enable lib_search_path libcellliberty_attributes libpin library library_domain line_number

Searching For Commands When You Are Unsure of the Name

You can use help to find a command if you only know part of its name, even as little as one letter.

You can type a single letter and press Tab to get a list of all commands that start with that letter.

For example:rc:/> c

This returns the following commands:ambiguous "c": cache_vname calling_proc case catch cd cdsdoc change_names check_dft_rules chipware clear clock clock_gating clock_ports close cmdExpand command_is_complete concat configure_pad_dft connect_scan_chains continue cwd_install ..

You can type a sequence of letters and press Tab to get a list of all commands that start with those letters.

For example:rc:/> path_

This returns the following commands:ambiguous command name "path_": path_adjust path_delay path_disable path_groupNovember 2013 15 Product Version 13.1 1999-2013 All Rights Reserved.


Preface

Documentation Conventions

Text Command Syntax

The list below defines the syntax conventions used for the RTL Compiler text interface commands.

literal Nonitalic words indicate keywords you enter literally. These keywords represent command or option names.

arguments and options

Words in italics indicate user-defined arguments or information for which you must substitute a name or a value.

| Vertical bars (OR-bars) separate possible choices for a single argument.

[ ] Brackets indicate optional arguments. When used with OR-bars, they enclose a list of choices from which you can choose one.

{ } Braces indicate that a choice is required from the list of arguments separated by OR-bars. Choose one from the list.{ argument1 | argument2 | argument3 }

{ } Braces, used in Tcl commands, indicate that the braces must be typed in.

... Three dots (...) indicate that you can repeat the previous argument. If the three dots are used with brackets (that is, [argument]...), you can specify zero or more arguments. If the three dots are used without brackets (argument...), you must specify at least one argument.

# The pound sign precedes comments in command files.November 2013 16 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical1Introduction

Using Physical Information in Synthesis on page 18

Special Files for Physical Flows on page 20

Physical Information in the Design Information Hierarchy on page 22November 2013 17 Product Version 13.1 1999-2013 All Rights Reserved.


Introduction

Using Physical Information in SynthesisTraditional synthesis tools use vendor-supplied wire-load models based on fanouts, which do not provide accurate wire delay information especially for designs where a significant portion of the delays are contributed by the wires. Consequently, you can see relative big differences in performance, area, and power between the logic and physical designs.

Custom wire-load models are considered to be the starting point for synthesis, as they are more accurate than the vendor-supplied wire-load models. But the disadvantage is that you need to place the design to create custom wire-load models. In addition, placement depends on an initial pass of gate generation done with ad hoc methods. Furthermore, custom wire-load models represent a static view of the design and depend on the netlist used to generate the placement. As the RTL and constraints change over the design cycle, the custom wire-load models become increasingly inaccurate.In many cases, the custom wire-load models generated at the start of the design can be worse than the vendor-supplied wire-load models at the end of the project.Physical layout estimation (PLE) uses physical information to model the effects of placement based on the current state of the RTL and the constraints, and provides you with a level of analysis and optimization that would not be available with a traditional synthesis methodology. Furthermore, using physical information gives a level of down-stream predictability that is superior to using vendor supplied wire-load models. Predictability will enable you to better gauge how the design will perform after place and route and help to reduce frontend to backend hand-off iterations. Ultimately, using physical information in synthesis gives you the opportunity to develop a smaller, faster design in less time than with traditional synthesis.

Table 1-1 summarizes the differences between performing synthesis using physical layout estimation or wire-load models.

Table 1-1 PLE versus WLM

Physical Layout Estimation (PLE) Wire-load Models (WLM)Uses actual design and physical library information.

Wire-load models are statistical.

Dynamically calculates wire delays for different logic structures in the design.

Wire-load models are calculated based on the nearest calibrated area.Selection of appropriate wire-load models for a design is tedious.

Correlates better with place and route. Correlation is difficult even with custom wire-November 2013 18 Product Version 13.1 1999-2013 All Rights Reserved.

load models.


Introduction

Flows, and Product and License Requirements

RTL Compiler offers three physical-related flows. They provide increasing accuracy in predicting the wire lengths.

The simple PLE flow uses technology information and cell areas from the LEF libraries instead of from the synthesis technology libraries. The PLE flow uses parasitic resistance and capacitance values from the LEF libraries or the capacitance tables (if available) when estimating the wire lengths. This flow works in all base RTL Compiler products.

The RC-Spatial flow uses in addition a rapid placement to better estimate long wires in your design. This helps deliver more accuracy to the core synthesis optimization engine during RTL-to-gate synthesis. This flow works in all base RTL Compiler products, but requires access to the Encounter Digital Implementation System.

The RC-Physical flow uses in addition a complete placement and considers congestion and legal placement as a cost function during the RTL-to-gates phase, to create a better netlist. This flow requires an RTL Compiler Advanced Physical Option license in addition to a base RTL Compiler product license and requires access to the Encounter Digital Implementation System.

You do not need a deep, technical knowledge of physical design to use physical information in RTL Compiler. The usage model is kept simple on purpose and the physical data is as abstract as possible. Reading through this document should be sufficient to becoming effective in using physical information in synthesis.November 2013 19 Product Version 13.1 1999-2013 All Rights Reserved.


Introduction

Special Files for Physical FlowsFigure1-1 shows the data flow for the physical flows.

Figure 1-1 Physical Information Files

The following file is required for the three physical-related flows.

LEF The LEF libraries are the physical libraries that contain information such as layer, via, placement site type, routing design rules, process information, and standard cell and macro cell definitions.

The following file is optional but recommended for the three physical-related flows.

Capacitance Table Capacitance tables contain the same type of parasitic information as the LEF files but the resistance and capacitance information in the

SynthesisLibraries

RTL Files

ConstraintFile

Gate-Level Netlist Files

Encounter Database

RTL Compiler

SDC Constraints

LEFLibraries

Capacitance Table File

DEF Floorplan

File

DEFFile

Encounter Configuration

File

Files added for physical Optional file November 2013 20 Product Version 13.1 1999-2013 All Rights Reserved.

capacitance table is more detailed and therefore more accurate than in the LEF file. The


Introduction

values in a capacitance table comes from the same process definition files that drive sign off extraction as well as the various other extractors used in Cadence tools.

The following file is optional but recommended in the RC-PLE and RC-Spatial flow, and is required for the RC-Physical flow:

DEF DEF files are ASCII files that contain information that represent the design at any point during the layout process. In RTL Compiler, the DEF is primarily used for floorplan information.

The following file is optional and can be only used in the RC-Physical flow:

Encounter Configuration The Encounter configuration file contains Tcl variables that describe design information such as the netlist, technology libraries, LEF information, constraints, capacitance tables, resistance scaling factors, capacitance scaling factors, and floorplan parameters. The ability to import the settings from an Encounter Configuration file provides a way for existing Encounter users to quickly get up and running. The preferred methodology is to specify the settings using native RTL Compiler commands.November 2013 21 Product Version 13.1 1999-2013 All Rights Reserved.


Introduction

Physical Information in the Design Information HierarchyRTL Compiler stores the original design data along with additional information in the physical files in the design information hierarchy in the form of attributes. Figure 1-2 shows the design information hierarchy.

Figure 1-2 Design Information Hierarchy

wireload_models

operating_conditions

(rc/>)root

design_name library_name

libcells

wireload_selections

ENC

blockages

PHYS

PLC

wireload_models

operating_conditions

physical_cells

libcells

wireload_selections

designs libraries hdl_librariesmessages object_types

dft

constants

instances_seq

instances_hier

instances_comb

nets

port_busses_in

port_busses_out

ports_in

ports_out

subdesigns

timing

physical

bumpsdefpinsfillsgcellsgroupslayersfillsnondefaultrulespcellspdomainspnetsregionsrows

sitesslotsspecialnetsstylestracksviasNovember 2013 22 Product Version 13.1 1999-2013 All Rights Reserved.


Introduction

The root directory contains the root attributes which apply to all designs that you read in. The root directory has six main directories.

The designs directory can have several subdirectories each representing a design in memory.

The hdl_libraries directory contain information about the ChipWare and third party libraries, and about the Verilog modules and/or VHDL architectures and entities that were read using the read_hdl command.

The libraries directory can have several subdirectories each representing a technology library in memory. The physical_cells contain information about the physical cells that are present in the LEF files (have a LEF MACRO definition), but not in synthesis libraries.

The messages directory contains all information for all messages that can be displayed during an RTL Compiler session. Physical-related messages are stored in the ENC, PHYS, and PLC subdirectories.

The object_types directory lists all attributes for all database objects (designs, subdesigns, pins, and so on) in the design hierarchy.

As shown in Figure 1-2 on page 22, each design also has several objects. The physical engine uses and updates physical-specific attributes on the following object types: Root

Design

Pin

Note: These attributes apply to objects in the pins_in and pins_out directories subdirectories of objects in the instances_comb, instances_hier, and instances_seq directories.

Net

Port

Subdesign

Instance

Note: These attributes apply to objects in the instances_comb, instances_hier, and instances_seq directories.November 2013 23 Product Version 13.1 1999-2013 All Rights Reserved.


Introduction

Each design also has a physical directory with the following subdirectories:

blockages contain information about the BLOCKAGES defined in the DEF file.

bumps contain information about the solder bumps on the chip. A BUMP is instantiated in the DEF COMPONENTS section but is not instantiated in the netlist.

defpins contain information about external pins in the design. The information is based on the PIN statement in the DEF file.

fills contain information about every metal FILL defined in the DEF file.

gcells contain information about the global routing cells (gcell). Gcells are derived from the GCELLGRID statements in the DEF file.

groups contain information about the GROUPS defined in the DEF file.

layers contain information about the metal layers defined in the LEF or capacitance table file.

nondefaultrules contain information based on the NONDEFAULTRULES statement in the DEF file.

pcells contain information about the physical cells (pcell) instantiated in the COMPONENTS section of the DEF file. Pcells are not instantiated in the netlist.

pdomains contain physical information about the power domains defined in the DEF file.

pnets contain information information based on the NETS section in the DEF file.

regions contain information about every REGION defined in the DEF file.

rows contain information about every ROW defined in the DEF file.

sites contain information based on the SITE statement in the LEF file.

slots contain informationabout the slotting of the wires in the design. The information is based on the SLOTS statement in the DEF file.

specialnets contain information based on the SPECIALNETS statement in the DEF file.

styles contain information based on the STYLES statement in the DEF file.

tracks contain track (or routing grid) information for each layer. The information is based on the TRACKS statements in the DEF file.

vias contain information about fixed vias and generated vias. The via names correspond to the via names specified in the VIAS statement. November 2013 24 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical2Simple PLE Flow

Overview on page 26

Attributes Affecting the PLE Flow on page 27

Tasks on page 28

Reading the LEF Libraries on page 28

Loading the Parasitic Information on page 30

Reviewing Consistency Between the LEF and Parasitic Files on page 31

Checking the Physical Layout Estimation Information on page 31

Setting the Appropriate Synthesis Mode on page 33

Reading the Floorplan on page 34

Analyzing the Results on page 37

Exporting Files for Place and Route on page 39

Sample Script for Simple PLE Flow on page 40November 2013 25 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

OverviewThe simple PLE flow does not differ much from the generic flow except that you will be using LEF files and capacitance tables to drive synthesis. Any steps that overlap with the generic flow will not be covered in this chapter. Refer to Using Encounter RTL Compiler for more information on the generic flow.

Figure 2-1 Simple PLE Flow

Meet constraints?

No

Change physical constraints

Change SDC constraintsApply constraints

Modify source

Read timing libraries

Load parasitic information

Review consistency between LEF and parasitic files

HDL files

DEFfile

SDC constraints

Task added for Physical

Start

Read LEF libraries

Target libraries

LEF libraries

Capacitance file

Analyze

Check physical layout estimation information

Read HDL files and elaborate design

Read floorplan

Set synthesis mode

QRC techfile

SynthesizeNovember 2013 26 Product Version 13.1 1999-2013 All Rights Reserved.

YesExport designOptional task


Simple PLE Flow

Attributes Affecting the PLE Flow

Attribute Name Object Type Defaultaspect_ratio design float 1.0cap_table_file root stringinterconnect_mode root string wireloadlef_library root stringlef_stop_on_error root boolean falselib_lef_consistency_check_enable root boolean truenumber_of_routing_layers design integerphys_ignore_nets design boolean falsephys_ignore_special_nets design boolean falseqrc_tech_file root stringshrink_factor root floatuse_area_from_lef root boolean trueutilization layer floatNovember 2013 27 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

TasksThe tasks below list only those that are different from the generic flow or illustrate a new step.









Reading the LEF Libraries

LEF files are ASCII files that contain physical library information such as layer, via, placement site type, routing design rules, process information, and standard cell and macro cell definitions. The technology information and the cell definitions are usually available in separate LEF files for easier management.

In the simple PLE flow, the cell area defined in the LEF libraries is used instead of the cell area defined in the timing library (.lib). The timing library area will be used if

The physical libraries do not contain any cell definitions.

You only read in the technology LEF file (containing only the metal routing layer information without the standard cell/macro definitions).

For best results, always use all available LEF files (standard cell, macro and technology LEF).To import LEF files, use the lef_library attribute. Specify all LEF files, the technology library and the cell libraries. It is a good practice to specify the technology LEF file first.

The following example imports a technology and cell library LEF files. rc:/> set_attribute lef_library {tech.lef cell.lef}November 2013 28 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Use the get_attribute command to confirm the list of imported LEF files:rc:/> get_attribute lef_librarytech.lefcell.lef

RTL Compiler will check whether the following definitions are in the LEF file:

CAPACITANCE CPERSQ

EDGECAPACITANCE

RESISTANCE RPERSQ

SITE

WIDTH

If any of these definitions are missing, RTL Compiler will issue a warning message.

If there is at least one MACRO definition in the LEF file, RTL Compiler checks if all the cells in the timing library have a corresponding definition in the LEF library. Any cells that are defined in the timing library but not in the LEF will be marked as avoid (they will not be used during synthesis) and a warning message will be issued. To turn off this consistency checking, set the lib_lef_consistency_check_enable attribute to false:rc:/> set_attribute lib_lef_consistency_check_enable false /

The resistance and capacitance information can be found in the capacitance table file.

RTL Compiler supports LEF 5.3 and above. Refer to the LEF/DEF Language Reference for more information on LEF files.

Troubleshooting Tips

Only one LEF file seems to be imported

Check if the lef_library attribute was set more than once or was part of a loop.

In the following example, the existing LEF file is replaced because it specifies the files separately with two set_attribute commands as opposed to a Tcl list with one set_attribute command.rc:/> set_attribute lef_library tech.lefrc:/> set_attribute lef_library cell.lefNovember 2013 29 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Loading the Parasitic Information

Capacitance tables files or QRC technology files contain the same type of parasitic information as the LEF files but the resistance and capacitance information in these files have a finer granularity. For technologies below 28nm, the Encounter Digital Implementation System requires a QRC technology file instead of a capacitance table file.

The capacitance in a LEF comes from a foundry and is generated by whatever process it sees as appropriate. The capacitance information in a capacitance table or QRC technology file comes from the same process definition files that drive sign off extraction as well as the various other extractors used in Cadence tools. The process definition files define layer thicknesses, compositions, and spacings.

To load the capacitance table file, use the cap_table_file attribute:rc:/> set_attribute cap_table_file my.cap /

To load the QRC technology file, use the qrc_tech_file attribute:rc:/> set_attribute qrc_tech_file techfile.qrc /

Note: If you specify both a capacitance table file and a QRC technology file, the QRC technology file takes precedence.

It is recommended to specify both LEF and parasitic files. However, you can specify the LEF files only, if the parasitic files are not available.

Scaling factors are used to align a design with a particular process. A capacitance table is process specific where as a scaling factor is design specific. The scaling factors are provided to be consistent with Encounter. Only use a scaling factor if it will also be used in the back-end.

RTL Compiler will check if the following information is available in the parasitic file:

PROCESS_VARIATION

BASIC_CAP_TABLE

width

Cc

Carea

Cfrg

If any of these definitions are missing, RTL Compiler will issue a warning message. It will November 2013 30 Product Version 13.1 1999-2013 All Rights Reserved.

purposely disregard the EXTENDED_CAP_TABLE section because the PLE is intended to synchronize with a view of the design where fast extractors are typically used.


Simple PLE Flow

TipFor best results, the corner for the parasitic file used should match the corner for the timing library. That is typically max or worst.

Reviewing Consistency Between the LEF and Parasitic Files

After you load both your LEF and parasitic files, RTL Compiler will perform consistency checks between the two files. This happens automatically, much like the check between the LEF and timing library files.

Number of Layers RTL Compiler will check to determine if the number of layers defined in the LEF and the parasitic files are equal.

If the LEF has more layers than the parasitic file, then an error message will be issued and you will need to manually check both of the files to resolve the inconsistency.

If the parasitic file has more layers than the LEF, a warning message will be issue and the number of routing layers will be set to the number specified in the parasitic file.

Width of Layers RTL Compiler will check to determine if the width of the layers defined in the LEF and the parasitic files are equal. A warning will only be issued if the width difference defined in the two files is greater than 10%.

RTL Compiler reports the inconsistencies in the log file. You should review the log file. For example, check for messages PHYS 24 through 27.

Checking the Physical Layout Estimation Information

After loading the LEF libraries, the capacitance information, and the design information, you can check the physical layout estimation information for the design.

To report the physical layout estimation information for the design, once all physical data has been read in, use the following command:report ple

As shown in Figure 2-2 on page 32, this command reports information like aspect ratio, shrink factor, site size, layer names, direction of layers, capacitance, resistance, and area. It also shows the source that it used to extract the physical information.

The Interconnect mode line in the report header is set to global, which indicates that you are running in PLE mode. In this flow, this value is kept throughout the flow.November 2013 31 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Figure 2-2 Example of Report PLE rc:/> report ple============================================================

Generated by: Encounter(R) RTL Compiler versionGenerated on: dateModule: DTMF_CHIPTechnology libraries: library1

library2...physical_cells

Operating conditions: slowInterconnect mode: globalArea mode: physical library

============================================================

Aspect ratio : 1.00Shrink factor : 1.00Scale of res/length : 1.00Scale of cap/length : 1.00Net derating factor : 1.00Site size : 5.70 um (from lef [tech+cell])

CapacitanceLayer / Length Data source:

Name Direction Utilization (pF/micron) cap_table_file------------------------------------------------

M1 H 1.00 0.000274M2 V 1.00 0.000242M3 H 1.00 0.000242M4 V 1.00 0.000242M5 H 1.00 0.000242M6 V 1.00 0.000304

ResistanceLayer / Length Data source:

Name Direction Utilization (ohm/micron) lef_library-------------------------------------------------

Metal1 H 1.00 0.439130Metal2 V 1.00 0.360714Metal3 H 1.00 0.360714Metal4 V 1.00 0.360714Metal5 H 1.00 0.360714Metal6 V 1.00 0.102273

AreaLayer / Length Data source:

Name Direction Utilization (micron) lef_library-------------------------------------------------

Metal1 H 1.00 0.230000Metal2 V 1.00 0.280000Metal3 H 1.00 0.280000Metal4 V 1.00 0.280000Metal5 H 1.00 0.280000Metal6 V 1.00 0.440000rc:/>November 2013 32 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Setting the Appropriate Synthesis Mode

RTL Compiler has two synthesis modes: wireload and ple. These modes are set using the interconnect_mode attribute.

In wireload mode (default), you use wire-load models to drive synthesis. In ple mode, you use Physical Layout Estimation (PLE) to drive synthesis. PLE is the

process of using physical information, such as LEF libraries, to provide better closure with back-end tools

When you read in LEF libraries, the interconnect_mode attribute is automatically set to ple.

Note: If you want to use wireload mode, you must manually set the interconnect_mode attribute to wireload after loading the LEF libraries.

For this flow, do not change the setting.November 2013 33 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Reading the Floorplan

Similar to providing timing and design constraints for the logic design, you should provide physical constraints in the form of a floorplan when you use PLE.

In RTL Compiler, you provide floorplan information through a DEF file.

The die or block bounding box determines the placement area and therefore influences the net length.

Pin and macro locations influence the standard cell placement and thus the net length.

RTL Compiler supports DEF 5.3 and above. Refer to the LEF/DEF Language Reference for more information on DEF files.

To import a DEF file, use the read_def command. rc:/> read_def def_file

RTL Compiler will perform a consistency check between the DEF and the Verilog netlist and issue relevant messages if necessary. For example:Parsing DEF file...Warning : A DEF component does not exist in the netlist. [PHYS-171]

: The component IOPADS_INST/Pcornerll does not exist.: This message has a default max print count of 25, which can be

changed by setting the max_print attribute.Warning : A DEF component does not exist in the netlist. [PHYS-171]

: The component IOPADS_INST/Pcornerlr does not exist....

Done parsing DEF file.

The DEF file must define the die size. For better synthesis results, you should also have the pin, macro locations, and standard cell placement specified in the DEF, although it is not required.

Figure 2-3 on page 35 shows an example of DEF statistics printed after the DEF file has been processed. November 2013 34 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Figure 2-3 Example of DEF Statistics Summary report for DEF file /xxx/floorplan/fplan_mp.def

Components----------

Cover: 0Fixed: 71

Physical: 0Placed: 0

Unplaced: 1TOTAL: 72 (1 is class macro)

There are 4 components that do not exist in the netlist.

Pins----

Cover: 0Fixed: 0


Unplaced: 57TOTAL: 62

Nets----

Read: 0Skipped: 0TOTAL: 0

SpecialNets-----------


Fences: 0Guides: 1Regions: 0

Done processing DEF file.

========================Physical Message Summary========================

5 / 5 I PHYS-154 Creating physical pin.4 / 4 W PHYS-171 Component not present in netlist.

71 / 0 I PHYS-181 Full preserve set on instance. Done reading and processing DEF file '/xxx/fplan_mp.def' (time: 1s)..November 2013 35 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Table 2-1 Component Types

Table 2-2 Pin Types

There is also a summary of the blockages defined in the DEF file:Fences: 0Guides: 1Regions: 0

For more information on these terms, refer to the Glossary on page 103

To check which DEF is loaded in the tool, use the def_file attribute:

Type Explanation Tip

Cover A component that has a location and is a part of a cover macro. A COVER component cannot be moved.

A large number of cover cells can indicate that the DEF file is not a floorplan but instead could be the DEF for a fully placed design.

Fixed A component that has a location and that cannot be moved by automatic tools.

All components in a floorplan DEF should be set as fixed to avoid unwanted movement during placement

Physical A component that is instantiated in the DEF but not in the netlist.

A large number of physical components can indicate that the DEF is not a floorplan DEF.

Placed A component that has a location and that can be moved by automatic tools.

These components are not expected in a floorplan.

Unplaced A component that has no location. These components are not expected in a floorplan.

class macro A large component. For example, a memory. The number of class macros should be less than or equal to the number of fixed components.

Type Explanation Tip

Cover A pin that has a location, orientation, and that is part of the cover macro. A COVER pin cannot be moved

Fixed A pin that has a location, orientation and that cannot be moved by automatic tools.

It is recommended to have all pins fixed.

Placed A pin that has a location, orientation and that can be moved by automatic tools.

Unplaced A pin that has no location.November 2013 36 Product Version 13.1 1999-2013 All Rights Reserved.

rc:/> get_attribute def_file /designs/design


Simple PLE Flow

Analyzing the Results To print an area report, use the report area command.

rc:/> report area============================================================




============================================================Instance Cells Cell Area Net Area Total Area------------------------------------------------------------------DTMF_CHIP 4969 1218398 74621 1293018 IOPADS_INST 67 721450 0 721450 DTMF_INST 4902 496948 71032 567980 TDSP_CORE_INST 2831 74538 41884 116422 MPY_32_INST 775 21339 10900 32238 M16X16_INST 592 18422 7083 25505 EXECUTE_INST 631 21472 7071 28543 ALU_32_INST 583 8898 7730 16628 TDSP_CORE_GLUE_INST 458 8073 5268 13341 DECODE_INST 157 5279 1394 6673 PROG_BUS_MACH_INST 57 2628 474 3102 PORT_BUS_MACH_INST 57 2635 466 3100 DATA_BUS_MACH_INST 55 2644 437 3081 TDSP_CORE_MACH_INST 36 1221 383 1604 ACCUM_STAT_INST 17 316 119 435 RAM_256x16_TEST_INST 17 113630 132 113762 RAM_128x16_TEST_INST 17 100778 132 100910 RESULTS_CONV_INST 1779 46573 23785 70358 ARB_INST 22 69455 233 69688 SPI_INST 45 2415 509 2924 DMA_INST 45 1943 454 2396 ULAW_LIN_CONV_INST 58 1207 592 1800 DATA_SAMPLE_MUX_INST 28 659 85 744 DIGIT_REG_INST 10 725 0 725 TDSP_DS_CS_INST 22 446 123 568 TDSP_MUX 17 439 12 451 TEST_CONTROL_INST 8 126 49 175

The Interconnect mode in the report header is still set to global because in the simple PLE flow the design is synthesized without placement information.

The report shows the total count of cells mapped against the hierarchical blocks, the combined cell area in each of the blocks and the top level design. The Cell Area numbers are based on the information in the LEF libraries. The Net Area refers to the estimated post-route net area and is based on the minimum wire widths defined in the LEF and capacitance November 2013 37 Product Version 13.1 1999-2013 All Rights Reserved.

table files and the area of the design blocks.


Simple PLE Flow

To get an overall report containing slack information, instance count, area information, cell power, runtime, and host name information, use the report qor command.rc:/> report qor============================================================

Generated by: Encounter(R) RTL Compiler version...Interconnect mode: globalArea mode: physical library

============================================================Timing--------Clock Period

--------------vclk01 5000.0vclk02 6000.0vclk1 5000.0vclk2 5000.0

Cost Critical ViolatingGroup Path Slack TNS Paths

--------------------------------------default No paths 0vclk01 No paths 0vclk02 No paths 0vclk1 -423.7 -671 4vclk2 2021.0 0 0--------------------------------------Total -671 4Instance Count--------------Leaf Instance Count 4969Sequential Instance Count 546Combinational Instance Count 4423Hierarchical Instance Count 26Area & Power------------Total Area 1293018.485Cell Area 1218397.679Floorplan Utilization 36.45%Leakage Power 4480.258 nWDynamic Power 247756070.964 nWTotal Power 247760551.222 nWMax Fanout 540 (scan_enI)Min Fanout 0 (n_3)Average Fanout 2.5Terms to net ratio 3.5Terms to instance ratio 3.9Runtime 77 secondsHostname hostNovember 2013 38 Product Version 13.1 1999-2013 All Rights Reserved.

Since you performed physical synthesis and started with a floorplan, the report also contains the floorplan utilization in %.


Simple PLE Flow

Exporting Files for Place and Route

The final part of the physical flow involves exporting the data for place and route processing. This is done through the write_design -encounter command.

The write_design -encounter command generates the following files:

Netlist (.v) Encounter configuration file (.conf), SDC constraints (.sdc) Tcl script (.enc_setup.tcl) Mode file (.mode) DEF file (.def) Timing derate file (.derate.tcl) generated when RTL Compiler changed the default

timing derate valuesNovember 2013 39 Product Version 13.1 1999-2013 All Rights Reserved.


Simple PLE Flow

Sample Script for Simple PLE Flowset_attribute source_verbose true /set_attribute information_level 9 /suppress_message "xxx "

set_attribute enc_temp_dir rc_enc /set_attribute lib_search_path path /set_attribute library "library_list" /set_attribute lef_library "lef_list" /# read parasitic information from capacitance table or QRC tech file# set_attribute cap_table_file file /# set_attribute qrc_tech_file techfile.qrc /read_hdl DESIGN/dtmf_chip.velaborate DTMF_CHIPreport pleread_sdc dtmf.sdcread_def DESIGN/floorplan/dtmf.defsynthesize -to_mappedreport area

report qor

write_design -encounterNovember 2013 40 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical3Generating PLE Data

Introduction on page 42

Generating the PLE Data on page 43

Using the PLE Data in the Physical Flows on page 44November 2013 41 Product Version 13.1 1999-2013 All Rights Reserved.


Generating PLE Data

IntroductionUsing LEF libraries and optionally parasitic information (through capacitance tables or QRC technology files) for Physical Layout Estimation (PLE) improves the correlation with the backend as compared to using wire-load models. However with shrinking technologies, it becomes a challenge to correlate well with the place and route tools. There is a need to handle special rectilinear floorplan effects. With no parasitic information or just a rudimentary parsing of the information, the correlation will be off. The solution is to create customized PLE information.

To create PLE correlation data for the design, use the following command:generate_ple_model design -outfile PLE_file

Net capacitances and resistances depend on technology parameters as well as the floorplan. This command refines the PLE parameters by taking both these variables into account and by comparing the PLE data with the SPEF data from Encounter. This results in a highly customized PLE equation for the given design and technology libraries.

The generated file is an encrypted file that contains

Average Capacitance and Resistance values based on placement and default routing

Adjustments for PLE equation parametersThe header of the generated file is readable. Check the header against the current design data to avoid miscorrelation. The header might look like:# DESIGN NAME: DTMF_CHIP# TECHNOLOGY LEF: all.lef# CAP-TABLE: typical.captbl# CAP SCALE: 1.0# RES SCALE: 1.0# ASPECT RATIO: 0.9814

If the design data is inconsistent, a message will be issued.November 2013 42 Product Version 13.1 1999-2013 All Rights Reserved.


Generating PLE Data

Generating the PLE DataAt the start of the synthesis process, use the following flow to generate the PLE data.set_attribute lib_search_path path /set_attribute library library_list /set_attribute lef_library lef_files /read_hdl hdl_fileelaborate# read constraint files including scaling factorsread_def def_filegenerate_ple_model design -outfile ple_filequit

This flow does not require a floorplan, though having a good floorplan is highly recommended. Since the flow generates a quick placement, you need access to the Encounter Digital Implementation System.

If you start from RTL, RTL Compiler will run the following command:synthesize -to_mapped -effort medium

Note: You can also start with a mapped or a placed design to generate the PLE data.

Once the PLE data are generated, quit the session and start a new session with the PLE data.

TipRun this flow once to generate PLE correlation data separately for each design. You can use the same model for small changes in the design, such as small RTL modifications, slight floorplan size changes, or slight macro movements. You can also use the model for different designs with the same technology libraries, but in the latter case the impact of the aspect ratio on the net lengths may be lost.November 2013 43 Product Version 13.1 1999-2013 All Rights Reserved.


Generating PLE Data

Using the PLE Data in the Physical FlowsSource the generated PLE data file for every subsequent run that starts from RTL.set_attribute library library_list /set_attribute lef_library lef_files /read_hdl hdl_fileelaborate# read constraint files including scaling factorsread_def def_filedecrypt ple_filesynthesize ...

Since you need access to the Encounter Digital Implementation System to generate the PLE data, the use of the generated PLE data is only shown in the Spatial Flow and RC-Physical Flow.November 2013 44 Product Version 13.1 1999-2013 All Rights Reserved.

Design with RTL Compiler Physical4Spatial Flow

Overview on page 46

Attributes Affecting the Spatial Flow on page 47

Tasks on page 48

Setting up the Spatial Flow on page 48







Loading Generated PLE Data on page 57

Synthesizing with Rapid Placement Input on page 58



Sample Script for Spatial Flow on page 62November 2013 45 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

OverviewIn addition to using technology information and cell areas from the LEF libraries, and parasitic resistance and capacitance values from the LEF libraries or capacitance tables, the RC-Spatial flow uses a rapid placement to better estimate long wires in your design. This improves the accuracy of the core synthesis optimization engine during RTL-to-gate synthesis. This flow is useful for blocks or chips with simple floorplans.

Figure 4-1 Spatial Flow

Meet constraints?

NoTask added for

PhysicalAnalyze

Synthesize with rapid placement input

Change physical constraints

Change SDC constraintsApply constraints

Modify sourceHDL files

DEF file

SDC constraints


Read HDL files and elaborate design

Read floorplan

Set synthesis mode

Read timing libraries

Load parasitic information

Review consistency between LEF and parasitic files

Start

Read LEF libraries

Target libraries

LEF libraries

Capacitance file

QRC techfile

Load generated PLE data


Using generated PLE dataNovember 2013 46 Product Version 13.1 1999-2013 All Rights Reserved.

YesExport designOptional task


Spatial Flow

Attributes Affecting the Spatial Flow

Attribute Name Object Type Defaultaspect_ratio design float 1.0cap_table_file root stringencounter_executable rootinit_core_utilization design floatinterconnect_mode root string wireloadlef_library root stringlef_stop_on_error root boolean falselib_lef_consistency_check_enable root boolean truenumber_of_routing_layers design integerphys_ignore_nets design boolean falsephys_ignore_special_nets design boolean falsepqos_ignore_msv root boolean falsepqos_ignore_scan_chains root boolean falseqos_report_power root boolean falseqrc_tech_file root stringscale_of_cap_per_unit_length root float 1.0scale_of_res_per_unit_length root float 1.0shrink_factor root floatuse_area_from_lef root boolean trueutilization layer floatNovember 2013 47 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

TasksThe tasks below list only those that are different from the generic flow or illustrate a new step.

Setting up the Spatial Flow on page 48







Loading Generated PLE Data on page 57

Synthesizing with Rapid Placement Input on page 58



Setting up the Spatial Flow To specify the Encounter executable that you want to use for the

synthesize -spatial command, set the following root attribute:set_attribute encounter_executable path_to_soc_executable /

If this attribute is not set, the following (default) search order is used:1. ENCOUNTER environment variable

2. PATH environment variable

3. CDS_SYNTH_ROOT environment variableNovember 2013 48 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

Reading the LEF Libraries

LEF files are ASCII files that contain physical library information such as layer, via, placement site type, routing design rules, process information, and standard cell and macro cell definitions. The technology information and the cell definitions are usually available in separate LEF files for easier management.

In the spatial flow, the cell area defined in the LEF libraries is used instead of the cell area defined in the timing library (.lib). The timing library area will be used if

The physical libraries do not contain any cell definitions.

You only read in the technology LEF file (containing only the metal routing layer information without the standard cell/macro definitions).

For best results, always use all available LEF files (standard cell, macro and technology LEF).To import LEF files, use the lef_library attribute. Specify all LEF files, the technology library and the cell libraries. It is a good practice to specify the technology LEF file first.

The following example imports a technology and cell library LEF files. rc:/> set_attribute lef_library {tech.lef cell.lef}

Use the get_attribute command to confirm the list of imported LEF files:rc:/> get_attribute lef_librarytech.lefcell.lef

RTL Compiler will check whether the following definitions are in the LEF file:

CAPACITANCE CPERSQ

EDGECAPACITANCE

RESISTANCE RPERSQ

SITE

WIDTH

If any of these definitions are missing, RTL Compiler will issue a warning message.

If there is at least one MACRO definition in the LEF file, RTL Compiler checks if all the cells in November 2013 49 Product Version 13.1 1999-2013 All Rights Reserved.

the timing library have a corresponding definition in the LEF library. Any cells that are defined in the timing library but not in the LEF will be marked as avoid (they will not be used during


Spatial Flow

synthesis) and a warning message will be issued. To turn off this consistency checking, set the lib_lef_consistency_check_enable attribute to false:rc:/> set_attribute lib_lef_consistency_check_enable false /

The resistance and capacitance information can be found in the capacitance table file.

RTL Compiler supports LEF 5.3 and above. Refer to the LEF/DEF Language Reference for more information on LEF files.

Troubleshooting Tips

Only one LEF file seems to be imported

Check if the lef_library attribute was set more than once or was part of a loop.

In the following example, the existing LEF file is replaced because it specifies the files separately with two set_attribute commands as opposed to a Tcl list with one set_attribute command.rc:/> set_attribute lef_library tech.lefrc:/> set_attribute lef_library cell.lef

Loading the Parasitic Information

Capacitance tables files or QRC technology files contain the same type of parasitic information as the LEF files but the resistance and capacitance information in these files have a finer granularity. For technologies below 28nm, the Encounter Digital Implementation System requires a QRC technology file instead of a capacitance table file.

The capacitance in a LEF comes from a foundry and is generated by whatever process it sees as appropriate. The capacitance information in a capacitance table or QRC technology file comes from the same process definition files that drive sign off extraction as well as the various other extractors used in Cadence tools. The process definition files define layer thicknesses, compositions, and spacings.

To load the capacitance table file, use the cap_table_file attribute:rc:/> set_attribute cap_table_file my.cap /

To load the QRC technology file, use the qrc_tech_file attribute:rc:/> set_attribute qrc_tech_file techfile.qrc /

Note: If you specify both a capacitance table file and a QRC technology file, the QRC November 2013 50 Product Version 13.1 1999-2013 All Rights Reserved.

technology file takes precedence.


Spatial Flow

It is recommended to specify both LEF and parasitic files. However, you can specify the LEF files only, if the parasitic files are not available.

Scaling factors are used to align a design with a particular process. A capacitance table is process specific where as a scaling factor is design specific. The scaling factors are provided to be consistent with Encounter. Only use a scaling factor if it will also be used in the back-end.

RTL Compiler will check if the following information is available in the parasitic file:

PROCESS_VARIATION

BASIC_CAP_TABLE

width

Cc

Carea

Cfrg

If any of these definitions are missing, RTL Compiler will issue a warning message. It will purposely disregard the EXTENDED_CAP_TABLE section because the PLE is intended to synchronize with a view of the design where fast extractors are typically used.

TipFor best results, the corner for the parasitic file used should match the corner for the timing library. That is typically max or worst.

Reviewing Consistency Between the LEF and Parasitic Files

After you load both your LEF and parasitic files, RTL Compiler will perform consistency checks between the two files. This happens automatically, much like the check between the LEF and timing library files.

Number of Layers RTL Compiler will check to determine if the number of layers defined in the LEF and the parasitic files are equal.

If the LEF has more layers than the parasitic file, then an error message will be issued and you will need to manually check both of the files to resolve the inconsistency.

If the parasitic file has more layers than the LEF, a warning message will be issue and November 2013 51 Product Version 13.1 1999-2013 All Rights Reserved.

the number of routing layers will be set to the number specified in the parasitic file.


Spatial Flow

Width of Layers RTL Compiler will check to determine if the width of the layers defined in the LEF and the parasitic files are equal. A warning will only be issued if the width difference defined in the two files is greater than 10%.

RTL Compiler reports the inconsistencies in the log file. You should review the log file. For example, check for messages PHYS 24 through 27.

Setting the Appropriate Synthesis Mode

RTL Compiler has two synthesis modes: wireload and ple. These modes are set using the interconnect_mode attribute.

In wireload mode (default), you use wire-load models to drive synthesis. In ple mode, you use Physical Layout Estimation (PLE) to drive synthesis. PLE is the

process of using physical information, such as LEF libraries, to provide better closure with back-end tools

When you read in LEF libraries, the interconnect_mode attribute is automatically set to ple.

Note: If you want to use wireload mode, you must manually set the interconnect_mode attribute to wireload after loading the LEF libraries.

For this flow, do not change the setting.

Checking the Physical Layout Estimation Information

After loading the LEF libraries, the capacitance information, and the design information, you can check the physical layout estimation information for the design.

To report the physical layout estimation information for the design, once all physical data has been read in, use the following command:report ple

As shown in Figure 4-2 on page 53, this command reports information like aspect ratio, shrink factor, site size, layer names, direction of layers, capacitance, resistance, and area. It also shows the source that it used to extract the physical information.

The report header contains an Interconnect mode line which indicates that you are running in PLE mode. In this case, the value is set to global because you run the report before the design is synthesized.November 2013 52 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

Figure 4-2 Example of Report PLE rc:/> report ple============================================================




============================================================

Aspect ratio : 1.00Shrink factor : 1.00Scale of res/length : 1.00Scale of cap/length : 1.00Net derating factor : 1.00Site size : 5.70 um (from lef [tech+cell])

CapacitanceLayer / Length Data source:

Name Direction Utilization (pF/micron) cap_table_file------------------------------------------------

M1 H 1.00 0.000274M2 V 1.00 0.000242M3 H 1.00 0.000242M4 V 1.00 0.000242M5 H 1.00 0.000242M6 V 1.00 0.000304

ResistanceLayer / Length Data source:

Name Direction Utilization (ohm/micron) lef_library-------------------------------------------------

Metal1 H 1.00 0.439130Metal2 V 1.00 0.360714Metal3 H 1.00 0.360714Metal4 V 1.00 0.360714Metal5 H 1.00 0.360714Metal6 V 1.00 0.102273

AreaLayer / Length Data source:

Name Direction Utilization (micron) lef_library-------------------------------------------------

Metal1 H 1.00 0.230000Metal2 V 1.00 0.280000Metal3 H 1.00 0.280000Metal4 V 1.00 0.280000Metal5 H 1.00 0.280000Metal6 V 1.00 0.440000rc:/>November 2013 53 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

Reading the Floorplan

Similar to providing timing and design constraints for the logic design, you should provide physical constraints in the form of a floorplan when you use a physical flow.

In RTL Compiler, you provide floorplan information through a DEF file.

The die or block bounding box determines the placement area and therefore influences the net length.

Pin and macro locations influence the standard cell placement and thus the net length.

RTL Compiler supports DEF 5.3 and above. Refer to the LEF/DEF Language Reference for more information on DEF files.

To import a DEF file, use the read_def command. rc:/> read_def def_file

RTL Compiler will perform a consistency check between the DEF and the Verilog netlist and issue relevant messages if necessary. For example:Parsing DEF file...Warning : A DEF component does not exist in the netlist. [PHYS-171] : The component IOPADS_INST/Pcornerll does not exist. : This message has a default max print count of 25, which can be changed by setting the max_print attribute.Warning : A DEF component does not exist in the netlist. [PHYS-171] : The component IOPADS_INST/Pcornerlr does not exist....

Done parsing DEF file.

The DEF file must define the die size. For better synthesis results, you should also have the pin, macro locations, and standard cell placement specified in the DEF, although it is not required.

Figure 4-3 on page 55 shows an example of DEF statistics printed after the DEF file has been processed. November 2013 54 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

Figure 4-3 Example of DEF Statistics Summary report for DEF file /xxx/fplan_mp.def

Components----------

Cover: 0Fixed: 71

Physical: 0Bump: 0

Placed: 0Unplaced: 1

TOTAL: 72 (1 is class macro)There are 4 components that do not exist in the netlist.

Pins----

Cover: 0Fixed: 0


Unplaced: 57TOTAL: 62

Nets----


SpecialNets-----------


Fences: 0Guides: 1Regions: 0

Done processing DEF file.

========================Physical Message Summary========================

5 / 5 I PHYS-154 Creating physical pin.4 / 4 W PHYS-171 Component not present in netlist.

71 / 0 I PHYS-181 Full preserve set on instance. Done reading and processing DEF file '/xxx/fplan_mp.def' (time: 1s).November 2013 55 Product Version 13.1 1999-2013 All Rights Reserved.


Spatial Flow

Table 4-1 Component Types

Table 4-2 Pin Types

Ther

rc_phys

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