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RAM64X1S R

RAM64X1S

64-Deep by 1-Wide Static Synchronous RAM

RAM64X1S is a 64-word by 1-bit static random access memory with synchronouswrite capability. When the write enable is Low, transitions on the write clock (WCLK)are ignored and data stored in the RAM is not affected. When WE is High, anypositive transition on WCLK loads the data on the data input (D) into the wordselected by the 6-bit address (A5 A0). For predictable performance, address and datainputs must be stable before a Low-to-High WCLK transition. This RAM blockassumes an active-High WCLK. However, WCLK can be active-High or active-Low.Any inverter placed on the WCLK input net is absorbed into the block.

The signal output on the data output pin (O) is the data that is stored in the RAM atthe location defined by the values on the address pins.

You can initialize RAM64X1S during configuration using the INIT attribute. SeeSpecifying Initial Contents of a RAMin the RAM16X1D section.

Mode selection is shown in the following truth table.

Usage

For HDL, this design element can be inferred or instantiated. The instantiation code isshown below. For information on how to infer RAM, see the XST User Guide.

Architectures Supported

RAM64X1S

Spartan-II, Spartan-IIE No

Spartan-3 Primitive

Virtex, Virtex-E No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

XC9500, XC9500XV, XC9500XL No

CoolRunner XPLA3 No

CoolRunner-II No

Inputs Outputs

WE (mode) WCLK D O

0 (read) X X Data

1 (read) 0 X Data

1 (read) 1 X Data

1 (write) D D

1 (read) X Data

Data = word addressed by bits A5 A0

X9265

A1

A0

WCLK

D

WE

A5

A4

A3

A2

O

RAM64x1S
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RAM64X1SR

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VHDL Instantiation Template

-- RAM64X1S: 64 x 1 positive edge write, asynchronous read

-- single-port distributed RAM

-- Virtex-II/II-Pro, Spartan-3

-- Xilinx HDL Language Template version 6.1i

RAM64X1S_inst : RAM64X1S

-- The following generic INIT declaration is only necessary

-- if you wish to change the initial

-- contents of the RAM to anything other than all zero's.

generic map (

INIT => X"0000000000000000")

port map (

O => O, -- 1-bit data output

A0 => A0, -- Address[0] input bit





A5 => A5, -- Address[5] input bit D => D, -- 1-bit data input

WCLK => WCLK, -- Write clock input

WE => WE -- Write enable input

);

-- End of RAM64X1S_inst instantiation

Verilog Instantiation Template

-- Note that the use of INIT below is for simulation only. For examples

-- of how to include INIT as an implementation constraint,

-- please refer to the Constraints Guide.

RAM64X1S RAM64X1S_inst ( .O(O), // 1-bit data output

.A0(A0), // Address[0] input bit






.D(D), // 1-bit data input

.WCLK(WCLK), // Write clock input

.WE(WE) // Write enable input

);

// The following defparam INIT declaration is only necessary if you

// wish to change the initial contents of the RAM to anything other// than all zero's. If the instance name for the RAM is is changes,

// that change needs to be reflected in the defparam statement.

defparam RAM64X1S_inst.INIT = 64'h0000000000000000;

// End of RAM64X1S_inst instantiation
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Commonly Used Constraints

BLKNM, HBLKNM, HU_SET, INIT, LOC, RLOC, U_SET, and XBLKNM

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