0018-9162/99/$10.00 1999 IEEE July 1999 27

Computing Practices

Designing an AlphaMicroprocessor

To those who have experienced one, anylarge engineering project can feel like ajourney on a rocket. At the start, all isexcitement and anticipationand fre-quent frustrationas a team wonders if

the whole project will ever get off the ground. Then thereis a rapid acceleration and the realization that there isno turning back. Eventually, in midflight, you feel thetransition into cruising mode as the pace becomes moresteady, the path a little clearer. Finally, as deadlinesapproach, the landing zone comes into sight. The pro-ject-rocket picks up speed, and the team comes face-to-face with the fact that theyre about to land.

Processor design teams at Compaq Computer Corp.have been designing and building microprocessors forabout 20 years. For the past 10 years, they have beendesigning Alpha processors, with the goal of main-taining industry-leading performance with each gen-eration. Over this time, the teams have developed aprocess, outlined here, that supports this goal.

The process has changed as technology has improved.Teams have become larger and projects more complex.The design trajectory has changed over time to adaptto technical and market conditions, but the design goalremains the sameto produce a microprocessor that isfunctional with first-pass silicon.

Unlike a rockets trajectory, however, the develop-ment of a new Alpha microprocessor passes throughmore than a dozen phases, which overlap to a greatdegree. Several occur in parallel. Nevertheless, the tra-jectory analogy feels right. Sticklers may point out thatas a chip design travels along its trajectory, unlike arocket, it gains mass. So, mercifully, we will dispensewith the rocket trajectory analogy here.

PRODUCT DEFINITIONAt the projects outset, a small groupcomposed of

senior technical and marketing professionalssurveysthe market, current research, competitors plans, andtechnology road maps. This group determines a newprocessors performance goals and best feature set.

The task is complex because the market is a movingtarget. Five years or more could pass between this ini-

tial planning stage and the time a customer actuallysees a new processor. Market surveys often appear tohave more in common with crystal ball gazing thanwith science. In five years, will processors for back-room servers be substantially different from those forpersonal systems? What workloads will be important?Will speech recognition be the major computationaltask for the desktop? Or will it be real-time anima-tion? How important are multiprocessor platforms?What will customers want?

Every year the organization sends engineers,researchers, and managers to dozens of conferences,seminars, and workshops. Much of the informationgathered at these meetings is incorporated intorequirements and features for the next generation ofprocessors.

The microprocessor marketplace is extremely com-petitive. Customers demand to know the road map forprocessors they are considering. This appetite foradvanced information and the competition amongteams for marketing presence and even personnelmake most companies surprisingly eager to talk aboutproducts that are years away from completion.

This situation has the rather happy effect of creating apositive feedback loop: Moores law works because semi-conductor companies say it will. If the Froodly ComputerCompany announces that its SuperFroodly VX90 willdeliver 4,000 bogoMips to the desktop in four years, pro-ject planners at Compaq had better have an answer when

Com

putin

g Pr

actic

es

Defining and designing a high-performance processor is high adventure in

computer engineering. Nevertheless, this journey into new technologies and

the unknown has a well-defined path. An architect shares the process the

Alpha design teams use to develop their processors.

Matt ReillyCompaq Computer Corp.

the board of directors asks how Alpha processorswill stack up against such competition.

Finally, the semiconductor industry makesprojections of its own on a regular basis. Theseprojectionswhich influence die size, wafersize, production costs, device performance,interconnect characteristics, and a host of othertechnical and financial measuresare a guidefor equipment manufacturers. They also guideproduct planners. The technology projectionsdefine (or at least suggest) the raw materials thatwill be on hand when the product ships.

At the end of this stage, the project has some-thing that looks like a charter. The product def-inition group has outlined the design task,enumerated the target markets, suggested likelytechnology features and resources, and (ofcourse) defined the performance goals.

Most contributors to product definition have expe-rience in the Alpha design group as circuit designers,architects, marketeers, or researchers. This broadexperience is crucial to finding a balance between mar-ket desires, available technology, and time-to-market.

EXPLORING THE ARCHITECTURAL DESIGN SPACEAs this group develops requirements, the architec-

ture team begins searching for an organizational

scheme for the design. They seek to answer severalquestions: How can the project best use a fixed die areato meet product requirements? How many functionalunits does it need? How much on-chip memory? Whatpolicies, structures, and algorithms will take maximumadvantage of the processors resources?

At the start of this phase, the team is comparativelysmallperhaps a half-dozen architects. They are,however, assisted by a much larger advanced devel-opment and research team as well as Compaqsresearch centers. They work in parallel with (and someare members of) the product definition group.

The architecture team tests most of the trade-offsand new concepts they develop using a performancemodel. This model is a high-level simulator with com-ponents that represent each of the major structuresand features under consideration. The design, con-struction, and maintenance of the model is a signifi-cant software development project on its own.1

But not all questions are answered by a performancestudy. Much of the exploration at this stage takes placeon whiteboards, at technical conferences, and in dis-cussions with circuit designers. As the major questionsare answeredfor example, how many integer unitswill this processor have? How many floating-pointunits and memory ports? What does the pipeline looklike? the team begins to sketch out a floor plan, a

Life for a Processor Design TeamPerhaps we can describe the atmosphere

around a microprocessor project by exam-ining the parking lot.

Product Definition5:30 p.m.: John, an architect, has been

meeting all day with the marketing group.After weeks of brainstorming and readingsurveys from market research and industryconsultants, he eagerly thinks about start-ing on the actual design, as he walks acrossthe full parking lot. The current processordevelopment project will tape out in a fewmonths. Johns project is years away fromtape out.

Exploring the Architectural Design Space7:30 p.m.: Most of the small architec-

ture team has already gone home as Dougwanders across the parking lot deep inthought. Hes spent the day consideringalternatives to the branch predictor thatwas used on the last project. His day isdone, and his simulations will run allnight. The parking lot is nearly empty now.

The Alpha development group is windingdown one project and starting another.

Technology Development, Foundry Specification, and Feasibility Studies

5:15 p.m.: George walks to the parkinglot with the rest of the technology andprocess team. The day has gone well. Thenew technology models indicate that thelikelihood is high that the project will hitits cycle time goalif all goes well. Theparking lot is almost empty by 7:00 p.m.

10:30 p.m.: Sharon, a circuit designer,has been working on block diagrams allday. Hers is the last car to leave the lot.

Tool Development and RTL Modeling12:00 midnight: Tracey has a deadline.

All the VBox RTL code must be ready forreview by next Tuesday. This means longnights, long daysbut just for a few weeks.Traceys car stands alone in the parking lot.

Schematic Design and Functional Verification

7:30 p.m.: Was there ever a time whenshe wasnt drawing schematics? Dianne

cant remember. For 7:30 p.m. on a win-ters evening, there are more cars thanusual in the parking lot, yet the schedulesays things are as they should be. Whilemuch of the team is working a standardwork week (and will continue to do sothrough the end of the project), almost aquarter of the team eats dinner at work.Dinner is served each evening at 6:00p.m.

Logic Verification, Layout, and Circuit Verification

4:00 p.m.: Harold, a layout designer,walks to his car. The days are warm andhes off to spend some time in the sun afterspending the morning and afternoonreworking a circuit layout to fix a fewcross talk problems. It is Saturday. Thereare a few dozen cars in the parking lot.

Tape Out9:00 p.m.: Ronnie has just checked the

last box on the status board. The designdatabase has been passed on to the maskpreparation folks. The chip has taped out.Tomorrow the parking lot will be empty.

28 Computer

Even before productdefinition, teamssometimes work to design new

circuit packaging.

geographic block diagram of the processor.The result of this stages studies is a complete perfor-

mance model and an understanding of the processorsblock-level structure. This information is documented invarious functional-unit specifications, block diagrams,charts, tables, memos, and interface definitions.

At this point in the project, the architecture teamdivides the processor into boxes. Each box has aparticular function. A simple processor might com-prise an IBox that fetches and parses instructions, anEBox that executes integer instructions, an FBox thatexecutes floating-point operations, and an MBox tohandle memory operations. As the team divides thechip into boxes, it does the same to itself. This divi-sion of task and team carries through to the circuitdesign, layout, and the verification teams: Each boxhas its own group of engineers responsible for itsdevelopment, design, and testing. This division of theteam into subgroups is crucial to managing complex-ity. Dividing the chip into boxes creates interfaceboundaries. If poorly chosen or ill-defined, the regionsaround the boundaries can become bug farms. Theassignment of team members to individual boxes is aninteresting management task in itself: an exercise inmatching widely different skill sets and temperamentsto the characteristics, complexity, and size of each box.

The division of the chip into boxes also creates aframework for resolving global design issues.Naturally, it also forms the framework for what is gen-erally good-natured competition between teams andthe occasional dispute as competing needs and per-spectives conflict. For example, an operation down-stream in the execution unit may need support froma feature in the instruction fetch unit. The fetch unitsteam has a set of performance targets and project mile-stones that they intend to meet. If the new featureraises the risk of missing a fetch-unit performancegoal, how is this to be balanced against the schedulerisk taken by the execution unit?

As in most ventures, the questions are resolved byreasoned discussion among peers, blizzards of e-mail,stacks of charts and graphs, hours and days of simu-lation, and an occasional heated debate.

A typical member of the architecture team has adegree in computer engineering. The level of experi-ence varies, but most members have either industrialexperience in circuit design, verification, or systemsarchitecture, or a PhD in computer engineering.

TECHNOLOGY DEVELOPMENT AND FOUNDRY SPECIFICATION

Often, before product definition, the technology andprocess teams are at work designing new packagesthe housings around the actual microprocessor circuits.They also work with vendors to select a new fabrica-tion process, usually one based on CMOS (comple-mentary metal oxide semiconductor). The intent is to

define a fabrication technology that will be ready butnot yet mature when the first prototypes are fabricated.

Though Compaqs Alpha Design Group operatesunder a fabless model (that is, the company doesntown its own production plants or fabs), vendorsrarely present a completely specified process on a take-it-or-leave-it basis. The eventual target process for anew Alpha product comes from a collaborationamong circuit designers, Compaqs technology team,and the chip foundry. The development of the processcontinues through the life of the project and well intothe manufacturing run of a new processor.

The technology team gathers requirements from thecircuit designers, architects, and product managers.The team considers both external and internalresearch and development efforts. They release a seriesof notes describing the process in increasingly greaterdetail and eventually arrive at a set of technology spec-ifications and low-level design rules.

For instance, the document will specify the dielec-tric constants of all insulating layers, the nominal thick-ness of each layer of metal, resistance and capacitanceof on-chip interconnect, and transistor characteristics.Further, the technology specification will set out thelimits of the process, indicating the minimum spacingand width for wires at each layer or the minimum spacebetween transistors, for example. These details are doc-umented in a technology file (actually a book) thatdescribes feature dimensions, layout design rules, elec-trical limits, and transistor characteristics.

Members of the technology team come from a vari-ety of backgrounds in materials science, electrical engi-neering, physics, chemistry, or other physical sciences.The members working with the foundry vendors typi-cally have extensive experience in process development.(The collaboration between vendor and customer ismuch easier when the customer has been there before.)

FEASIBILITY STUDIESEarly in the design process and in parallel with the

architectural exploration, circuit designers test newdesign concepts. For example, what type of state stor-age elements will the new chip use: edge-triggered flip-

July 1999 29

As the designgroup developsrequirements,

the architectureteam develops

an organizationalscheme for the

design.

flops or level-sensitive latches? Are new circuittypes made possible by innovations in the tar-get CMOS process? Is it possible to build thestructures proposed by the architecture team?

Feasibility studies follow the development ofthe processors block diagram and pipelinecharts. As the architecture begins to take form,it becomes possible to identify critical featuresand architectural loops that may be difficult toimplement.

For example, register-renaming structuresmust often implement algorithms that require theoutput at cycle N to depend on the output at cycleN- 1. The circuit that implements this algorithmmust complete its task within the target cycletime. At times, the feasibility analysis finds thata structure cant be implemented in the technol-ogy at hand and still meet the cycle time target.

In other cases, a study may indicate that acircuit does meet cycle time requirements.

Or the study may find that a circuit canimpose intolerable risks to the project, either in termsof schedule (it will take too much time to design, layout, or verify) or reliability (its reliability would be inquestion until the company fabricated a few thousandparts). When studies indicate that an architectural fea-ture is infeasible, architects and circuit designers returnto the whiteboard to work out alternatives.

At the end of the feasibility process, the circuit fea-sibility team has a fairly clear picture of the majorstructures on the chip. Additionally, members havedeveloped a great deal of experience with the newtechnology and architecture. Much of this informa-tion influences the authors of a project design guidea handbook (or set of handbooks) that circuitdesigners and layout designers will use to draw andlay out production schematic diagrams.

The team working on feasibility studies will even-tually form the core of the circuit design team.Typically, members have degrees in electrical or com-puter engineering. Some team members are fresh outof school but work under the supervision of moreexperienced engineers.

TOOL DEVELOPMENTWith each new generation of Alpha processors, the

design style evolves; the team may add new circuittypes or enumerate new design rules. In addition, asgeometries have shrunk from feature sizes of 2 m m toless than 0.18 m m, second- or third-order physicaleffects (such as noise and cross talk) have becomeimportant to the chips performance or even its func-tional correctness.

To cope with these effects and with constantlyincreasing design complexity, Compaq has devotedsignificant effort to developing new computer-aideddesign tools. These CAD tools range from circuit and

30 Computer

layout synthesis tools to design rule checkers for bothcircuits and layout. The design of custom, high-per-formance microprocessors requires a custom set ofdesign tools, many of which the CAD team must buildor modify especially for the current design effort.

For the projects duration, the CAD team developsnew tools based on designer suggestions, the CADteams research, industry trends, and technologyrequirements.

Typically, CAD team members have degrees in elec-trical or computer engineering or computer science.

RTL MODELINGBefore manufacturing a processor, the team must

be reasonably sure that the chip will actually work.For quite some time, chip design teams have used sim-ulation to test designs before they are manufactured.Modern microprocessors, however, are far too com-plex to simulate at the circuit levelthe level of everytransistor or gate. While a team will subject some com-ponents to circuit simulation, it simulates the wholechip at a much higher level of abstraction. Evenswitch-level simulation is too slow for processors withtens of millions of transistors.

Therefore, most of the architectural design verifi-cation effort centers on a high-level description of thechip. This description also serves as a component ofthe chip specification.

The high-level description takes the form of an exe-cutable register-transfer-level (RTL) model, a programwritten in a hardware description language. The RTLdescribes every bit of state in the processor and all ofthe operations that can take place on that state. Itdescribes every register, RAM array, adder, and logicblock. Written by the architecture team with sub-stantial assistance from the circuit design team, theRTL model culminates the teams work on block dia-grams, feasibility analysis, product requirements, andarchitecture research.

As the RTL model begins to take shape, the teamstarts feeling that the project is finally coming together.Every engineer knows the feeling of turning on a newlydesigned widget for the first time. Many architects getthat feeling when the RTL model executes its first pro-gram. But the team is still many months away fromturning on an actual chip.

FUNCTIONAL VERIFICATIONAs a program that describes an Alpha processor, the

RTL model can execute Alpha programs. The verifi-cation team builds a set of tools and a structure thatcreates test programs, runs the programs on the RTLmodel, and compares the state of the RTL model to areference model of an Alpha processor. The referencemodel is based on the chip specification and the AlphaSystem Reference Manual. Much of the referencemodel is borrowed from previous chip efforts, but

Early in the designprocess and in

parallel with thearchitectural

exploration, circuitdesigners test newdesign concepts.

Experienced circuit designers are often able to comeup with creative and elegant designs that would be dif-ficult for an automated system to produce. Compaqsdesign teams have worked to find a balance betweenthe productivity advantages of synthesis and the cre-ativity of clever circuit designers. For this reason, theAlpha team synthesizes some of the processors con-trol logic but designs most data path circuits by hand.Efficient, fast data path logic proceeds from carefulplanning of the interconnect, tuning of componentsizes, and considering a host of third-order effects thatare beyond the ken of synthesis tools. Data path designis more art than science and so is better performed bythe designer-artist than by a machine.

As circuit designers draw the schematics, othersreview them. The schematics are also critiqued by asuite of CAD programs developed to identify depar-tures from accepted design practice. These programsalso identify circuits that may be vulnerable to real-world effects like cross talk, clock skew, and CMOS(fabrication) process variation.

Because of the increasing level of detailmillions oftransistors to draw and miles of wire to routethe cir-cuit design team is two to three times larger than thearchitecture team. The schematic design effort consumesabout a third of the time spent on the project betweenthe start of RTL modeling and delivery of masks to thefoundry. Most team members see this as the cruisingphase, where the project assumes a steady pace.

The schematic design phase typically exposes prob-lems in the original architecture scheme. These areresolved by collaboration between the architectureand implementation teams. As in any collaborationthere is give and take, heat and humor.

LOGIC VERIFICATIONThe functional verification step attempts to show

that the RTL model is correct. But the RTL model istranslated (frequently by humans) into a more detaileddescription (the schematics). This translation step isdifficult and error prone, so demonstrating the cor-rectness of the RTL model is only part of the task.

The architecture team is responsible for ensuringthat the translation from RTL to schematics was faith-

with each new chip the reference model must incor-porate additions to the instruction set and correctlymimic the implementation-specific behaviors that arepeculiar to the new chip.

The architecturally defined states of the two mod-els must correspond perfectly at each clock cycle. Inthis way, the team gains confidence that the RTLmodel describes a processor that correctly executesAlpha instructions.

Architects also use many of these same tests toshow that the circuit design corresponds to the RTLmodel. They run the same program on both the RTLmodel and a gate-level simulation of the circuitschematics. By comparing the major signals describedin both, they demonstrate that the circuit schematicsare a faithful translation of the RTL model.

Unfortunately, no practical simulation effort canexhaustively test a processor design. For this reason,the verification team devotes significant attention todeveloping test programs that stress the processor in asmany ways as possible before the first prototype chips.

The goal of functional verification is to establishan acceptable level of confidence in the assertion thatthe RTL model describes an Alpha microprocessor.The verification team is roughly the same size as thearchitecture team. It builds the infrastructure for cre-ating tests, tracking their results, reporting bugs, andtracking their resolution. Most team members havebackgrounds in computer science or computer engi-neering.

SCHEMATIC DESIGNThe RTL is sufficiently detailed to describe the

processor to a simulation engine, but is far tooabstract to use to generate a layout for the chip. Atranslation stepschematic designis necessarybefore the design can be handed over to the physical-layout team.

Schematic diagrams drawn for Alpha processorstypically describe both the connections between tran-sistors and the relative position of signal wires thelayout team should use as a guide. These geographi-cally organized schematics reduce the probability thatsignal-integrity problems will later force a change inthe physical-design layout.

The circuit design team translates the RTL modelinto circuit schematics. At times, the schematicdesigner will use the RTL model as a guide. At othertimes, the designer will ignore the model altogetherand design a structure that is functionally equivalentor better. In these cases, the architecture team modi-fies the RTL model to correctly reflect the revisedstructures behavior.

The Alpha team makes no distinction betweengate- and transistor-level design. A circuit designer isfree to use the most appropriate level of abstractionfor describing a logic function.

July 1999 31

The verificationteam devotes

significant attention to

developing testprograms that

stress the processor.

late schematic descriptions into optimally packedarrangements of polygons in two dimensions on asmany as ten layers. Complex sets of rules (describedin the technology file) establish the constraints on theplacement of polygons relative to other polygons onthe same layer and on other layers.

CIRCUIT VERIFICATIONDemonstrating a logical correspondence between

the schematics and the RTL model does not mean thatthe actual circuit will work. Logic verification assumesa universe where all transistors are either on or off,and all signals are either true or false and travel at infi-nite speed. In real life, transistors leak, noise and othercircuit effects corrupt signal values, and signals incurdelay in flowing from driver to receiver.

Circuit designers use a host of special-purpose CADtools developed by our own CAD group to verify thecorrect timing behaviorthat signals leave and arrivewhen they are supposed tofor every circuit. Thesetools also help ensure that signals corrupted by crosstalk are still discernible as high or low levels and thatsuch signals do not cause temporary or permanent cir-cuit failures. These CAD tools also ensure that everywire on the chip can carry the current that will flowthrough it, that clock signals arrive at each point onthe chip within tolerances for skew and edge rate, andthat every circuit adheres to accepted design practice.

Most of the tests done at this point require full char-acterization of the wires that connect the chips tran-sistorsthe analysis accounts for each wiresresistance and its capacitance to ground and to neigh-boring wires. Again, the CAD suite is used to extractcapacitance and resistance information from the lay-out database. This information is used in timing analy-sis (for slow paths as well as race analysis), cross talkchecks, and electromigration checks.

This phase of the design task will require a year ormore of concentrated effort. The circuit verificationsteps occur in parallel with the final layout tasks andall of the logic and functional verification.

In the projects last few months, the pace becomesfrenetic. Dozens of tasks in dozens of areas converge,and team members update project-wide status boardsin offices, hallways, and conference rooms. Imaginethe frenzy of an undergraduate computing lab thenight before term projects are due, and you can almostget a feel for the atmosphere in the two or threemonths before the chip is released for fabrication.

FABRICATIONThe processor team releases the design to the fabri-

cation facility only after we are confident that thedesign will produce a chip capable of executing Alphaprograms. Tape out, as this final release is called, is amajor milestone for the entire team. It may take as lit-tle as three weeks from the release date (or tape out) to

ful. They test this correspondence schematic byschematic, building a gate-level logic simulation foreach schematic and running it in parallel with the RTLsimulation of the same circuit. Identical stimulisequences of input data or programsare presentedto both the RTL and logic models. The outputs of bothmodels must match in the expected manner at everycycle. The team resolves discrepancies by either fixingthe schematic or adapting the RTL model. Since theRTL is only a guide for the circuit designer, the RTLis frequently changed to match the schematic.

In addition to simulation at the RTL and logic lev-els, Compaq has recently made more use of tools thatprovide an analytic comparison of the schematics tothe RTL. Such comparison tools can provide a defin-itive and automatic proof that the schematic is a faith-ful translation of the RTL model.

LAYOUTSchematics, though geographically drawn, are still

not sufficiently detailed to describe the chips physicallayout.

As schematics are completed, a team of layoutdesigners begins to translate them into descriptions ofactual chip geometries. That is, they enter each tran-sistor on every schematic into a database as a set ofpolygonsat least nine rectangles in the case of a tran-sistorrepresenting its source, drain, and gate termi-nals. Every wire is also entered into the database.

Along the way, they compare each piece of the layoutdatabase to the schematics it represents. The correspon-dence must be 100 percent faithful. Again, Compaq hasfound that automatic layout synthesis is useful for onlysome parts of the design. For much of the design, skilledlayout designers produce faster, smaller layouts.

At the end of the layout design effort, the chip hasbeen described in minute detail. At this point, the layoutcan be translated into masks for production. But first,the layout is used to generate capacitance and resistanceestimates for every wire on the chip. These are used asinputs to the timing and circuit verification steps.

At its peak, the layout team is similar in size to thecircuit design team. The size of the team during anygiven week varies as the project needs change.Members of the layout team are specifically trained inhigh-performance VLSI layout. Very few have a back-ground in electrical engineering, and all are adept atsolving spatial problems. Layout designers must trans-

32 Computer

A translationstepschematic

designis necessary beforethe design can be

handed over to the physical-

layout team.

Compaq system design groups. The system groupsprovide input to product planning, schedule man-agement, and, of course, the feature set.

From the very beginning, the Alpha team hasinvested in best-of-the-art CAD tools and pro-cesses. Upper management recognized that high-performance processor design was so specializedas to require capabilities and tools that just dontcome from the commodity electronic designautomation market. Alphas CAD developmentgroup has produced advanced tools for every-thing from high-level hardware modeling to spe-cial-purpose design-rule checkers. Sophisticatedtools often require sophisticated users, but thelow turnover in the hardware design groupallows us to effectively deploy these special-pur-pose, sophisticated design automation tools.

Cultural factorsCertainly, the organization has encouraged and

enabled close ties among architecture, circuitdesign, and base-technology development. The orga-nization lacks stratification and maintains an ethic ofcooperation that frowns upon throwing the problemover the wall. These factors provide an environmentin which iteration and compromise allow the team tomake the most of the available talent and technicalresources.

The Alpha design team has also always had a cleartechnical charter. Although business models may havechanged in the 10 years since the first Alpha processoreffort began, the technical mandate has always beento build the worlds fastest microprocessor. Each majornew processor design has taken that as its primarygoal. This has the happy consequence of allowing theteam to develop cost-reduced designs that often out-perform all but our own newest designs.

Most visitors to the Alpha design team are surprisedby the number of engineers in the group with eight, 10,even 15 years and more with the same company. Thiscomparatively low turnover allows the organization toinvest in the career development of each team member.It is much easier to justify two or three years of intensementoring of a new hire if management can expect thenewly trained engineer to stay. As engineers gain moreexperience, there is less need for a rigid design guide:We can place more trust in an individual engineersjudgment. This increased flexibility allows engineers tomake trade-offs at every level of the design process.

Just as low turnover provides an opportunity for moreintense training, it also provides an opportunity for eachengineer to acquire a broader set of skills. Although Ivediscussed the design process as divided into discretesteps, Compaq has found significant advantage in avoid-ing strict correspondence between tasks along the devel-opment path and individual team members.

At various times in the project, team members might

the arrival of the first chips for testing. During this wait-ing period, team members take a much-needed break.

DEBUGFinally, waferseach comprising dozens of proces-

sor chipsemerge and then go on to a wafer test sta-tion where testers exercise the chip. As the team gainsconfidence in the design, selected chips are packagedand tested with another set of tests, and they are even-tually tested in an actual computer system. Once in asystem, the processor undergoes thousands of test pro-grams, perhaps none so complex as the operating sys-tems that Alpha supports: OpenVMS, Tru64 Unix,Windows NT, and Linux.

Booting the operating system(s) is another major mile-stone; an e-mail sent from the prototype systemannounces that the new processor is alive. Each gen-eration of Alpha processor has been able to boot an oper-ating system with first-pass chips, an accomplishmentthat the Alpha teams are extremely proud of. This allowsthe team to conduct much of the debug phase with theaid of an operating system and using real software appli-cations to test the design. As engineers find bugs in thedesign, we incorporate fixes into a second or even thirdpass. Each pass of the design entails a repeat of the design,layout, verification, fabrication, and debug steps.

WHY DOES THIS WORK?With each announcement of a new Alpha proces-

sor, presenters, project leaders, and marketeers areasked the same question: Why is it that the industryshighest performing processors come from a designgroup centered in Shrewsbury, a small town inMassachusetts? It is likely that no one will ever knowthe complete reason, but Id like to suggest a few fac-tors that clearly make a difference.

Technical factorsFirst, the Alpha instruction set architecture was

among the last of the major RISC instruction sets intro-duced. In fact, it was preceded by at least two other pro-posals within Digital Equipment Corp. (The originalhome of the Alpha processor, Digital was purchased byCompaq Computer Corp. in 1998.) Alphas instructionset clearly benefited from the experiences of other designteams both within the company and in the rest of theindustry. As a result, the instruction set presents rela-tively few quirks or impediments to high-performanceimplementations. But the instruction set design is by nomeans the greatest contributor to the teams success.

Alpha processors have always had the benefit of excel-lent compilers, and the corporations investment in com-piler technology is substantial. Compaqs compilerdevelopment groups work closely with the processorarchitects to tune our products to make optimal use ofeach generations new features. The Alpha team also ben-efits from close ties to our major first-level customerthe

July 1999 33

As schematics arecompleted, a team of layout designersbegins to translate

them intodescriptions of

actual chip geometries.

From assembling a team to assembling the finaldesign package for fabrication, the whole effortseems sometimes like a dance. Like dancers, weall have a pretty good idea as to what will come next,though there are always little surprises along the way.While the dance is always fun, it is the surprises thatmake it exciting. v

Reference1. J. Edmondson and M. Reilly, Performance Simulation

of an Alpha Microprocessor, Computer, May 1998,pp. 50-58.

Matt Reilly is a senior member of technical staff atCompaq Computer Corp., where he helps develop themicroarchitecture for Compaqs next-generationAlpha microprocessors. Reilly received a BSEE fromVirginia Polytechnic Institute and State University andan MSEE and a PhD in computer engineering fromCarnegie Mellon University. He is a member of theIEEE.

Contact Reilly at Compaq Computer Corp., 334South St., SHR3-1/S30, Shrewsbury, MA 01545;matthew.reilly@compaq.com.

work on tasks that would normally be outside their jobfunction. A circuit designer, for example, might con-tribute to RTL modeling (often viewed as an architectsjob) or CAD tool development. An architect mightdraw a schematic or two or help in circuit verification.Not only does such a practice promote the developmentof each team member, it also provides an opportunityfor closer cooperation among groups within the team.This practice results in a design that takes advantage ofthe best efforts and advances the team can make in cir-cuits, logic, architecture, and tool design.

Perhaps the most striking and defining characteristicof the Alpha design team is its sense of a shared culture.The design processes are encoded, more often than not,in a set of rituals rather than a set of documents. Theprocess is passed on from the more experienced engi-neers to those at the start of their careers. This culturalmemory is embodied in the group as a whole rather thanin any one team member or even any small subgroup.

It may take as littleas three weeks from tape out to the arrival of the

first chips.

Online CatalogBrowse Search Shop Secure Ordering

http://computer.org

The Anatomy of a High-PerformanceMicroprocessorA Systems Perspective(Interactive Book & CD-ROM)by Bruce Shriver and Bennett Smith

Shriver and Smith use the K6 3D (the new AMD-K6-III processor with 3DNow! technology) as the case study for a detailed overviewof microprocessors, platforms, and systems.

584 pages. 8" x 10" Hardcover / CD-ROM. July 1998. ISBN 0-8186-8400-3Catalog # BP08400 $48.00 Members / $54.00 List

In stock

now!