New FA Opportunities with Ultra Thin Silicon

R. Schlangen, U. Kerst, C. BoitBerlin University of Technology, Germany

S. Schömann, B. KrügerInfineon Technologies, D-81739 Munich, Germany

R. Jain, T. Malik, T. LundquistCredence DCG, CA 94089-1138 Sunnyvale, USA

berli

n

Oct. 2007 EFUG 2007 2

Outline

● FIB Backside Preparation Procedure

● CtS for Probing & FET Characterization

● E-Beam Probing from chip backside

● Backscattered Electron Microscopy

● Outlook

Oct. 2007 EFUG 2007 3

10-5

0µm

up to 250 x 250 µm2

trench placement

?planarity control

FIB Backside Circuit Edit Procedure● mechanical thinning

● localized FIB trench- stopping on n-wells

Oct. 2007 EFUG 2007 4

Navigation & Planarity

Credence - OptiFIB

IR-Microscope

Ion Beam

Global navigation through silicon with co-axial IR and ion column

Co-planarity check of trench bottom to chip levels with interference rings (fringes)

ΔZ≈130nm

Oct. 2007 EFUG 2007 5

FIB Backside Circuit Edit Procedure● mechanical thinning

- stopping on STI

● localized FIB trench- stopping on n-wells

STI

polyp-diffn-diffARC

STI

actives4 - 40000µm2

< 400nm remaining Si● local alignment

Ultra Thin Silicon

Oct. 2007 EFUG 2007 6

Application of CtS for Backside Probing

n-Polyp-PolyIMD

p+ n+

CoSi WM1node of interest

NW PWST

I

active probe

● FIB trench to n well level ● small STI opening ● CtS to node of interest● probing directly on CtS

needle fixed via side walls

Oct. 2007 EFUG 2007 7

bulk-Si

frontside AFP backside

NWPW

IMD

bulk Silicon

W

tungstencontacts

AFP needles

GSD

FIB Pt

● parallel lapping down to contact layer

● isolated devices● low ohmic contact● DuT disfunctional

● FIB backside process● devices not isolated● creation of new

circuit nodes● DuT functional

Accepted publication in ISTFA 07

Oct. 2007 EFUG 2007 8

FIB Created SOI Devices

D G S n-well

STI

Vss

● trench to n-well does not alter device physics

● trench to STI level- well / bulk disconnected- similar to PD SOI- FET body floating

body potential is modulated by any switching of the

device

e-

Oct. 2007 EFUG 2007 9

inv 2

chain 2

inv 3

50MHz

chai

n1

2

3

4

inv 2 inv 3

Accurate Data Monitoring

Very good SNR

Backside E-Beam Probing

e - e -

Oct. 2007 EFUG 2007 10

0

200

400

600

00,511,522,5. . .

Transition from Pass to Fail

Linear Voltage Dependency

Voltage Scaling

Oct. 2007 EFUG 2007 11

Backscattered Electron Generation● e- range is beam energy dependent

DUT surface

SE

e- beam

BSE

SE<50eV<BSE SiO2

11.325.31

3.22

1.55

0.45

0.03

Range [µm]

1.2520

0.3110

0.0925

2.3230

0.7315

~0.0071

max. BSE [µm]

Beam Energy [keV]

origin ofmax. BSE generation Range

● surface information with SE < 50eV● BSE are generated in sample volume

depth of max. BSE generation = f(beam energy)

Oct. 2007 EFUG 2007 12

3D Chip Inspection

D G S n-well

STI

Vss

● remaining thickness below 400nm

● Backscattered Electron Microscopy- scanning through the still functioning DUT

M1

STI

350nmFIB - SiO2

FET

≈ 5keV15keV ≈

Oct. 2007 EFUG 2007 13

One Image = STI, diff, poly, W….

1µm 20kV

Oct. 2007 EFUG 2007 14

One Image = STI, diff, poly, W….

1µm 20kV

Oct. 2007 EFUG 2007 15

Summary

● Ultra Thin Si offers various new applications

● direct probing with reduced impact

● non destructive single FET characterization

● Backside E-Beam Probing

● non destructive 3D chip inspection

● allows complete FA through chip backside

- no depackaging / DuT stays functional