r & d work at smu

J.Ye / SMU April 22, 2023

R & D Work at SMUR & D Work at SMU1. The Test of the GOL chip.2. First test on the SoS driver chip and the

submission of a dedicated test chip for radiation tests.

3. Test results of the GSE laser and a 10 GHz VCSEL .

The SMU group: Wickham Chen, Ping Gui, Andy T. Liu, Ryszard Stroynowski, Annie C. Xiang, John C. Yang, PeiQing Zhu,, Juheng Zhang, Jingbo Ye


1 to 2 Gbps serialisers, why GOL1 to 2 Gbps serialisers, why GOLG-Link1.25 Gbps

TLK25012.5 Gbps

GOL1.6 Gbps

Rad-hardBi-polar, 2.5 W

Rad-soft360 mW

Rad-hard by design, 400 mW LD driver included

23.2×17.2mm2×2.7mmPrice: $50/pcs

12.2×12.2mm2×1mm13×13mm2×1.7mmPrice: $15/pcs


GOL overviewGOL overview GOL overview: Transmission speed

Fast: 1.6Gbps, 32 bit@40MHz Slow: 0.8Gbps, 16 bit@40MHz

Encoding scheme CIMT (ex: HDMP-1024) 8B/10B (ex: TLK2501)

Program interface I2C JTAG

Driver Internal laser driver (bias: 1 mA to 55 mA in 0.4 mA

steps) 50ohm line driver, minimum 780 mV differential. Good for VCSEL and Edge Emitter.

Package: 144 pin fpBGA with 1 mm solder-ball pitch. Dimensions: 13 mm sides, 1.68 mm tall.


GOL architectureGOL architecture


Previous tests Previous tests [ [ Ref. GOL CERN website ]

1. Total dose effect: 10Mrad (x-ray, 10 KeV peak) at a dose rate of 10.06 Krad(SiO2)/min. No current increase after the irradiation.

2. SEU: 60 MeV proton, fluence of 3×1012 p/cm2 at a flux of 3×108p/cm2sec. No SEU was observed.

Requirements: 10 to 100 Mrad and 1015 to 1016p/cm2 fluence.

3. BER tests in lab: better than 1.3×10-14.

4. Power consumption: 400 mW.


Test of the GOL chipTest of the GOL chip

We plan: A complete chip characterizing according to the IEEE

Gigabit Ethernet standard. This includes rise/fall times, eye mask test, jitter studies (DJ and RJ at all 4 testing points of the link system, jitter transfer of the GOL), optical power margin (again in the link system). We did this for the G-Link for the LAr optical link. Agilent didn’t provide it in the data sheet.

The PLL lock range. Probe the total dose limit to see if it reaches 100 Mrad.

Measure SEUs at different flux levels, using 200 MeV proton beams.

Gain experience of using this chip, should it be suitable to inner detector upgrade.


System block diagram for in lab System block diagram for in lab testtest

Pattern/clock generator with jitter input TP1

TP2

TP3

TP4

PC interface


System block diagram for irradiation System block diagram for irradiation test test

FPGA Board

Test chip Carrier Board 1

Test Chip Carrier Board 2

Switch Board

Picoammeter

Prog. V. Source

Freq. Counter

Power Supply BoardDMM

GOL Board 1

GOL Board 2

TLK Rx

PC

USB DIO Card

2 m away from the beamControl Room 37 m away In the beam

Flux

TLK Rx

TTLLVDS

TTLLVDSGPIB

GPIB

GPIB

RS232

This design is still in progress and is changing on daily basis.


The scheduleThe schedule

System design 1 monthSchematic capture 1 monthPCB layout 1 month

Board assembly 3 wkPCB Debug 3 wk

FPGA code 1.5 month

Lab Test 1 month

Labview code 1 month

Irradiation Tests

10/1/05

11/1/05

12/1/05

1/15/05

2/15/063/1/06

3/31/06

We are here


Why SoSWhy SoS There is no guarantee that GOL can withstand

~10 times more radiation than what has been tested.

We do not know if more bandwidth would be needed.

We are designing a Link-on-Chip ASIC for the LAr upgrade. This chip may be used for the ID upgrade as well.

This project has just been started. Here I report on the first irradiation test and the actions we take based on the preliminary result.


The Irradiation of one SoS chipThe Irradiation of one SoS chip A laser driver chip based on 0.5 m SoS

technology was irradiated at MGH (230 MeV proton).

Total dose: 116 Mrad. Error free at 1.5 krad/sec and up to 17 Mrad. LAr upgrade

okay. Observed current increase at very high dose rate.


The SoS test chip The SoS test chip In CMOS layout, the technique to combat the

leakage current is the enclosed layout transistor (ELT) and the guard-ring around the transistors. In SoS, only ELT is needed.

We will use the new 0.25 m SoS technology for the LOC design. In order to probe the total dose limit, to check ELT on SoS, and to check layout parameters on design blocks like the PLL, we submitted a dedicated test chip mid October.

The test of this chip is in preparation (3 slides back) and the irradiation test is aimed for April 2006.


1) 12X9 transistor array, ELT and “standard” layout, NMOS and PMOS with different size.Test layout techniques and rad-hard limit.

2) 4 ring oscillators (ELT, “std”, different transistor size). Test SEUs.

3) 5 shift Registers (… + various resistors, majority voting). Test SEUs.

4) 6 individual gates (ELT and “std”).

5) PLL parts:- Div16- VCO- PFD

12 X 8 Transistor

Array6 Individual

Gates

4 Ring oscillators

5 Shift registers

PLL parts

The SoS test chip block diagramThe SoS test chip block diagram

Many parameters will be measured in lab and in irradiation. The results will guide us in designing of the LOC chip.


The SoS test chip layoutThe SoS test chip layout

Transistorsarray

PLL cells

CMOS Ring Oscillators

Shift Registers

Individual gates

Resistors

Differential Ring Oscillator

Majority votecircuitry


Looking for E/O devicesLooking for E/O devices We also started to look for laser diodes. We

tested two surface emitting lasers. One long wavelength and can couple to single mode fiber, one VCSEL. The preliminary results are briefly reported here.


Test results on the GSE laserTest results on the GSE laserWe exposed 12 Grating-outcoupled Surface-Emitting laser (1310

nm) up to 22.3 Mrad at IUCF with 200 MeV proton. The lasers that received 11.4 Mrad total dose still pass 2.5 Gbps eye mask test.

1.8 MradPass.

22.3 MradFail.

5.9 MradPass.

11.4 MradPass.


Test results of a 10 GHz VCSELTest results of a 10 GHz VCSELPreliminary test results on the ULM 10 GHz VCSEL:We irradiated 2 ULM 10 GHz VCSELs at MGH. The VCSEL were biased during irradiation. The total dose received is 116 Mrad. All DC parameters are still within spec after the irradiation.

V-I curve

0

0.5

1

1.5

2

2.5

3

0 5 10 15current (mA)

volta

ge (V

)

L-I curve

0

0.5

1

1.5

2

2.5

0 5 10 15current (mA)

pow

er (m

W)

rad1rad2nonrad3nonrad4nonrad5nonrad6nonrad7nonrad8

Eye diagram and other AC parameters will be measured soon.


SummarySummary The GOL test program has been started and is

on track. We designed and submitted a dedicated SoS

test chip to check out layout techniques and measure related parameters. The lab and irradiation tests of this chip is in preparation.

We have tested the GSE lasers and find them useful in 11 Mrad environment. The GSE lasers can couple to single mode fibers. The results are accepted for publishing by Photonics Technology Letters (PLT).

We have identified a 10 GHz VCSLE and preliminary test results show potential in use with 100 Mrad. More tests are on going and more VCSELs will be tested.

r & d work at smu

Documents