queueing theory modeling of a cpu-gpu system september 15, 2010 lindsay b. h. may, ph.d. systems...
DESCRIPTION
Private Memory Work Item 1 Local Memory Global/Constant Memory Data Cache Global Memory Compute Device Memory Compute Device Private Memory Work Item M Private Memory Work Item 1 Private Memory Work Item M Local Memory Compute Unit 1Compute Unit N SM 2 SM net 2 SM net 1 SM 3 SM net 3 M0M0 P0MP0M M0M0 P01P01 SM net 1 M0M0 M0M0 P0MP0M P01P01 GPU Global Memory CPU Compute Units PCIe Connection Station 1 Depends on shader clock rate Station 3Station 2 GPU Shared Memory OpenCL Model, Kuck Diagram, and Queueing Model SM 1TRANSCRIPT
Queueing Theory Modeling of a CPU-GPU System
September 15, 2010
Lindsay B. H. May, Ph.D.Systems Engineer
Problem/Goals
• GPGPUs have been touted as the solution to the loss of the Altivec engine in PowerPCs in the embedded space
• We set out to answer a few questions…– Are GPGPUs all that they are purported to be?– What are some of the defining architectural limitations?– We know they’re good for graphics but how well do they map into our problem
space?– Is there a discernable task/data level parallelism “line” defined by the architecture?– Is there a reasonable mathematical modeling approach to this problem?
Private Memory
Work Item 1
Local Memory
Global/Constant Memory Data Cache
Global MemoryCompute Device Memory
Compute Device
Private Memory
Work Item M
Private Memory
Work Item 1
Private Memory
Work Item M
Local Memory
Compute Unit 1 Compute Unit N
SM2
SM net2
SM net1
SM3
SM net3
M0
P0M
M0
P01
SM net1
M0M0
P0MP0
1
GPU Global Memory
CPU
Compute Units
PCIe Connection
Station 1
Depends on
shader clock rate
Station 3Station 2GPU
Shared Memory
OpenCL Model, Kuck Diagram, and Queueing Model
SM1SM1
)1(1
)1(1
)1(1
K
PK
K
K
K
)1(2
)1()(1
))(1(1
*
*1*
1*
*
*
K
K
NK
K
KP 1*
M0
P0
Queuesize = Kq
Server
Arrival Rate ()
Service Rate (m)
M/M/1/K
K = Kq+1
Queueing Equations
m
*, * include effects of blocking
GPGPUs for HPEC – Hype or Hope?