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MICROELECTRONICS SIMULATIONS LABORATORY DEPT OF ELECTRICAL ENGINEERING, IIT BOMBAY

ASSIGNMENT 4 – SMALL AREA MOSFET SIMULATION OF SMALL AREA MOSFET (SUB 100nm)

NAME – INDRANIL CHAKRABORTY

ROLL NO- 143070072

PROGRAMME – M.TECH

DEPT – ELECTRICAL ENGINEERING

SPECIALIZATION – MICROELECTRONICS

ACKNOWLEDGEMENTS:

SIMULATION SOFTWARE – SENTAURUS

BOOKS REFERRED - Silicon VLSI Technology (Plummer)

Firstly, we scale down the MOSFET designed in the previous assignment to sub-100 nm and analyze its characteristics.

SPROCESS We simply reduce the gate length to 90nm and reduce the oxide thickness to 1.5nm, and do not optimize the device any further.

We observe that the effective Gate Length has reduced significantly.

SDEVICE • Threshold Voltage

Vtlin

We plot the ID-VG curve at low VDS(0.05V) and find out the linear threshold voltage by max-gm method.

Observed Vtlin:

𝑉𝑉𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 = 0.508𝑉𝑉 −𝑉𝑉𝐷𝐷𝐷𝐷

2

𝑉𝑉𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 = 0.483𝑉𝑉

Vtsat

We plot the ID-VG curve at high VDS(1.2V) and find out the saturation threshold voltage by max-gm

method.

Observed Vtsat:


𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜 = 0.55𝑛𝑛𝑛𝑛

𝐼𝐼𝑜𝑜𝑡𝑡 = 0.6𝑚𝑚𝑛𝑛

𝐼𝐼𝑜𝑜𝑡𝑡𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜

= 1.09𝑀𝑀

So, we observe that the On current and Off current do not meet specifications, and hence we have to optimize the device.

OPTIMIZATION

We optimize the above device in the following way:

1) Deep Boron Implant: Deep Boron implants were done implant Boron dose=3.15e14<cm-2> energy=200<keV> tilt=0 rotation=0 implant Boron dose=0.55e14<cm-2> energy= 80<keV> tilt=0 rotation=0

2) Vt adjust implant: Shallow Boron implants were done to adjust the threshold voltage around 0.3-0.5V implant Boron dose=0.8e13<cm-2> energy= 28<keV> tilt=0 rotation=0

3) LDD implant: Lightly doped drain gives us shallow drain junctions in the overlap region of drain and gate. Hence, we applied this implant so as to reduce the hot carrier effect by reducing the electric field in the channel near the drain region. implant Arsenic dose=3.1e14<cm-2> energy=2<keV> tilt=0 rotation=0

4) Halo Implants: Halo Boron implants were done to avoid Punch through of the depletion region as the drain and source are quite near to each other. implant Boron dose=1e13<cm-2> energy=3<keV> tilt=30<degree> \ rotation=0 implant Boron dose=1e13<cm-2> energy=3<keV> tilt=30<degree> \ rotation=90<degree> implant Boron dose=1e13<cm-2> energy=3<keV> tilt=30<degree> \ rotation=180<degree> implant Boron dose=1e13<cm-2> energy=3<keV> tilt=30<degree> \ rotation=270<degree> diffuse temperature=1050<C> time=5.0<s>

5) Nitride Spacer Creation: Spacer is the created so as to separate the deep source and drain implants from the gate or channel region. deposit material= {Nitride} type=isotropic time=1 rate= {0.08} etch material= {Nitride} type=anisotropic time=1 rate= {0.096} etch material= {Oxide} type=anisotropic time=1 rate= {0.01}

6) Deep Source/Drain implants: Deep implants are done using a slight tilt so as to introduce the implants ions at an inclined angle away from the Gate. implant Arsenic dose=1e15<cm-2> energy=6<keV> tilt=7<degree> \ rotation=-90<degree>

FINAL DEVICE

SPECIFICATIONS:

Effective Gate Length = 68nm

Oxide Thickness = 1.5nm

Source/Drain Depth: 40nm

DEVICE CHARACTERISTICS EXTRACTION of Vt: We have used a script to find out the threshold voltage by the max-gm method using the INSPECT tool load_library EXTRACT set Vt [ExtractVtgm Vtgm <Curve> nMOS] 1) Threshold Voltage (low VDS)(Vtlin)(VDS = 0.05V)

By max-gm method, we observe,

𝑉𝑉𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 = 0.335𝑉𝑉 −𝑉𝑉𝐷𝐷𝐷𝐷

2


2) Threshold Voltage (high VDS)(Vtlin)(VDS = 1.2V)(n=1.3) ID-VG

ID1/n-VG(n=1.3)


3) Vt roll off At L=80nm

ID1/n-VG curve(n=1.4)


At L=70nm ID

1/n-VG curve(n=1.4)


L 𝑉𝑉𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 90 0.306 80 0.277 70 0.251

Vt roll off

4) Ion/Ioff LOGARITHMIC PLOT OF ID-VG(at Hight VDS)

𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜 = 11.9𝑛𝑛𝑛𝑛

𝐼𝐼𝑜𝑜𝑡𝑡 = 1𝑚𝑚𝑛𝑛

𝐼𝐼𝑜𝑜𝑡𝑡𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜

= 84033.61

5) EFFECT of DIBL We observed ID-VG curves at low VDS and high VDS to observe the effect of drain induced barrier lowering. We observed the following plots:

90nm 180nm

DIBL is a short channel effect which causes the drain voltage to take a larger control of the drain current as the length shortens. We observe that for this length, the gap between the two current plots is much higher than that of a 180nm device.

6) Gate Leakage current We observe Gate leakage current for a low VDS. We turn on the Direct Tunneling model in our Physics section to observe this effect:

IG-VG curve

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑛𝑛𝐶𝐶 𝑎𝑎𝐶𝐶 𝑉𝑉𝐺𝐺 = 0: 2.21 × 10−17𝑛𝑛

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑛𝑛𝐶𝐶 𝑎𝑎𝐶𝐶 𝑉𝑉𝐺𝐺 = 1.2𝑉𝑉: 1.374 × 10−11𝑛𝑛

7) FAMILY OF ID-VD curves: We observed ID-VD curves at VG = 0.4, 0.6,0.8,1,1.2V

We observe that with increasing VG, ID-VD family of curves rises upwards, because the current increases with rising VG.

8) FAMILY OF ID-VG curves: We observed ID-VG curves at VD = 0.4, 0.6,0.8,1,1.2V

We observe that with increasing VD, ID-VG family of curves rises upwards as the current increases with rising VD.

9) Low-field mobility:

We plot mobility by distance for low VDS(VDS = 50mV) and observe the mobility in the channel. So, we take a X-cut near the channel to find out the low field mobility.

We observe a maxima in the channel region in the mobility curve. That is the value of low field mobility required.

𝐿𝐿𝐿𝐿𝐿𝐿 − 𝑓𝑓𝑓𝑓𝐶𝐶𝑓𝑓𝑓𝑓 𝑚𝑚𝐿𝐿𝑚𝑚𝑓𝑓𝑓𝑓𝑓𝑓𝐶𝐶𝑚𝑚 = 426𝑐𝑐𝑚𝑚2/𝑉𝑉 − 𝑠𝑠

10) RSD and ΔL We observed Ron for different VGS at different values of L(70nm, 80nm, 90nm) and plotted fit curves to obtain RSD and ΔL. VGS L Ron

0.4 70 3143.258 80 3626.698 90 4123.569

0.6 70.0 1276.494 80.0 1413.317 90.0 1584.811

0.8 70.0 868.3721 80.0 964.6674 90.0 1039.2917

1 70.0 707.9145 80.0 750.469 90.0 792.8202

1.2 70.0 3143.258 80.0 3626.698 90.0 4123.569

𝑅𝑅𝐷𝐷𝐷𝐷 = 414𝛺𝛺

∆𝐿𝐿 = 25.459𝑛𝑛𝑚𝑚

11) Effective Mobility vs Effective Electric field We plot the effective mobility by effective electric field in the channel by turning on the effective mobility option CurrentPlot { PMIModel ( Name="EffectiveMobility" Start=(-0.033,0,0) ) } At high VDS (1.2V), we observe the following plot.

We observe that the effective mobility decreases at low fields, and increases at high fields.

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