questasim training in mohali
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QUESTASIM Training in Mohali
E2MATRIXCALL: +91 9056501501,9915525860WEB: WWW.E2MATRIX.COMEMAIL: [email protected]
E2MATRIX
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Outline Command Line Simulation
◦ Compile and Simulate◦ Add Signals to Wave◦ Applying Inputs
Interactive Simulation
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Command Line Simulation Make sure Modelsim exists in the path by doing the following◦Windows:
◦ Start run -> cmd◦ In cmd window:
vsim -version◦Linux:
◦ In any shell: vsim -version
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Command Line Simulation Create VHDL file
◦ Edit the file my_demo1.vhd◦ Insert the text and save
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY andgate IS port (a, b: in std_logic_vector(2 downto 0); c: out std_logic_vector(2 downto 0) ); END ENTITY;
ARCHITECTURE behav OF andgate ISBEGIN c <= a and b; END ARCHITECTURE;
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Compile and Simulatevlib work
vcom <VHDL files>
vsim <top level>
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• vlib: creates a library to compile and simulate the code with
• vcom: compiles VHDL files, the files should be ordered in a hierarchal way [leaf level first then top]
• vsim: starts the simulator to simulate the top level module
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Add signals to Wave RMB on any signal in the Objects window Add to Wave signals in Region
Now start applying inputs and monitor outputs
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Applying Inputs RMB on input port force
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• In the “value” field, insert an appropriate value OK
• Apply inputs to other inputs
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Run Simulation Press run button
Monitor the output
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Make FilesOn Unix:
If you changed the code you will have to recompile the design files again. A make file is used to do repetitive compilation and simulation tasks; “Make” knows which files have been edited and automatically compiles only changed files.
ModelSim offers a simple way to automatically generate a Makefile for your design hierarchy. vmake work > Makefile
To recompile code at anytime just type make
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Interactive Simulation File new project Insert project name and location; leave other fields with defaults
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Interactive Simulation In “Add items to the project” window choose “Create new file”
Insert file name Make sure to select VHDL
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Interactive Simulation Create VHDL file
◦ Edit the file my_demo1.vhd◦ Insert the text and save
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY andgate IS port (a, b: in std_logic_vector(2 downto 0); c: out std_logic_vector(2 downto 0) ); END ENTITY;
ARCHITECTURE behav OF andgate ISBEGIN c <= a and b; END ARCHITECTURE;
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Compile VHDL files Select the file RMB compile selected
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Simulation Simulate menu Start Simulation
Expand work library and select andgate OK
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