Quantum Cellular Automata

Final Project Report

Apoorv KhurasiaPulkit Gambhir

May 22, 2006

Abstract

Our project involved the study of next generation paradigms ofcomputation. In particular, our area of interest was nano-scale computingand the various materials or techniques we may use to achieve the same.

We began with the study of Carbon Nano-tubes and then moved on to thestudy of Quantum Cellular Automata , which became our primary focus in

the project. This report is written with a twofold purpose, firstly tosummarize what all major work has been done in the area of Quantum

Cellular Automata to date and secondly to document our efforts inextending this given knowledge.

Contents

1 Introduction 5

2 Basics of a QCA 72.1 Quantum Wells, Boxes and Dots . . . . . . . . . . . . . . . . 72.2 From Dots to Cells . . . . . . . . . . . . . . . . . . . . . . . . 102.3 Cell Polarization and Binary Encodings . . . . . . . . . . . . 112.4 Transmitting Information . . . . . . . . . . . . . . . . . . . . 13

2.4.1 Line Saturation . . . . . . . . . . . . . . . . . . . . . . 14

3 From Wires to Logic 173.1 Making crossing coplanar . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Rotated Cells and Inverter chains . . . . . . . . . . . . 183.1.2 Coplanar Wire Crossing . . . . . . . . . . . . . . . . . 19

3.2 Logical Operations on the Encoded Information . . . . . . . . 203.2.1 Negation . . . . . . . . . . . . . . . . . . . . . . . . . 213.2.2 Higher Arity functions: Majority function . . . . . . . 223.2.3 Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 Dealing with Numerals . . . . . . . . . . . . . . . . . . . . . . 243.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Clocked Quantum Cellular Automata 264.1 Molecular Quantum Cellular Automata . . . . . . . . . . . . 26

4.1.1 Single molecule response . . . . . . . . . . . . . . . . . 264.1.2 Cell to cell response . . . . . . . . . . . . . . . . . . . 28

4.2 Effects of external field . . . . . . . . . . . . . . . . . . . . . . 294.3 Inducing information flow . . . . . . . . . . . . . . . . . . . . 304.4 More on clocking . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Regular Designs based on Quantum Cellular Automata 355.1 Designing a QCA FPGA . . . . . . . . . . . . . . . . . . . . . 35

5.1.1 Basic Logic Block . . . . . . . . . . . . . . . . . . . . 355.1.2 Inter-connect Design . . . . . . . . . . . . . . . . . . . 375.1.3 Some untackled issues . . . . . . . . . . . . . . . . . . 39

5.2 Designing a QCA RAM . . . . . . . . . . . . . . . . . . . . . 40

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5.2.1 Top Level Design . . . . . . . . . . . . . . . . . . . . . 405.2.2 QCA Implementation . . . . . . . . . . . . . . . . . . 40

5.3 Combining RAMs and FPGAs . . . . . . . . . . . . . . . . . 42

6 Basic synchronous elements : Latches and Flip-Flops 436.1 Building a D-latch . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.1 Traditional Design . . . . . . . . . . . . . . . . . . . . 436.1.2 QCA Implementation . . . . . . . . . . . . . . . . . . 44

6.2 Building a D-flipflop . . . . . . . . . . . . . . . . . . . . . . . 466.2.1 Traditional Design . . . . . . . . . . . . . . . . . . . . 466.2.2 QCA Implementation . . . . . . . . . . . . . . . . . . 47

6.3 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . 48

7 Extending synchronous designs : Building a counter 497.1 Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 507.2 A different approach . . . . . . . . . . . . . . . . . . . . . . . 517.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.3.1 Further Work . . . . . . . . . . . . . . . . . . . . . . . 53

Bibliography 57

2

List of Figures

2.1 Wave functions for the one dimensional Quantum Well prob-lem for a proton. (width of the well is 3.65fm) . . . . . . . . 8

2.2 Wave functions for the one dimensional Quantum Well prob-lem for a proton. (width of the well is 3.65fm) . . . . . . . . 9

2.3 Symmetric state of a proton in a box of height 25MeV andside 3.65fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Anti-symmetric state of the quantum dot in figure 2.3 . . . . 112.5 A Quantum Cell for QCA . . . . . . . . . . . . . . . . . . . . 122.6 The two ground states for the system (labelled P = ±1) in

the absence of an external Electric Field. . . . . . . . . . . . . 132.7 The cell-cell response function with t = 0.3meV . . . . . . . . 132.8 A Line of interacting Quantum Cells. . . . . . . . . . . . . . . 142.9 Response of a line of cells. . . . . . . . . . . . . . . . . . . . . 142.10 The response of a line of cells for a different value of tunneling

energy parameter. The driver cell is at 1st location. . . . . . . 152.11 The variation of Psat with tunneling energy parameter. . . . . 15

3.1 A Quantum Cell rotated by 45◦. It is similar in all otherrespects to the one shown in fig 2.5. . . . . . . . . . . . . . . 18

3.2 Representing logical states in rotated cells . . . . . . . . . . . 183.3 An inverter chain and the variations in the cell polarization

with distance(no. of cells) from driver . . . . . . . . . . . . . 193.4 Wire converters . . . . . . . . . . . . . . . . . . . . . . . . . . 193.5 Coplanar wire crossing in QCA . . . . . . . . . . . . . . . . . 203.6 The results of simulation on the circuit of Fig. 3.5 . . . . . . 213.7 The implementation of an inverter gate in QCADesginer. . . 213.8 The simulation results on the inverter shown in Fig. 3.7 . . . 223.9 The implementation of a majority gate in QCADesginer. . . . 223.10 The simulation results on the majority gate shown in Fig. 3.9 233.11 The layout of a XOR gate. . . . . . . . . . . . . . . . . . . . . 233.12 The implementation of a XOR gate in QCA. . . . . . . . . . 243.13 The implementation of a full adder in QCA. . . . . . . . . . . 243.14 Unoptimized and optimized full adder . . . . . . . . . . . . . 25

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4.1 1, 4-diallyl butane radical cation . . . . . . . . . . . . . . . . . 274.2 1, 4-diallyl butane radical cation in various states of polarization 274.3 Single molecule response : the setup . . . . . . . . . . . . . . 284.4 Single molecule response . . . . . . . . . . . . . . . . . . . . . 284.5 The bistable ground state of the molecular QCA cell . . . . . 294.6 Cell-cell response . . . . . . . . . . . . . . . . . . . . . . . . . 294.7 Electric field applied to a single molecule . . . . . . . . . . . . 304.8 Arrangement used for clocking of Quantum Cellular Automata 314.9 The 4-phase clocking signal . . . . . . . . . . . . . . . . . . . 314.10 Resulting electric field produced at QCA surface on applica-

tion of the clocking signal shown in figure 4.9 . . . . . . . . . 324.11 Spatio-temporal evolution of states in a clocked regime . . . . 33

5.1 6-pass transistor used in traditional FPGA’s . . . . . . . . . . 375.2 First-cut design . . . . . . . . . . . . . . . . . . . . . . . . . . 385.3 2x2 and 3x3 connect block . . . . . . . . . . . . . . . . . . . . 395.4 Memory cell with a loop . . . . . . . . . . . . . . . . . . . . . 405.5 4 bit wide RAM with 4 addressable words . . . . . . . . . . . 415.6 QCA cell layout of RAM module . . . . . . . . . . . . . . . . 41

6.1 Truth table for a gated D-latch . . . . . . . . . . . . . . . . . 436.2 Traditional design of a D-latch . . . . . . . . . . . . . . . . . 446.3 Latched wire . . . . . . . . . . . . . . . . . . . . . . . . . . . 446.4 Simulations of the latched wire . . . . . . . . . . . . . . . . . 456.5 D-latch circuit diagram . . . . . . . . . . . . . . . . . . . . . 456.6 QCA layout of D-Latch . . . . . . . . . . . . . . . . . . . . . 466.7 Simulation results of the D-Latch . . . . . . . . . . . . . . . . 466.8 Negative edge triggered D-flip flop design 1 . . . . . . . . . . 476.9 Negative edge triggered D-flip flop design 2 . . . . . . . . . . 476.10 Negative edge triggered QCA based D-flip flop . . . . . . . . 486.11 Simulation results of D-flip flop . . . . . . . . . . . . . . . . . 48

7.1 Binary counter or bit flipper . . . . . . . . . . . . . . . . . . . 497.2 Bit flipper QCA circuit . . . . . . . . . . . . . . . . . . . . . 507.3 A different way to think of synchronous circuits . . . . . . . . 517.4 NI +OI and OI.NI . . . . . . . . . . . . . . . . . . . . . . . 537.5 CS.OI.NI and CS.(NI +OI) . . . . . . . . . . . . . . . . . 547.6 CS.(NI +OI) + CS.OI.NI . . . . . . . . . . . . . . . . . . . 557.7 Next state state connected back to current state, completing

the loop of fig. 7.6 . . . . . . . . . . . . . . . . . . . . . . . . 567.8 Simulation results of circuit shown in fig. 7.6 . . . . . . . . . 56

4

Chapter 1

Introduction

This report is a result of a one semester long study and experimentation(through simulations) by the authors at the Indian Institute of Technol-ogy, Delhi under the supervision of Dr. Kolin Paul. This report aims atintroducing to the reader a new paradigm for computation - one that isof Quantum Cellular Automata (inter-changeably referred to as QCA fromnow on). This field is a wonderful and exciting blend of Computer Scienceand Physics.

There is a constant demand for developing faster (and hence often smaller)digital computing components today. Over the past few years the comput-ing hardware industry and chip manufacturers in particular have tried toachieve these small scale hardware devices by almost a brute force scalingdown of the involved components. Thus one saw the development of suchthings as TFTs (Thin Film Transistors) and a whole range of Thin FilmDesign innovations aimed only at one thing - to scale down the existingcomponents and save space. In this process both success and failure wereachieved. The success was an achievement of feature sizes of 60nm, and thedevelopment of commercial hardware such micro-controllers and processorsbuilt using such tiny devices. The failure was that the power leakage asdevice sizes shrunk down, started to grow exponentially. About 5 years ago,switching power leakage was so small that researchers almost neglected theissue completely but today with the tiny chips we have, power dissipationis a major headache. At feature sizes mentioned above, power loss due toswitching alone is reaching values of up to 50%.

However, the story does not end here, there are bigger evils to be tackled.Even if we were able to come up with schemes to ebb this loss of power, itwould not suffice. The reason being the fact that as device dimensions scaledown, the variation between two transistors produced by the same processbecomes serious enough to hamper the scalability and hence the usabilityof the device. Perhaps even more threatening is the fact that QuantumEffects are beginning to show up now. Going any further below this scale

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would require researchers to develop knowledge about high power losses andbuilding up and controlling very large Electric Fields capable of damagingthe device. To add to this, quantum effects mean a very high probability ofelectrons tunneling through the wires and other devices thus creating moretroubles for the already troubled scientists. The time is therefore apt, to lookelse where for newer ways of doing things, in short to look beyond silicon.In Quantum Cellular Automata we explore one such paradigm which hasshown quite some potential over the past decade.

This report starts by firstly delving into some quantum mechanics andin particular talking about quantum dots. We then introduce the conceptof a Quantum Cellular Automata and the various interesting properties itdisplays. We then move on to the design of basic building blocks of digitalcircuit design using Quantum Cellular Automata wherein we explore somethings such as quantum wires, inverters and majority gates. After lookingat some of these basic designs, we go on to explore the concept of clockingwith reference to Quantum Cellular Automata and the build up of very basicsynchronous machinery in terms of a shift register. We then discuss a coupleof large regular designs such as ROMs and FPGAs that may potentiallybe built using these automata. Finally, we describe our own efforts towardextending the work in synchronous circuits using QCA’s where in we discusssome synchronous modules we had success in creating and also discuss somedifficulties experienced in the same.

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Chapter 2

Basics of a QCA

QCAs or Quantum Dot Cellular Automata were introduced by Lent et alin the early 90s. They consist of an array of several Quantum Dots in closeproximity. We shall describe the basics of a Quantum Dot in the followingsection.

2.1 Quantum Wells, Boxes and Dots

One of the first things that one does in a basic Quantum Mechanics course isto solve the Schrodinger equation for a single particle in a single dimensionalpotential trap with infinite height (also called a Quantum Well). The waveequation for this problem is

∂2ψ(x)∂x2

+2µE~2

ψ(x) = 0 (2.1)

assuming the well dimension to be a.The boundary conditions for the equation are given by :

ψ(x = 0) = 0 (2.2)ψ(x = a) = 0 (2.3)

The normalized solutions for this equation are well known

ψn(x) =

√2a

sin(nπ

ax) where n is the principal quantum number. (2.4)

and are plotted in Figure 2.1.If the height of the well is made finite then the particle can tunnel out of

this well and can get ‘lost’. The Schrodinger equation for this case becomes

∂2ψ(x)∂x2

+ k2ψ(x) = 0 for |x| < a

2(2.5)

∂2ψ(x)∂x2

+ κ2ψ(x) = 0 for |x| ≥ a

2(2.6)

7

Figure 2.1: Wave functions for the one dimensional Quantum Well problemfor a proton. (width of the well is 3.65fm)

while the boundary conditions change to the following

limx→− ∞

ψ(x) = 0 (2.7)

limx→ ∞

ψ(x) = 0 (2.8)

with the additional requirements of continuity and differentiability of ψ(x)at x = −a

2 and x = a2 . The solutions for this equation are now a little tricky.

For the symmetric case (when ψ(x) is a symmetric function of x) they are

ψ(x) = A cos(kx) for |x| < a

2(2.9)

ψ(x) = B exp(−κ|x|) for |x| ≥ a

2(2.10)

tan(ka

2) =

k

κ(2.11)

And for the anti-symmetric case one has

ψ(x) = A sin(kx) for |x| < a

2(2.12)

8

ψ(x) = B exp(−κ|x|) for |x| ≥ a

2(2.13)

cot(ka

2) = − κ

k(2.14)

These wave functions are plotted in Figure 2.2. Equations like (2.11) and(2.14) determine the allowed solutions for the well and hold only when E <V0. When E > V0 all states are allowed and we say that the particle is ‘free’.

Figure 2.2: Wave functions for the one dimensional Quantum Well problemfor a proton. (width of the well is 3.65fm)

Now consider a particle in a square well. In this case the Schrodingerequation is two dimensional and its solutions can obtained by the separationof variables method.

Ψ(x, y) = ψ(x)ψ(y) (2.15)

We already know the values of ψ(x) and ψ(y) from Equations (2.9),(2.10), (2.12) and (2.13) we just need to substitute them in Equation (2.15)to get the wave function for the two dimensional case. Figures 2.3 and 2.4show the wave functions of the particle in a square trap.

A Quantum Dot is a three dimensional extension of the mentioned wells.The reader should note that the type of the dot may be spherical for whichthe solutions are in terms of the Legendre polynomials, or a cube for which

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Figure 2.3: Symmetric state of a proton in a box of height 25MeV and side3.65fm

we have, as above, sinusoidal solutions. Whatever be the case, the importantproperty of a quantum dot is that motion within it is restricted in all thethree spatial dimensions. A particle in such a dot cannot move freely. Butsince the potential at the boundaries is still finite there is a finite probabilitythat the particle tunnels outside and is lost from the dot. For our purposeswe need a quantum dot which can trap an electron.

There are many ways to implement an electron Quantum Dot. Im-plementations with semiconductors are most common and they are mainlyused in Quantum Dot Lasers, which in themselves are a very active area ofresearch today. Implementations with organic molecules have also been re-ported and are particularly useful for reasons discuused in chapter 4. Oncewe have a Quantum Dot ready we can move to the next level of abstractionand forget how it was implemented. This shall be our general philosophyof working wherein we try to understand a structure, build an appropri-ate model for the structure, then work with the abstraction of the modelforgetting about the actual underlying structure.

2.2 From Dots to Cells

Moving on, now we shall generate a Quantum Cell from such QuantumDots which we have seen in the previous section. Such a cell consists of

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Figure 2.4: Anti-symmetric state of the quantum dot in figure 2.3

four quantum dots on the corners of a square and one central dot (Fig.2.5). The cell is occupied by two electrons. The electrons are free to tunnelfrom one dot to another but they cannot tunnel through the cell along thepaths shown in the figure. We generally associate tunneling parameterst and t′ for tunneling between boundary dots and between boundary andcenter respectively. A good choice of these values is generally associatedwith t = t′/10 = 0.3eV .

It is also pertinent to point out there is nothing holy about the givenconstruction of the quantum cell. It will become clear in the ensuing sec-tions that the only reason for choosing this particular design is to have aconfiguration with a bistable ground state. If a design made with differentnumbers of dots or with different geometries may also achieve the same, wecan equivalently build our model around that structure.

2.3 Cell Polarization and Binary Encodings

Since there are five positions available and only two electrons to occupythem, there are 5C2 configurations available for a single cell, classicallyspeaking. Quantum mechanics however ensures that there is in fact a contin-uum of possibilities with the electronic wave functions being delocalized overthe quantum dots. It is helpful to define a quantity P called polarizationand associate it with a cell.

P =(ρ1 + ρ3)− (ρ2 + ρ4)ρ0 + ρ1 + ρ2 + ρ3 + ρ4

(2.16)

11

Figure 2.5: A Quantum Cell for QCA

where ρi = 1 if the ith dot is occupied and 0 otherwise.If the cell is isolated, which means that there are no fields present in its

vicinity, then the observable value of P is 0. This is because any state Awhich has a polarization PA also has a counter state A′ with polarization−PA. Now since both these states are symmetric (the only thing that canbreak their symmetry is an electric field) they occur with equal probabilityp and hence their superposed state has an expected value of polarizationpPA + p(−PA) = 0. Now since all states which have a non-zero polarizationhave their counterpart, the net polarization in case of isolated cells is zero.

When the cell temperature is low (≈ 0 K)the tunneling probabilitiesdecrease and Coulombic term in the cell hamiltonian become dominant andhence the probability that the system occurs with the electrons in the an-tipodal sites (Fig.2.3) increases. This essentially means that at sufficientlylow temperatures where perturbation due to thermal effects is negligible, ifwe can tune tunneling parameters correctly, we can have a bistable groundstate; which consists of the electrons at the opposites of the diagnol. Thishappens because under such conditions, electrostatic repulsion is the onlyimportant quantity. These two states are equi-probable when the cell is inisolation (they are symmetric as the dot is isolated and there is no ElectricField in its proximity) and one has a polarization −1 and the other has apolarization 1. We can label them as binary zero and one respectively. Thuswe have shown the way in which binary information can be stored in sucha Quantum Dot Cell.

Notice that the analysis assumes a very low temperature which is nota possibility for practical computability. However this is not a very seriousdrawback as it is fairly easy to increase our working temperature withoutlosing the bistable ground state. This can be done by the appropriate tun-ing of the tunneling parameters from one dot to the other within the cell,which in turn is a highly implementation dependent matter. Also anotherassumption that we make hence forth is that although it is possible to haveintra-cell tunneling, the probability of inter-cell tunneling is low enough to

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Figure 2.6: The two ground states for the system (labelled P = ±1) in theabsence of an external Electric Field.

be completely ignored.

2.4 Transmitting Information

Once information is available to us we must be able to transmit it as well.Consider two Quantum Cells A and B adjacent to each other. Now supposewe have somehow fixed the polarization of A to P and lets call this config-uration S (we will see later how this can be done). What will happen tocell B? Now this seems to be a case of broken symmetry and our intuitiontells us that the most probable state for B is S now. That is indeed thecase provided we control tunneling. Lent et al have shown that the cell-cellresponse function is abrupt and non-linear. The cell-cell response functionfor two cells is defined as variation in the polarization of one with respectto the other’s. In this case it would be PA as a function of PB see Figure2.7 below.

Figure 2.7: The cell-cell response function with t = 0.3meV

We can indeed see that the response function is highly non-linear. Thetype of function ensures that even a slight amount of polarization in thedriver cell (which is A here) can fix the state of its adjacent cells. It is ahighly error-correcting type of response function which immediately restoresthe polarization to fixed rails of ±1. Now we know that our dot can trans-mit the information stored in it without any passage of current through it.This is the most fundamental difference between a QCA circuit and normalelectronics circuit. In the latter information travels through passage of cur-rent while in the former it is through the Electric Field created by the cell’s

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polarization. We can now expect to keep a driver cell in an array and itwill drive the whole array for us. Figure 2.8 shows schematically a line oftwo-electron quantum cells. The distance between the cells is three timesthe near-neighbor distance between dots in a single cell. We are interestedin the question that if the polarization of the ‘leftmost’ cell is fixed to sayP = +1, then is the saturation sufficient enough to lock the whole array intothe same polarization state. If this occurs then we have a ‘wire’ available tous which is capable of transmitting information from one place to another.

Figure 2.8: A Line of interacting Quantum Cells.

2.4.1 Line Saturation

Figure 2.9 shows the polarization as a function of cell number for a line often cells. The polarization of cell 1 is set to values P = 0.9, 0.8, 0.6, 0.2 and0.02, and the ground state of the electrons in the remaining nine cells iscalculated. The cell considered has t = 0.3meV and t′ = t

10 . Note thatin figure 2.9 for the shown values of t and t′ the polarization reaches veryquickly up to 1.0 from cell 2 itself. This re-iterates the error correctingnature of the wire.

Figure 2.9: Response of a line of cells.

If the tunneling energies, t and t′, are increased then the two-particleground state wave function in each cell becomes less and less localized in theantipodal sites and eventually we loose the information we were supposed totransmit. Figure 2.10 shows the variations in the polarization of the line ofcells for different values of t and t′. Notice that in both cases the polarization

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saturates to a certain value Psat, quite far away from the driver cell. Thelast cell always has a slightly lower (in case of positive driver polarization)polarization as it has only one near neighbor. The quantity Psat actuallydepends on the physical parameters in the cell and on the distance betweenthe cells. For still larger values of t and t′ one can completely loose theinformation of the driver cell (Psat = 0).

Figure 2.10: The response of a line of cells for a different value of tunnelingenergy parameter. The driver cell is at 1st location.

Figure 2.11: The variation of Psat with tunneling energy parameter.

Thus we have seen that information can indeed be transmitted usingQuantum Dot Cells provided we choose our cells in a smart way and con-trol the tunneling. All the above discussion is a lot simplified case sincewe have assumed that entropy effects are absent. That is indeed the casewhen the temperature of the cells is 0K. At non-zero temperatures we maysee the presence of other excited states too. But as mentioned earlier, by

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appropriate setting of tunneling parameters, we can increase our workingtemperature as well.

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Chapter 3

From Wires to Logic

In the previous chapter we discussed how one can encode and transmit in-formation using Quantum Dots arranged in a Quantum Cell. It would behighly desirable to be able to process the information using QCA based cir-cuits rather than decoding this information and using the traditional semi-conductor based circuits to process it. The latter approach, of course defeatsthe purpose of introducing this paradigm in the first place itself.

In the current chapter we shall first deal with the primary logical oper-ations (inversion, conjunction and disjunction) on the encoded information.Then we shall build some circuits to perform the basic arithmetic operationsof addition, subtraction and multiplication. The only way to test these cir-cuits, before realizing them on the materials, is through simulation. Thesimulator, most widely used, is the QCADesigner. It is an Open SourceSoftware freely available from http://www.qcadesginer.ca . Our own cir-cuit designing and simulation has been done using this tool.

3.1 Making crossing coplanar

Today’s complicated electronic circuits involve a huge amount of wiring.Even the less complicated PCB’s these days may involve over ten layers ofwiring. This is a major problem, not because it is impossible to manufac-ture but because it is expensive to do so. A single layered board will bea lot cheaper than a multi-layered board and one of the optimizations inPCB design is to design circuits with minimum layers, typically done usingalgorithms from the area of planar graph drawing. Moreover, great caremust be taken to ensure these overlapping wires do not short as that canlead to uncertain behavior and possible circuit damage. An important is-sue, as iterated and re-iterated several times in this report is that in theQCA paradigm we are not dealing with currents, instead we are dealingwith electrostatic charges. So it is indeed possible to do things which haveno equivalent in traditional designs. One such possibility is the coplanar

17

crossing of wires which we shall demonstrate in this section. This idea issimple yet very powerful as it potentially means making circuit layouts lesscomplicated and easier to manufacture.

3.1.1 Rotated Cells and Inverter chains

In the previous chapter we discussed a Quantum Dot Cell of a particulartype and we used it to form a ‘wire’ in which cells copy the state of theiradjacent cells so as to make the state of the whole line of cells collapse to theground state. There is a yet another way to place these cells. Consider thedesign of the Figure 3.1. It is the same cell as of Figure 2.5 but now it hasbeen rotated by 45◦. Figure 3.2 shows the binary encoding representationfor these kinds of cells.

Figure 3.1: A Quantum Cell rotated by 45◦. It is similar in all other respectsto the one shown in fig 2.5.

Figure 3.2: Representing logical states in rotated cells

Now consider two such cells adjacent to each other say A and B. Nowlet us fix the state of A to some polarization P = ±1.0 and let us label thestate of A by S. We shall denote the negation of S by S. Intuitively oneshall expect that the state of B shall become S. That is indeed the case.So if we build a line of such cells then the polarization shall alter for everyalternate cell. We shall refer to such a line as an inverter line. Figure 3.3shows such a line of Quantum Dot Cells and the variations in its polarizationwith respect to the cell distance (measured in terms of the number of cellsfrom the driver cell). Provided we know this length we can safely predictthe output signal we obtain at the other end for any input on the drivercell. An inverter chain is another useful way of relaying information fromone point to the other. Moreover, just like the binary wire it too is error-correcting in nature. But, in order to use it in conjunction with our normal

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Figure 3.3: An inverter chain and the variations in the cell polarization withdistance(no. of cells) from driver

binary wire, we require a way to convert information going down a normalwire into an inverter chain and then convert back. This may be achieved by× to + converters and + to × converters respectively. These converters areshown in figure 3.4 as the red and blue highlighted sections respectively.

Figure 3.4: Wire converters

In general we may observe that if we tap input and output on same side ofthe rotated line, then leaving an even number of rotated cells between inputand output results in the same output as input whereas an odd number ofrotated cells result in inverted output. Ina complementary manner, if wetap input and output on opposite sides of the rotated line, an even numberof cells give inverted output and an odd number yield normal output.

3.1.2 Coplanar Wire Crossing

In this section we shall use the inverter line developed in section 3.1.1 toimplement coplanar wire crossings. The basic idea is quite simple in princi-ple. If we cross a line of rotated cells with one made up of normal cells as in

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Figure 3.5: Coplanar wire crossing in QCA

figure 3.5 then there would be no cross talk between the wires. The reasonis is not too hard to understand intuitively.

Consider the electric field pattern of the rotated cells (see Fig. 3.1). Itshall either point along the z direction (in case of P = 1.0) or along the xdirection (if P = −1.0). In either of the cases this field does not break thesymmetry of the ”normal” cells. So if we can convert a line from +-to-×then essentially we have a solution. The simulation results for this coplanarwires setup can be seen in figure 3.6. It must be noted that although we saidthat tunneling probability between cells is negligible, the fact that coplanarcrossing work implies that the effect of one cell can be felt not only by itsnearest neighbor but also by the cell next to its neighbor. And the effect feltat the neighbor’s neighbor is strong enough to drive the polarization statethrough that cell as well.

3.2 Logical Operations on the Encoded Informa-tion

In this section we will talk about circuits to perform the basic logical op-erations of negation, conjunction and disjunction on the encoded binaryinformation. We shall begin with the simplest of logic operations, negation.

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Figure 3.6: The results of simulation on the circuit of Fig. 3.5

3.2.1 Negation

Negation is fairly simple to achieve as the discussion on wire crossing hasprobably also indicated. There are multiple ways to do it in the QCAparadigm we present a particularly intelligent and intuitive one. This im-plementation is shown in Figure 3.7 and the simulation results are shownin Figure 3.8. Lets understand the circuit. The signal ”comes in” from

Figure 3.7: The implementation of an inverter gate in QCADesginer.

the left, splits into two parallel wires, and is inverted at the point of con-vergence. The design is geometrically symmetric, so inversion of a 1 or a0 occurs with the same reliability. We have mentioned earlier that there isno meaning to talk about coming in of a signal, as there are no currentshere only static charges. But if we have fixed the polarization of one of thecells then the symmetry of the cells adjacent to this cell is broken. The onlydegree of freedom (in a Classical sense) is the one associated with the drivercell. This is what we mean by coming in of a signal. This design of theinverter may be (intuitively) tested out on paper using simple ruling out ofstates. The idea is to look for a state of the system in which the energy of

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Figure 3.8: The simulation results on the inverter shown in Fig. 3.7

the configuration is minimum, that is one in which electrostatic repulsionbetween electrons is also minimized.

3.2.2 Higher Arity functions: Majority function

Figure 3.9: The implementation of a majority gate in QCADesginer.

We have successfully made an inverter in the previous subsection. Nowwe shall focus on conjunction and disjunction. But before we move on tothose functions we should implement a seemingly auxiliary function which ismore easily achievable in this paradigm than the conjunction and disjunctionoperators. This is the Majority Voting Function defined as

M(A,B,C) = AB + BC + CA (3.1)

The Majority gate, as the reader might be aware of, is a programmablelogical function. If one of the input is bound to some fixed value thenthe output is a conjunction or disjunction of the remaining two inputs. Ifsuppose A,B and C are the inputs to M then if C is considered to be theprogram input then

M(A,B,C) = AB when C = 0 (3.2)

M(A,B,C) = AB + B = A + B when C = 1 (3.3)

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Figure 3.10: The simulation results on the majority gate shown in Fig. 3.9

This gate is surprisingly simple to implement using QCAs. It is implementedin Figure 3.9 and the simulation results are shown in Figure 3.10. The imple-mentations of the conjunction and the disjunction functions follow trivially.All one has to do it to bind one of the inputs to a P = −1.0 or P = 1.0depending upon the case of interest.

A very important point to be noticed here, is that the majority functionis a generalized version of the AND and OR gates. It is a three functionwhich when implemented can be be combined with other gates to achievefairly non-trivial circuits particularly easily. One of the challenges for de-signing QCA circuits is to forget about AND gates and OR gates and useMAJORITY gates. Although, we can take a regular circuit and blindly re-place AND’s and OR’s with hard wired MAJORITY gates, this will veryoften give sub-optimal designs. In short, there is a need to come up with al-gorithmic methods to reduce complicated boolean expressions to optimizedimplementations using MAJORITY gates. (Note that Majority + Invertersform a complete logical set equally powerful as AND-OR-INVERT).

3.2.3 Exclusive OR

Figure 3.11: The layout of a XOR gate.

Now that we have seen the implementations and the uses of a major-ity gate as a generator gate for the logical operations of conjunction and

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Figure 3.12: The implementation of a XOR gate in QCA.

disjunction. Now we must concentrate on some more complex functions.Consider an Exclusive OR gate. From basic knowledge of Digital circuitswe have an implementation of XOR in terms of the AND and OR gates.We will translate it to the QCA design now (without trying to optimize onmajority gates). The implementation is shown in Figure 3.12

3.3 Dealing with Numerals

Figure 3.13: The implementation of a full adder in QCA.

Handling boolean information and being able to process it is not quitethe only thing our computing paradigm should be capable of. Indeed itshould be able to handle other complex operations like addition, subtraction(comparison) etc. Once we have made a XOR gate we should not have anyproblem building a full adder using it. The implementation is shown in Fig.3.13.

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In order to appreciate the comment about optimization of logic circuitsfor using majority gates mentioned in a previous section, it is perhaps in-teresting to point out that it took over six years for an optimized version ofan adder to come up; after the original paper on QCA’s had presented animplementation based on blind translation of AND’s and OR’s to hardwiredMAJORITY gates. Clearly even optimizing trivial circuitry like this one isa non-trivial task. The two designs are shown in figure 3.14; while one needs5 M-gates and 3-NOT gates the other just 3-M gates and 2-NOT gates.

Figure 3.14: Unoptimized and optimized full adder

3.4 Conclusion

Some of the implementations presented henceforth may appear quite com-plicated in terms of the number of cells required. But the actual work ofimplementation is not very cryptic once we have with us the modular knowl-edge in terms of building basic gates, doing wire crossing etc. which we havetried to gain in this chapter. Also as we develop more and more simple mod-ules such as multiplexers, decoders etc., later on we can use them as readymade blocks in more complicated and involved circuits. The real untackledproblem that remains however is the one dealing with optimized circuitryfor MAJORITY gates. If Quantum Cellular Automata are indeed the com-puting paradigm of the near future, this problem will only gain more andmore in importance.

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Chapter 4

Clocked Quantum CellularAutomata

In this chapter we discuss the concept of a clock as relevant to QuantumCellular Automata . Although this concept of clocking is quite different fromthe one we use in traditional circuits, the underlying philosophy of the clockremains unchanged, it being a mechanism to synchronize flow of data in asystem. Before we get into the details of clocking, we discuss the concept ofmolecular a QCA which we will use later to build our clocking model.

4.1 Molecular Quantum Cellular Automata

A molecular Quantum Cellular Automata is one which is implemented atthe molecular level. This requires a molecule in which charge is localizedon specific sites and can tunnel between those sites. The molecules used ingeneral have one or more redox centers and one or more bridging ligandsconnecting these centers. The redox centers play the role of the quantumdots in this case and the bridging ligands act as the tunneling barriers. Onesuch molecule is 1, 4-diallyl butane radical cation which is shown in figure 4.1.It consists of two allyl groups connected by a butyl bridge. There is a singleunpaired electron that can tunnel through the barrier and provide variousconfigurations just as is required in a QCA cell. Under the absence of anexternal field, the electron is delocalized over the molecule occupying boththe redox centers, but an external charge or field can break this degeneracyas can be seen in figure 4.2, wherein (b) is the normal state of the moleculeand (a) as well as (c) result when degeneracy is broken.

4.1.1 Single molecule response

A single molecule response refers to the state of polarization (measured asdipole moment of the molecule) when an external charge is moved alongside

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Figure 4.1: 1, 4-diallyl butane radical cation

Figure 4.2: 1, 4-diallyl butane radical cation in various states of polarization

the molecule (the nature of the external charge is also measured as an ex-ternal dipole moment). A schematic illustration depicting this can be seenin figure 4.3. We wish to plot the response of our molecule with respect tothe state of the driver. We would want this response to be highly non-linearfor good switching.

It should be clear why we require such a response. If we were to puttwo of these molecules side by side in parallel, then essentially we’d get asystem of 4 quantum dots very similar to our originally defined notion of aquantum cell. Then if the single molecule response is highly non-linear andclose to a steep sigmoidal or better still a step function, it would mean thatjust placing the molecules close to each other would break their individualdegeneracies. What we would obtain is a system with two bistable groundstates in which the electrons occupy opposite corners. This is precisely thekind of system we are trying to build. The response is in fact plotted infigure 4.4, and is highly non-linear and step function like.

Theses results have all been obtained by Hartree-Fork based quantum

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Figure 4.3: Single molecule response : the setup

Figure 4.4: Single molecule response

mechanical simulations, and they can be interpreted to mean that we canindeed build a system with a bistable ground state by placing two singlemolecules next to each other. The bistable ground states are shown infigure 4.5. To conclude the construction however we will also have to showthe inter-cell response function to be equally non-linear and step functionlike. Once we achieve this we can have a QCA cell which is composed ofonly two such molecules.

4.1.2 Cell to cell response

To complete our molecular QCA construction we need to show a cell to cellresponse which will ensure that we can build a binary wire out of it andtransmit information through that wire. This is indeed possible as is shownby the cell to cell response which is plotted in figure 4.6. This time thequantity we use to measure the response is the double molecule quadruplemoment about the center of the system. We can in fact do one step betterusing our simulations and show the working of a majority gate based on

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Figure 4.5: The bistable ground state of the molecular QCA cell

molecular QCA, although we are not including the relevant simulation datafor the same in this report.

Figure 4.6: Cell-cell response

4.2 Effects of external field

The structure of a molecular Quantum Cellular Automata cell studied inthe previous section leaves us with a rather important lesson, it does notmatter what the fine structure at the implementation level is, as long as itit satisfies certain conditions such as the existence of a bistable ground stateand the ability to drive neighboring cells, each of those structures may bea valid implementation for our abstract QCA model. In this structure onceagain the type of structure we use is changed slightly so that we can exploitsome extra new properties to develop the concept of clocking.

The type of molecule we now use has been illustrated in figure 4.7. It isessentially one with three redox centers rather than two but still has only onefree electron. If we do not apply a field, the electron wave function will bedelocalized over all the three sites. However, the figure shows two interestingcases, when we apply an external field in the appropriate direction. In

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Figure 4.7: Electric field applied to a single molecule

one case, the electron is forcefully confined to a single redox site, we labelthis molecular state as the “null” state. In the other case, the electron isforced into the other portion of the molecule where there are two redoxsites, each of which may be occupied with equal probability. Again we havegotten a position equivalent to our original development of molecular QCAcells, wherein an external charge (dipole moment) will be able to breakthis symmetry/degeneracy. Without going into the details, it is intuitivelyobvious that if we were to place two of these molecules in parallel and appliedthe appropriate field, we would obtain a bistable ground state as we didearlier.

In summary the effect of the field on a complete two molecule quantumcell is as follows :

• Under 0 field, the wave functions of the electrons spread over all 6redox sites.

• Underfield pointing vertically upwards (electron attracted downwards),both molecules enter a “null” state and we declare our cell to be inthe “null” state as well.

• Underfield pointing vertically downwards (electron attracted upwards),we get two electrons in four redox centers, whose mutual repulsion foreach other ensures the presence of a bistable ground state, which wemay then treat as our binary zero and binary one.

• As a QCA cell switches state from “null” to non-”null”, it immediatelyacquires the polarization of its neighboring cell due to electrostaticforces. This is the crucial phenomenon we will use for informationflow using clocking techniques.

4.3 Inducing information flow

Consider the arrangement shown in figure 4.8. The idea is to embed verytiny metallic wires below the bed of QCA cells. Then by appropriately

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Figure 4.8: Arrangement used for clocking of Quantum Cellular Automata

controlling the voltage applied in the wires, we aim to create the requisitefield at the surface of the QCA cells in order to cause an information flowthrough a QCA wire. The conductor shown above the cells is grounded andis placed in order to draw the electric lines of force in the y direction, whichis how we require them to be.

Figure 4.9: The 4-phase clocking signal

If we were to apply a four phase clocking signal (fig. 4.9) on the clockingwires, i.e., send such a trapezoidal voltage wave along each wire, with a phasedifference of π/2 between consecutive wires then the electric field producedat the surface of the QCA’s will be roughly sinosuidal as shown in figure4.10. The thresholds indicate that the cells will keep shifting between thelocked and the null states in between separated by the switch states, which is

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basically the indeterminate state in which the wave function of the electronis delocalized all over the molecule.

Figure 4.10: Resulting electric field produced at QCA surface on applicationof the clocking signal shown in figure 4.9

A typical single cycle of the sinosuid will result in a series of state changesof the cell, in the order ...,Locked,Switch,Null,Switch,Locked,.......The dottedcurves in figure 4.10 indicate the time evolved version of the spatial electricfield distribution. This time evolution of the distribution shows that thelocked state is traveling to the right with time, i.e., the switch state justnext to the locked state transforms into the locked state and reads as wellas stores the value of this old locked state, which itself then goes into aswitch mode followed by a null mode and then a switch mode again afterwhich the cycle starts to repeat. The new switch state propagates the bitforward in a similar manner.

The null mode is very important since it ensures that the next bit ofinformation does not interact with the previous bit. It buffers out or shieldsthe next bit from the previous bit. This shielding occurs because when theold bit’s current cell state change from locked to switch, it is vulnerable tochange from the next bit, but the next bits is delayed by a quarter clock byintroducing a null mode in between ensuring that the bits remain mutuallynon-interacting and exclusive.

It is pertinent to point out that the spatial evolution through states fromleft to right, is not the same as the temporal evolution of states of a given cell,this fact is more clearly depicted diagrammatically in figure 4.11 where wemay see that the sequence of states left to right is different from the sequencetop to bottom. The spatio-temporal assymetry in some sense is responsiblefor the transmission of information down the line a buffered manner. Notethat in figure 4.11, switch and release (blue and yellow respectively) referto what we have so far called the switch state; relax (red) refers to what we

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have so far called the null state and hold (green) refers to what we have sofar called the locked state.

Figure 4.11: Spatio-temporal evolution of states in a clocked regime

4.4 More on clocking

We summarize some conclusions that may be drawn from this chapter :

• Clocking in QCA is on the face value very different from clocking inregular CMOS based circuits wherein the clock refers to a periodicsignal on whose edges events occur. However, the underlying philos-ophy remains constant, it is a mechanism to provide synchronisation.It may be used to make events occur simultaneously in time.

• Clocked QCA’s, if implementable, will be able to achieve clock speedswe cannot even imagine regular circuits. This is so because in regularcircuits, clock speed is limited by the power losses at higher switchingrates. In QCA however there is no such restriction, the clock periodmay be limited by one of two things :

1. Relaxation time to reach ground state

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2. Maximum switching rate on a metallic wire (due to inherent ca-pacitive effects)

It is widely believed that the actual bottleneck is the latter of the abovementioned reasons, meaning that we can currently think of circuitsworking in the THz range.

• The clock in QCAs is the only source of power we really need (apartfrom the few bits for which we may need to spend some energy toset constant polarization values); this is therefore also a low energyparadigm. (This statement has to be taken with a pinch of salt becausewe may not in all cases be working at room temperature and willexpend power to cool things down)

• The nature of the QCA clock ensures that consecutive bits are in somesense ‘latched’ from one clocking zone to the next and are also pre-vented from interfering with each other. We therefore have a veryready and natural implementation of a shift register available (ex-plained in more detail in the ensuing chapters).

• A majority of the work in designing QCA clocked circuits will be spentin deciding and laying out the clocking zones . This is necessary toensure data synchronization and correct working of designs.

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Chapter 5

Regular Designs based onQuantum CellularAutomata

In this chapter we explore some regular designs based on Quantum CellularAutomata . By regular designs we refer to digital designs which can be veryeasily scaled up by repeatedly copying a basic unit. We explore two suchregular designs, first that of an FPGA and then that of a RAM.

5.1 Designing a QCA FPGA

The design for an FPGA based on QCA presented in this section is basedon work done at the University of Notre Dame.

The design philosophy is to is to look at the FPGA in two essentiallyindependent portions, the first one is the design of a basic logic block (whichdecides what sort of functionality is possible in the FPGA) and the secondis the design of the inter-connect logic (which decides the what kind offlexibility is possible in the FPGA). Hence we split the discussion of thedesign into these two components.

5.1.1 Basic Logic Block

We have seen some basic digital blocks that are implementable in the QCAparadigm, these include foremost, the majority gate which in turn may beused to implement AND gates as well as OR gates. We also have invertersavailable to us. However the one thing lacking so far in our QCA tool boxis a memory, so our logic block will also be devoid of any memory elementsuch as a flip flop or a latch. Our design choice now reduces to buildinga system which is complete (in the sense of being able to implement anylogic circuit) and also simple to keep it realistic and given both of these

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constraints we also don’t have the luxury of using a memory or a look uptable in the design. We explore various choices below :

1. AND-OR-INVERTBuilding a sea of two-input AND gates and two-input OR-gates seemsa simple design but it is not complete since it cannot be used to imple-ment NOT logic. Thus if we want to use AND gates and OR gates wemust also use INVERTERS. Although at first glance it seems that thisis a good option as it delivers a very natural way to build Sum of Prod-ucts as well as Product of Sums designs, and even the inter-connectlogic seemingly gets simplified. But there is a very big problem withthis choice, the inversion has to be provided in every logic block andneeds to be optional and thus multiplexed. The problem is in the mul-tiplexer, as that design is non-trivial and takes a very large number ofcells. Also conditional multiplexing requires a memory which we donot have. We therefore reject this option.

2. MUXMultiplexers can be used to implement any logic gate, and thus aloneform a complete logical system. But their use in our blocks has twodisadvantages as already stated above :

• They require many more more cells than simple logic gates

• The programming part needs a store or memory which is some-thing we do not have.

3. AND-XORAND-XOR is also a complete logical system. The advantages of thischoice is that it does not need any inverters or any multiplexers, andthus each logic block can be either an AND or a XOR gate. Howeverthe problem is the complexity of the XOR gate in the QCA implemen-tation, it requires a non-trivial implementation. In general, having twodifferent kinds of logic blocks would mean it is harder to come up witha ground layout of the FPGA in order to make the inter-connects easierto design.

4. NORNOR logic alone is complete. The gates are also very simply imple-mented using QCA cells and provide a very simple and elegant logicblock, one with a single NOR gate. However we disregard this optionsince in NOR logic, the natural way to design circuits is in a Productof Sums manner whereas designs are more often presented in a Sumof Products manner.

5. NANDThis option provides the simplicity and elegance of NOR gates along-

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side a natural implementation of Sum of Products design. Hence itis chosen as the logic block design. Our logic block is thus chosen toconsist of a single NAND gate.

5.1.2 Inter-connect Design

Traditional FPGA’s

In traditional FPGA’s, inter-connects typically connect everything to ev-erything in a metallic grid, with a 6-pass transistor at every node in thegrid which can provide optional switching between any two of the wires atthe node. This is depicted diagrammatically in figure 5.1. This design usesan SRAM to program and hold the switches in an appropriate state, whichis something we cannot directly emulate on QCA’s. Hence we look for al-ternate designs that can achieve the same goal without involving memoryunits.

Figure 5.1: 6-pass transistor used in traditional FPGA’s

Emulating the switch

One way to directly map the switch design a transistor may provide tradi-tionally, is to use a MUX-DEMUX pairing to connect any wire to any wire.Typically for a 4 wire node we would therefore require 3 or 4 control signals.This design has a couple of major flaws in it :

1. It needs a storage to remember the control signals.

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2. The design may not be as straight forward as the first glance wouldhave us believe. We would need to ensure that a wire cannot self-loopetc. Hence it is not a trivial design.

3. The multiplexers use too many cells and very large area.

Non-traditional methods

We now present a series of non-traditional methods to do our routing, whichare based on the concepts of QCA clocking, do not require memories andcan provide very useful inter-connect options.

The first-cut design is shown in figure 5.2. It is essentially our wirecrossing as discussed in section 3.1.2, and provides us with a single optionof interconnect at every node that of crossing over two signals without in-terference.

Figure 5.2: First-cut design

The idea is shown in figure 5.3. We essentially lay out the cells as shownin the figure, dividing into various zones (4 in the case of figure I and 9in figure II). Then by choosing certain blocks to be in the null state of theclock permanently, we can effectively take them out of the circuit and obtainthe various inter-connect options that are illustrated at the bottom of thefigures. The 2x2 block provides a lot of flexibility but has some problemswhich are shown in sub-figure I(c). We develop the 3x3 connection blockto overcome precisely this problem. This design methodology can be usedto obtain a 3x2 block on similar lines which does not have the shortingproblems of the 2x2 block and which takes less space than the 3x3 block.

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This extended design can be found in a paper published on QCA FPGAdesign, which is refrenced in the bibliography.

I II

Figure 5.3: 2x2 and 3x3 connect block

5.1.3 Some untackled issues

• Given a design we need to modify known algorithms to decide uponwhich inter-connect zones to activate and which to switch off.

• Given a design, we also need to modify known algorithms for FPGA’sto decide on the ground mapping of the design onto the board.

• A major issue is to ensure all signals reach the appropriate parts ofthe circuit at the appropriate time. For example, two inputs to a gatemust reach at the same time. This problem is tackled by appropriatelyclocking the cells and has not been dealt with in the current design.

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5.2 Designing a QCA RAM

The design of a QCA RAM is a very exciting prospect because firstly it addsa new element into our available QCA modules collection and substantiallyopens up new design possibilities. On a more practical note, since we canclock QCA circuits at very high rates (limited primarily by the rate at whichwe can switch a signal on a metal wire) without worrying at all about powerloss, we can have low power memories that work at clock speeds of 100’s ofGHz and give an incredible high memory density (1.6Gbit/cm2) as well.

5.2.1 Top Level Design

The basic idea is to design a bit storage mechanism. This is done by circu-lating a bit in a closed QCA loop which consists of all four clocking zones,this ensures we don’t lose information. We then need to build extra circuitryaround this loop to allow us to read and write. We also have a select line todecide whether we wish to operate on a memory cell or not. This memorycell is laid out in figure 5.4. We may then put lots of these blocks together

Figure 5.4: Memory cell with a loop

on a regular array, interfaced with appropriate circuits to get a completeRAM block which is usable as a synchronous memory. Such a design of a 4bit data, 4 word RAM is shown in figure 5.5

5.2.2 QCA Implementation

We were able to map the design onto the QCA simulator and produced thefollowing QCA cell layout using 295 cells. We did not try to optimize onthe number of cells and this number can probably be reduced substantiallyby a more clever layout. Our cell layout is shown in figure 5.6.The designshown involves 8 clocking zones from input to output. Due to the nature ofclocking in QCA’s, this means two things :

1. Our RAM cell has a response time of two clock cycles.

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Figure 5.5: 4 bit wide RAM with 4 addressable words

2. There is inherent pipelining of instructions, thus we may give in aninstruction of signal every cycle to the cell, the output comes two cycleslater.

Figure 5.6: QCA cell layout of RAM module

To complete the design of the RAM, we need to further add decoders behindeach of the RAM cells, this can be done fairly trivially and we are notincluding those details here.

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5.3 Combining RAMs and FPGAs

In the section on FPGA design we continually stressed the absence of amemory in our tool kit and avoided all designs which involved the same.However, now that we have also given a RAM design we must defend ourdesign choice for FPGA’s. This is fairly easy to do and the reasons arepresented below :

• The RAM cell design for storing a single bit of information is very tinyif we wish to design a memory of the size of a few GBs. However, forthe purpose of our FPGA, the size is far too large. The RAM cell fora single bit consumes nearly 300 cells whereas we can get a majorityget in less than 10 cells. The complexity is too high for use in a firstcut design.

• Another important fact is that unlike majority gates which may involvea couple of clocking zones, the RAM cell takes up 8 zones on the pathfrom input to output. This will only complicate the already unsolvedproblem of clocking the FPGA appropriately.

In the following chapters, we strip down the RAM cell to obtain a basicD-latch which is far less complicated and involves only 4 clocking zones andhence only a single clock cycle delay. We shall also develop a D-flipflop.These are perhaps better choices for such a design.

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Chapter 6

Basic synchronous elements :Latches and Flip-Flops

Latches and flip flops are the basic building blocks of synchronous circuitdesign and our aim in this chapter is to evolve the design of both usingQuantum Cellular Automata .

6.1 Building a D-latch

6.1.1 Traditional Design

A gated D-latch is specified by the truth table shown in figure 6.1. In thetable E stands for the gating or enabling signal whereas D is the input. Thesimilarity of the latch to the RAM cell in terms of functionality is quiteobvious. In traditional CMOS design however, flip flops come first andthen one designs RAMs based on arrays of flip flops. The role in the caseof Quantum Cellular Automata is reversed, wherein the RAM cell designdiscussed earlier gives rise to a latch design followed by a flip flop design.

Figure 6.1: Truth table for a gated D-latch

Traditionally, a D-latch is implemented using cross-coupled NAND gatesas shown in figure 6.2. It is similar to the RAM cell in the sense that it

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Figure 6.2: Traditional design of a D-latch

involves a closed loop inside the circuit as well. However there is a subtledifference, whereas the CMOS latch works on currents and thus involvespropagation of currents in a deterministic manner across the loop; the QCARAM cell does not. The directionality that current provides in a CMOScircuit is provided in a more subtle manner by proper clocking in QCA’s.

It was natural to build memory cells in QCA by looping because of the

Figure 6.3: Latched wire

nature of the clock. As soon as we clocked a wire, we had gotten a bit shiftregister or a latched line (figure 6.3) wherein every clock quarter cycle thebit was shifted forwards. The simulation results (figure 6.4)on the latchedline show how bits are shifted in time at every consecutive clocking zone,which is just like latching the bit forward through a shift register. But thiswas of little use in so far as storing information is concerned as ultimatelythe bit was shifted out. The answer to our problem was also in some senseobvious, to loop around the latched wire and close it to store information.We only need extra circuitry to retrieve or change this information.

6.1.2 QCA Implementation

The stripped down version of the RAM cell which acts as a gated D-latch isshown in figure 6.5. The portion of the circuit removed corresponds to thecircuitry for the select line; this small change reduces the design complexitytremendously as can be seen in the QCA cell layout diagram shown in figure6.6. This design involves only 50 cells and only 4 clocking zones; henceinput-output delay is only a single clock cycle. The simulation results on

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Figure 6.4: Simulations of the latched wire

Figure 6.5: D-latch circuit diagram

the circuit can be seen in figure 6.7.

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Figure 6.6: QCA layout of D-Latch

Figure 6.7: Simulation results of the D-Latch

6.2 Building a D-flipflop

In the previous section, we illustrated the design of a Quantum CellularAutomata D-latch. Although this is a value component for synchronous de-signs, to really harness the power of synchronous design we need to constructa D-flipflop. A flip flop in essence is just an edge detector, but in being anedge detector it embodies in itself the essential nature of a counter, whereinit becomes possible to cascade several flip flops and build n-ary counters.The inspiration for this design comes directly from the way flip flops (edgedetectors) are built in traditional CMOS circuits.

6.2.1 Traditional Design

There are two different ways flip flops arise in traditional circuitry. The firstone is illustrated in figure 6.8 and is the circuit layout of a negative edge

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triggered D-flip flop. This circuit design can be obtained from techniquesof asynchronous design fairly easily, though at first there seems no intuitiveway of getting at this circuit. We cannot construct an analogue of this designusing Quantum Cellular Automata as we have no analogue of cross coupledNAND gates. The second design methodology is illustrated in figure 6.9

Figure 6.8: Negative edge triggered D-flip flop design 1

Figure 6.9: Negative edge triggered D-flip flop design 2

wherein we use two gated latches in a master and slave arrangement. Thisis a design we can take and incorporate into the QCA framework since wealready have all the required lower level modules built.

6.2.2 QCA Implementation

The QCA circuit layout for the master slave arrangement is shown in figure6.10. The layout clearly shows two latches cascaded one after the other.This design uses 133 QCA cell and spans over 8 clocking zones from inputto output. The input-output delay of the circuit is therefore 2 clock cycles.Although the translation of the design seems a very mechanical task, it is infact a very tricky and non-trivial one particularly with respect to decidingthe clocking zones. The layout shown in figure 6.10 took several iterationsto come to its current working form.

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Figure 6.10: Negative edge triggered QCA based D-flip flop

Some simulation results showing the negative edge triggering of the flipflop are shown in figure 6.11. The simulation results clearly show how thecircuit indeed behaves as a negative edge triggered flip flop with a two cycledelay between input and output.

Figure 6.11: Simulation results of D-flip flop

6.3 Concluding Remarks

In the preceding sections we took a working RAM cell design and graduallymodified it to at first obtain a latch and then a negative edge triggered flipflop. This process of translation seemingly enhances our available set ofQuantum Cellular Automata modules substantially by including the basicsynchronous elements in it. It seems that henceforth it will become possibleto translate our large body of knowledge concerning synchronous circuitsverbatim into the QCA domain. However, in the ensuing chapter we shallnotice that this translation is not that simple and trouble free.

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Chapter 7

Extending synchronousdesigns : Building a counter

This chapter deals with our major attempt to add to the existing knowledgebase of QCA circuits. We have already presented a novel design for a D-flipflop in the previous section. Our attempt here will be to put this designto use and build a counter out of it. The motivation is the need to extendthe Quantum Cellular Automata paradigm to include the design of FiniteState Machines. This may be achieved in one of the following two ways.One is via direct mapping of FSM circuits to QCA circuits. This seeminglyachievable as we have the last missing component in terms of the flip flop.The alternative methos is to come up with an entirely new way to encodestate and data in FSMs. As with previous designs we first explore theeasier option of mapping our known knowledge, show a special case wherethis approach works and highlight the reasons for its non applicability ingeneral. We also try to explore a different way to design FSMs. In the end,the idea is to motivate novel ways of FSM design which fit more naturally inthis framework and are more probable to work than the traditional methods.

Figure 7.1: Binary counter or bit flipper

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7.1 Binary Counter

The easiest and simplest of all FSMs is the binary counter. It only requiresa single bit to encode state and keep flipping the state at every positive (ornegative) edge of the input signal. In essence by counting rising (or falling)edges what we achieve is the effect of frequency division by two or counting.The traditional circuit for this is shown using a D flip flop in figure 7.1. The

Figure 7.2: Bit flipper QCA circuit

circuit as mapped onto a QCA design is shown in figure 7.2. Things arehowever not as ideal as they might seem. The circuit of figure 7.2 doesn’twork the way it should, although it seems a logically correct design.

The simulation package we used (http://www.qcadesigner.ca) pro-vides two kind of simulation environments, the first is based on a bistablestate approximation and the second is based on a coherence vector analysis.The latter is more involved as it requires numerical solutions of several sim-ulataneous differential equations. In our experience with the designer, bothenvironments gave the same results in nearly every case we tested. The cellwidth used for designs are ≈ 18nm and the radius of effect is set to a de-fault value of ≈ 65nm, which means that cell can effect not only its nearestneighbors but also the cells next to its neighbors. This is essentially whycoplanar wire crossings work.

Now, if we take the circuit layout presented in figure 7.2 and simulate itunder the condition of radius of effect ≈ 35nm, our results change dramat-ically and the bit flipper begins to work. This is rather interesting becauseas mentioned in the previous paragraph, under these conditions coplanarwire crossings do not work (note that they are not needed in this design).We will try to discuss the reasons behind this failure and subsequent successwith tweaked simulation parameters in section 7.3.

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7.2 A different approach

Figure 7.3: A different way to think of synchronous circuits

The different approach that we take now is to base the design of ourFSM on regular sequential circuit design, this being a possibility because inthis case it is possible for us to actually take out a signal which has beendelayed by exactly one clock cycle, all we need to do is to put the wirethrough 5 clocking zones. And after all, an FSM can be thought of as asequential circuit in which the next state is a function of previous state andinput (fig. 7.3), if we have access to all of the three signals we can form acircuit. In general, we can treat the clock or gating signal as just anotherinput. Although, as we shall see, the ghosts of the earlier design would notleave us, this new strategy will still provide us with some new insights.

Old Input New Input Current State New State0 0 0 00 0 1 10 1 0 11 0 0 01 0 1 11 1 0 01 1 1 1

Table 7.1: Truth table for the bit flipper

Table 7.1 shows the truth table for a bit flipper, which essentially flipsstate on every positive edge in the input. This truth table results in thefollowing boolean function :

NS = CS[OI + NI] + CS.OI.NI (7.1)

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where NS is the next state, CS is the current state, OI is the old input (orthe input from 1 cycle earlier) and NI is the next input (or the input of thecurrent cycle).

We designed a cirtit in various stages (by gradually building the booleanfunction term by term) to implement this truth table, checking the correct-ness of the output at every stage. These stages are shown in figures 7.4,7.5, 7.6 and 7.7. At every step, if we compare the simulation results to theexpected answer we get the expected answers, in particular for the secondlast step, the simulations are shown in figure 7.8. It is easy to see that theresults match with table 7.1. Note that due to the circuit spreading over 8clocking zones, the output is delayed by two cycles.

However, if we now move on to the final step of the design and connectthe computed next state to the current state signal to complete our feedback,the simulations become unstable and do not yield the desired results, this isexactly what was happening in the earlier design attempt. It is now all themore pertinent to discuss why our designs are failing.

7.3 Analysis

In our introduction to Quantum Cellular Automata we had mentioned a sub-tle difference in the logic circuits based on QCA and those based on CMOSswitching. This difference lied in the fact that whereas CMOS switchingwas controlled by currents and the directionality characteristics of the same,QCA circuitry works on the interaction of static charges and coulombic po-tentials. This difference is also the reason for our failures.

If we look at the systems developed both in section 7.1 and section 7.2,they have one common characteristic, the presence of a feedback loop. Thisfeedback loop can help us explain why our circuits did not show expectedbehavior. In the case of current driven circuits, when we have a feedbackloop, the current gives the needed directionality. It ensures the fact that westart at the input and end at the output going through a series of voltagechanges along the way. However, in this case, there is no current and nodirectionality. It is a system which we await to settle in a stable groundstate. This means that the concept of feeding output back into the inputis equivalent to actually feeding the input into the output since there is noquestion of direction when there is no driver (cell of a forcing and fixedpolarization), and our feedback loop has no driver. Hence as soon as we geta closed loop without the sense of a driving signal that drives the next state,it is a system which just settles to some ground state. There is no reasonwhy this ground state should in all cases coincide with the one expectedwhen we start evaluating the loop in a particular direction. This is why thedesign start to fail when we loop back.

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7.3.1 Further Work

We have been able to come up with a design for a latch and a flip flop.However, we failed to extend the design to have a universal paradigm forsynchronous circuit design using quantum cells. This is an area which prob-ably requires a new way of thinking about state encoding and finite stateautomata to come up with a general approach. It probably requires a noveldesign of the kind presented in the Quantum Cellular Automata clockingsection, wherein the underlying principle of synchronization mechanism re-mained invariant but the the structure on top was radically different. Thisremains our area of further query into this fascinating subject.

Figure 7.4: NI +OI and OI.NI

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Figure 7.5: CS.OI.NI and CS.(NI +OI)

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Figure 7.6: CS.(NI +OI) + CS.OI.NI

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Figure 7.7: Next state state connected back to current state, completing theloop of fig. 7.6

Figure 7.8: Simulation results of circuit shown in fig. 7.6

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