Quadrature Decoder/CounterInterface ICs

Technical DataHCTL-2000HCTL-2016HCTL-2020

Features• Interfaces Encoder to

Microprocessor• 14 MHz Clock Operation• Full 4X Decode• High Noise Immunity:

Schmitt Trigger Inputs DigitalNoise Filter

• 12 or 16-Bit Binary Up/Down Counter

• Latched Outputs• 8-Bit Tristate Interface• 8, 12, or 16-Bit Operating

Modes• Quadrature Decoder Output

Signals, Up/Down and Count• Cascade Output Signals, Up/

Down and Count• Substantially Reduced

System Software

ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX familyICs.

Devices

Part Number Description Package DrawingHCTL-2000 12-bit counter. 14 MHz clock operation. AHCTL-2016 All features of the HCTL-2000. 16-bit counter. AHCTL-2020 All features of the HCTL-2016. Quadrature decoder output B

signals. Cascade output signals.

DescriptionThe HCTL-2000, 2016, 2020 areCMOS ICs that perform thequadrature decoder, counter, andbus interface function. TheHCTL-20XX family is designed toimprove system performance

Applications• Interface Quadrature

Incremental Encoders toMicroprocessors

• Interface Digital Potentiom-eters to Digital Data InputBuses

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in digital closed loop motioncontrol systems and digital datainput systems. It does this byshifting time intensive quadraturedecoder functions to a costeffective hardware solution. Theentire HCTL-20XX family con-sists of a 4x quadrature decoder,a binary up/down state counter,

and an 8-bit bus interface. Theuse of Schmitt-triggered CMOSinputs and input noise filtersallows reliable operation in noisyenvironments. The HCTL-2000contains a 12-bit counter. TheHCTL-2016 and 2020 contain a16-bit counter. The HCTL-2020also contains quadrature decoder

output signals and cascadesignals for use with manystandard counter ICs. The HCTL-20XX family provides LSTTLcompatible tri-state outputbuffers. Operation is specified fora temperature range from -40 to+85°C at clock frequencies up to14 MHz.

Package Dimensions

Operating CharacteristicsTable 1. Absolute Maximum Ratings(All voltages below are referenced to VSS)

Parameter Symbol Limits Units

DC Supply Voltage VDD -0.3 to +5.5 V

Input Voltage VIN -0.3 to VDD +0.3 V

Storage Temperature TS -40 to +125 °C

Operating Temperature TA[1] -40 to +85 °C

Table 2. Recommended Operating Conditions

Parameter Symbol Limits Units

DC Supply Voltage VDD +4.5 to +5.5 V

Ambient Temperature TA[1] -40 to +85 °C

19.05 ± 0.25(0.750 ± 0.010)

15°1.52 ± 0.13

(0.060 ± 0.005)

25.91 ± 0.25(1.02 ± 0.010)

9.40 (0.370)

15°

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Table 3. DC Characteristics VDD = 5 V ± 5%; TA = -40 to 85°C

Symbol Parameter Condition Min. Typ. Max. Unit

VIL[2] Low-Level Input Voltage 1.5 V

VIH[2] High-Level Input Voltage 3.5 V

VT+ Schmitt-Trigger Positive- 3.5 4.0 VGoing Threshold

VT- Schmitt-Trigger Negative- 1.0 1.5 VGoing Threshold

VH Schmitt-Trigger Hysteresis 1.0 2.0 V

IIN Input Current VIN = VSS or VDD -10 1 +10 µA

VOH[2] High-Level Output IOH -1.6 mA 2.4 4.5 V

Voltage

VOL[2] Low-Level Output IOL = +4.8 mA 0.2 0.4 V

Voltage

IOZ High-Z Output Leakage VO = VSS or VDD -10 1 +10 µACurrent

IDD Quiescent Supply Current VIN = VSS or VDD, VO = HiZ 1 5 µA

CIN Input Capacitance Any Input[3] 5 pF

COUT Output Capacitance Any Output[3] 6 pF

Notes:1. Free air.2. In general, for any VDD between the allowable limits (+4.5 V to +5.5 V), VIL = 0.3 VDD and VIH = 0.7 VDD; typical values are

VOH = VDD - 0.5 V @ IOH = -40 µA and VOL = VSS + 0.2 V @ IOL = 1.6 mA.3. Including package capacitance.

Figure 2. Waveform for Positive Clock Related Delays.

Figure 1. Reset Waveform.

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Functional Pin DescriptionTable 4. Functional Pin Descriptions

Pin PinSymbol 2000/2016 2020 Description

VDD 16 20 Power Supply

VSS 8 10 Ground

CLK 2 2 CLK is a Schmitt-trigger input for the external clock signal.

CHA 7 9 CHA and CHB are Schmitt-trigger inputs which accept the outputsCHB 6 8 from a quadrature encoded source, such as incremental optical shaft

encoder. Two channels, A and B, nominally 90 degrees out of phase,are required.

RST 5 7 This active low Schmitt-trigger input clears the internal positioncounter and the position latch. It also resets the inhibit logic. RST isasynchronous with respect to any other input signals.

OE 4 4 This CMOS active low input enables the tri-state output buffers. TheOE and SEL inputs are sampled by the internal inhibit logic on thefalling edge of the clock to control the loading of the internal positiondata latch.

SEL 3 3 This CMOS input directly controls which data byte from the positionlatch is enabled into the 8-bit tri-state output buffer. As in OE above,SEL also controls the internal inhibit logic.

SEL BYTE SELECTED

0 High

1 Low

CNTDCDR 16 A pulse is presented on this LSTTL-compatible output when thequadrature decoder has detected a state transition.

U/D 5 This LSTTL-compatible output allows the user to determine whetherthe IC is counting up or down and is intended to be used with theCNTDCDR and CNTCAS outputs. The proper signal U (high level) or D(low level) will be present before the rising edge of the CNTDCDR andCNTCAS outputs.

CNTCAS 15 A pulse is presented on this LSTTL-compatible output when theHCTL-2020 internal counter overflows or underflows. The rising edgeon this waveform may be used to trigger an external counter.

D0 1 1

D1 15 19

D2 14 18

D3 13 17

D4 12 14

D5 11 13

D6 10 12

D7 9 11

NC 6 Not connected - this pin should be left floating.

These LSTTL-compatible tri-state outputs form an 8-bit output portthrough which the contents of the 12/16-bit position latch may be read in2 sequential bytes. The high byte, containing bits 8-15, is read first (on theHCTL-2000, the most significant 4 bits of this byte are set to 0 internally).The lower byte, bits 0-7, is read second.

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Switching CharacteristicsTable 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.

Symbol Description Min. Max. Units

1 tCLK Clock period 70 ns

2 tCHH Pulse width, clock high 28 ns

3 tCD[1] Delay time, rising edge of clock to valid, updated count 65 ns

information on D0-7

4 tODE Delay time, OE fall to valid data 65 ns

5 tODZ Delay time, OE rise to Hi-Z state on D0-7 40 ns

6 tSDV Delay time, SEL valid to stable, selected data byte 65 ns(delay to High Byte = delay to Low Byte)

7 tCLH Pulse width, clock low 28 ns

8 tSS[2] Setup time, SEL before clock fall 20 ns

9 tOS[2] Setup time, OE before clock fall 20 ns

10 tSH[2] Hold time, SEL after clock fall 0 ns

11 tOH[2] Hold time, OE after clock fall 0 ns

12 tRST Pulse width, RST low 28 ns

13 tDCD Hold time, last position count stable on D0-7 after clock rise 10 ns

14 tDSD Hold time, last data byte stable after next SEL state change 5 ns

15 tDOD Hold time, data byte stable after OE rise 5 ns

16 tUDD Delay time, U/D valid after clock rise 45 ns

17 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise 45 ns

18 tCLD Delay time, CNTDCDR or CNTCAS low after clock fall 45 ns

19 tUDH Hold time, U/D stable after clock rise 10 ns

20 tUDCS Setup time, U/D valid before CNTDCDR or CNTCAS rise tCLK-45 ns

21 tUDCH Hold time, U/D stable after CNTDCDR or CNTCAS rise tCLK-45 ns

Notes:1. tCD specification and waveform assume latch not inhibited.2. tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup

and hold times do not need to be observed.

Figure 3. Tri-State Output Timing.

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Figure 4. Bus Control Timing.

Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only).

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Digital Noise FilterThe digital noise filter section isresponsible for rejecting noise onthe incoming quadrature signals.The input section uses twotechniques to implementimproved noise rejection.Schmitt-trigger inputs and athree-clock-cycle delay filtercombine to reject low level noiseand large, short duration noisespikes that typically occur inmotor system applications. Bothcommon mode and differentialmode noise are rejected. The userbenefits from these techniques byimproved integrity of the data in

input is tested for a stable levelbeing present for threeconsecutive rising clock edges.Therefore, the filtered outputwaveforms can change only afteran input level has the same valuefor three consecutive rising clockedges. Refer to Figure 8 whichshows the timing diagram. Theresult of this circuitry is thatshort noise spikes between risingclock edges are ignored andpulses shorter than two clockperiods are rejected.

the counter. False countstriggered by noise are avoided.

Figure 7 shows the simplifiedschematic of the input section.The signals are first passedthrough a Schmitt trigger bufferto address the problem of inputsignals with slow rise times andlow level noise (approximately< 1 V). The cleaned up signalsare then passed to a four-bitdelay filter. The signals on eachchannel are sampled on risingclock edges. A time history of thesignals is stored in the four-bitshift register. Any change on the

Figure 6. Simplified Logic Diagram.

OperationA block diagram of the HCTL-20XX family is shown in Figure 6.The operation of each majorfunction is described in thefollowing sections.

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Figure 7. Simplified Digital Noise Filter Logic.

Quadrature DecoderThe quadrature decoder decodesthe incoming filtered signals intocount information. This circuitrymultiplies the resolution of theinput signals by a factor of four(4X decoding). When using anencoder for motion sensing, theuser benefits from the increasedresolution by being able toprovide better system control.

The quadrature decoder samplesthe outputs of the CHA and CHBfilters. Based on the past binarystate of the two signals and thepresent state, it outputs a countsignal and a direction signal to

the internal position counter. Inthe case of the HCTL-2020, thesignals also go to external pins 5and 16 respectively.

Figure 9 shows the quadraturestates and the valid state transi-tions. Channel A leading channelB results in counting up. ChannelB leading channel A results incounting down. Illegal statetransitions, caused by faultyencoders or noise severe enoughto pass through the filter, willproduce an erroneous count.

Design ConsiderationsThe designer should be awarethat the operation of the digitalfilter places a timing constrainton the relationship betweenincoming quadrature signals andthe external clock. Figure 8shows the timing waveform withan incremental encoder input.Since an input has to be stablefor three rising clock edges, theencoder pulse width (tE - low orhigh) has to be greater than threeclock periods (3tCLK). Thisguarantees that the asynchronousinput will be stable during threeconsecutive rising clock edges. Arealistic design also has to take

Figure 8. Signal Propagation through Digital Noise Filter.

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channels. Therefore, tES (encoderstate period) > tCLK. Thedesigner must account fordeviations from the nominal 90degree phasing of input signals toguarantee that tES > tCLK.

Position CounterThis section consists of a 12-bit(HCTL-2000) or 16-bit (HCTL-2016/2020) binary up/downcounter which counts on risingclock edges as explained in theQuadrature Decoder Section. All12 or 16 bits of data are passedto the position data latch. Thesystem can use this count data inseveral ways:

A. System total range is ≤ 12 or16 bits, so the count repre-sents “absolute” position.

B. The system is cyclic with ≤12 or 16 bits of count percycle. RST is used to resetthe counter every cycle andthe system uses the data tointerpolate within the cycle.

C. System count is > 8, 12, or 16bits, so the count data isused as a relative or incre-mental position input for asystem software computationof absolute position. In thiscase counter rollover occurs.In order to prevent loss ofposition information, theprocessor must read theoutputs of the IC before thecount increments one-half ofthe maximum count capabil-

ity (i.e. 127. 2047, or 32,767quadrature counts). Two’s-complement arithmetic isnormally used to computeposition from these periodicposition updates. Threemodes can be used:1. The IC can be put in 8-bit

mode by tying the SELline high, thus simplify-ing IC interface. Theoutputs must then beread at least once every127 quadrature counts.

2. The HCTL-2000 can beused in 12-bit mode andsampled at least onceevery 2047 quadraturecounts.

3. The HCTL-2016 or 2020can be used in 16-bitmode and sampled atleast once every 32,767quadrature counts.

D. The system count is > 16 bitsso the HCTL-2020 can becascaded with other stand-ard counter ICs to giveabsolute position.

Position Data LatchThe position data latch is a 12/16-bit latch which captures theposition counter output data oneach rising clock edge, exceptwhen its inputs are disabled bythe inhibit logic section duringtwo-byte read operations. Theoutput data is passed to the businterface section. When active, asignal from the inhibit logicsection prevents new data frombeing captured by the latch,keeping the data stable whilesuccessive reads are madethrough the bus section. Thelatch is automatically reenabledat the end of these reads. Thelatch is cleared to 0 asynchron-ously by the RST signal.

into account finite rise times ofthe waveforms, asymmetry of thewaveforms, and noise. In thepresence of large amounts ofnoise, tE should be much greaterthan 3tCLK to allow for theinterruption of the consecutivelevel sampling by the three-bitdelay filter. It should be notedthat a change on the inputs thatis qualified by the filter willinternally propagate in a maxi-mum of seven clock periods.

The quadrature decoder circuitryimposes a second timing con-straint between the external clockand the input signals. There mustbe at least one clock periodbetween consecutive quadraturestates. As shown in Figure 9, aquadrature state is defined byconsecutive edges on both

Figure 9. 4x Quadrature Decoding.

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Inhibit LogicThe Inhibit Logic Section samplesthe OE and SEL signals on thefalling edge of the clock and, inresponse to certain conditions(see Figure 10 below), inhibitsthe position data latch. The RSTsignal asynchronously clears theinhibit logic, enabling the latch. Asimplified logic diagram of theinhibit circuitry is illustrated inFigure 11.

Bus InterfaceThe bus interface section consistsof a 16 to 8 line multiplexer andan 8-bit, three-state outputbuffer. The multiplexer allowsindependent access to the lowand high bytes of the positiondata latch. The SEL and OEsignals determine which byte is

output and whether or not theoutput bus is in the high-Z state.In the case of the HCTL-2000 thedata latch is only 12 bits wideand the upper four bits of thehigh byte are internally set tozero.

Quadrature DecoderOutput (HCTL-2020Only)The quadrature decoder outputsection consists of count and up/down outputs derived from the4X decode logic of the HCTL-2020. When the decoder hasdetected a count, a pulse, one-half clock cycle long, will beoutput on the CNTDCDR pin. Thisoutput will occur during the clockcycle in which the internalcounter is updated. The U/D pin

will be set to the proper voltagelevel one clock cycle before therising edge of the CNTDCDRpulse, and held one clock cycleafter the rising edge of theCNTDCDR pulse. These outputsare not affected by the inhibitlogic. See Figures 5 and 12 fordetailed timing.

Cascade Output (HCTL-2020 Only)The cascade output also consistsof count and up/down outputs.When the HCTL-2020 internalcounter overflows or underflows,a pulse, one-half clock cycle long,will be output on the CNTCAS pin.This output will occur during theclock cycle in which the internalcounter is updated. The U/D pinwill be set to the proper voltagelevel one clock cycle before therising edge of the CNTCAS pulse,and held one clock cycle after therising edge of the CNTCAS pulse.These outputs are not affected bythe inhibit logic. See Figures 5and 12 for detailed timing.

Figure 11. Simplified Inhibit Logic.

InhibitStep SEL OE CLK Signal Action

1 L L 1 Set inhibit; read high byte

2 H L 1 Read low byte; starts reset

3 X H 0 Completes inhibit logic reset

Figure 10. Two Byte Read Sequence.

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Cascade Considerations(HCTL-2020 Only)The HCTL-2020’s cascadingsystem allows for position readsof more than two bytes. Thesereads can be accomplished bylatching all of the bytes and thenreading the bytes sequentiallyover the 8-bit bus. It is assumedhere that, externally, a counterfollowed by a latch is used tocount any count that exceeds 16bits. This configuration iscompatible with the HCTL-2020internal counter/latchcombination.

Consider the sequence of eventsfor a read cycle that starts as theHCTL-2020’s internal counterrolls over. On the rising clockedge, count data is updated in theinternal counter, rolling it over. Acount-cascade pulse (CNTCAS)

will be generated with some delayafter the rising clock edge (tCHD).There will be additionalpropagation delays through theexternal counters and registers.Meanwhile, with SEL and OE lowto start the read, the internallatches are inhibited at the fallingedge and do not update again tillthe inhibit is reset. If the CNTCASpulse now toggles the externalcounter and this count getslatched a major count error willoccur. The count error is becausethe external latches get updatedwhen the internal latch isinhibited.

Valid data can be ensured bylatching the external counter datawhen the high byte read is started(SEL and OE low). This latchedexternal byte corresponds to the

count in the inhibited internallatch. The cascade pulse thatoccurs during the clock cyclewhen the read begins getscounted by the external counterand is not lost.

For example, suppose the HCTL-2020 count is at FFFFH and anexternal counter is at F0H, withthe count going up. A countoccurring in the HCTL-2020 willcause the counter to roll over anda cascade pulse will be generated.A read starting on this clock cyclewill show FFFFH from the HCTL-2020. The external latch shouldread F0H, but if the host latchesthe count after the cascade signalpropagates through, the externallatch will read F1H.

Figure 12. Decode and Cascade Output Diagram.

CLK

CHAFILT*

U/D

COUNT

CHBFILT*

CNTDCDR*

CNTCAS

*CHAFILT AND CHBFILT ARE THE OUTPUTS OF THE DIGITAL NOISE FILTER (SEE FIGURES 7 AND 8).

FFFDH FFFEH FFFFH 0000H FFFFH FFFDH

INTERNAL COUNTER ROLL OVER

FF

START INHIBIT

00

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For proper operation of theinhibit logic during a two-byteread, OE and SEL must besynchronous with CLK due tothe falling edge sampling of OEand SEL.

The internal inhibit logic on theHCTL-20XX family inhibits thetransfer of data from the counterto the position data latch duringthe time that the latch outputs arebeing read. The inhibit logicallows the microprocessor to first

General InterfacingThe 12-bit (HCTL-2000) or 16-bit(HCTL-2016/2020) latch andinhibit logic allows access to 12or 16 bits of count with an 8-bitbus. When only 8-bits of countare required, a simple 8-bit (1-byte) mode is available byholding SEL high continuously.This disables the inhibit logic. OEprovides control of the tri-statebus, and read timing is shown inFigures 2 and 3.

read the high order 4 or 8 bitsfrom the latch and then read thelow order 8 bits from the latch.Meanwhile, the counter cancontinue to keep track of thequadrature states from the CHAand CHB input signals.

Figure 11 shows the simplifiedinhibit logic circuit. Theoperation of the circuitry isillustrated in the read timingshown in Figure 13.

Figure 13. Typical Interface Timing.

*OE can consist of two short low pulses, as well as one long pulse, and still satisfythe inhibit logic sequence. During the time that OE is high, the data lines are tri-seated.

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low on OE during a fallingclock edge.

6. When OE goes high, the datalines change to a high imped-ance state.

7. The IC detects a logic high onOE during a falling clock edge.This satisfies the second resetcondition for the inhibit logic.

Actions1. On the rising edge of the clock,

counter data is transferred tothe position data latch,provided the inhibit signal islow.

2. When OE goes low, theoutputs of the multiplexer areenabled onto the data lines. IfSEL is low, then the high orderdata bytes are enabled onto thedata lines. If SEL is high, thenthe low order data bytes areenabled onto the data lines.

3. When the IC detects a low onOE and SEL during a fallingclock edge, the internal inhibitsignal is activated. This blocksnew data from beingtransferred from the counter tothe position data latch.

4. When SEL goes high, the dataoutputs change from the highbyte to the low byte.

5. The first of two reset condi-tions for the inhibit logic ismet when the IC detects alogic high on SEL and a logic

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Interfacing the HCTL-2020 to a Motorola 6802/8 and Cascading the Counter for 24Bits

Figure 14. A Circuit to Interface to the 6802/8.

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In this circuit an interface to aMotorola 6802/8 and a cascadingscheme for a 24-bit counter areshown. This circuit provides aminimum part count by: 1) usingtwo 74LS697 Up/Down counterswith output registers and tri-stateoutputs and 2) using a Motorola6802/8 LDX instruction whichstores 16 bits of data into theindex registers in two consecutiveclock cycles.

The HCTL-2020 OE and the74LS697 G lines are decodedfrom Address lines A15-A13. Thisresults in counter data beingenabled onto the bus wheneveran external memory access ismade to locations 4XXX or 2XXX.Address line A12 and processorclock E enables the 74LS138.The processor clock E is also

used to clock the HCTL-2020.Address AO is connected directlyto the SEL pin on the HCTL-2020. This line selects the low orhigh byte of data from the HCTL-2020.

Cascading is accomplished byconnecting the CNTCAS output onthe HCTL-2020 with the counterclock (CCK) input on both74LS697s. The U/D pin on theHCTL-2020 and the U/D pin onboth 74LS697s are also directlyconnected for easy expansion.The RCO of the first 4-bit74LS697 is connected to the ENTpin of the second 74LS697. Thisenables the second counter onlywhen there is a RCO signal on thefirst counter.

This configuration allows the6802 to read both data bytes with

a single double-byte fetchinstruction (LDX 2XX0). Thisinstruction is a five cycleinstruction which reads externalmemory location 2XX0 and storesthe high order byte into the highbyte of the index register.Memory location 2XX1 is nextread and stored in the low orderbyte of the index register. Thehigh byte of counter data isclocked into the 74LS697registers when SEL is low andOE goes low. This upper byte canbe read at any time by pulling the74LS697 G low when readingaddress 4XXX. Figure 15 showsmemory addresses and gives anexample of reading the HCTL-2020. Figure 16 shows theinterface timing for the circuit.

Address Function

CXXX Reset Counters

4XXX Enable High Byte on Data Lines

2XX0 Enable Mid Byte on Data Lines

2XX1 Enable Low Byte on Data Lines

Read Example

LDX 2000 Loads mid byte and then low byte intoSTX 0100 memory locations 0100 and 0101

LDAA 4000 Loads the high byte into memorySTAA 0102 location 0102

Figure 15. Memory Addresses and Read Example.

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Actions1. The microprocessor clock

output is E. If the internalHCTL-2020 inhibit is notactive, new data is trans-ferred from the internalcounter to the position datalatch.

2. An even address outputfrom the 6802 causes SEL togo low. When E goes high,the address decoder outputfor the HCTL-2020 OEsignal goes low. This causesthe HCTL-2020 to outputthe middle byte of thesystem counter (high byte ofthe HCTL-2020 counter).This middle byte, FFFFH isavailable at (2) through (4),the first time OE is low. Inthis example an overflow

has occurred and OE hasbeen pulled low to start aread cycle. SEL and OE aregated to give RCK whichlatches the external highbyte, equal to 00H. Thefalling edge, of the CNTCASsignal counts up theexternal counter to 0001H.

3. With the first negative edgeof the clock after SEL andOE are low the internallatches are inhibited fromcounting and the 6802 readsthe high byte in.

4. OE goes high and the databus goes into a highimpedance state.

5. OE is low and SEL is highand the low byte is enabledonto the data bus. The lowbyte is valid through (7).

6. With the first negative edgeafter OE and SEL go high,the first of the two HCTL-2020 inhibit reset conditionsis met and the 6802 readsthe low byte in.

7. The data bus returns to thehigh impedance state, whenOE goes high.

8. With the first negative edgeof the clock after OE goeshigh, inhibit reset iscomplete.

9. With the positive going edgeof the clock, G is assertedand the external high byte,00H is available on the databus from 9 through 10 andthe 6802 reads the high bytein at (10).

Figure 16. Interface Timing for the 6802/8.

CLK

SEL

INTERNAL INHIBIT

DATA BUS

OE

CNTCAS

FFFF 0000HCTL-2020 INTERNAL CLOCK

RCK

G

ACTIONS

HIGH Z

11 1

2 3

4 5

6

7 8 9 10

MID BYTE

LOW BYTE

HIGH BYTE

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is the crystal frequency dividedby 3. T0 must be enabled byexecuting the ENT0 CLKinstruction after each systemreset, but prior to the firstencoder position change. An8748 program which interfacesto the circuit in Figure 17 isgiven in Figure 18. The resultinginterface timing is shown inFigure 19.

Interfacing the HCTL-20XX to an Intel 8748The circuit shown in Figure 17shows the connections betweenan HCTL-20XX and an 8748.Data lines D0-D7 are connectedto the 8748 bus port. Bits 0 and 1of port 1 are used to control theOE and SEL inputs of the HCTL-20XX respectively. T0 is used toprovide a clock signal to theHCTL-20XX. The frequency of T0

Figure 17. An HCTL-20XX-to-Intel 8748 Interface.

* NOTE: PIN NUMBERS ARE DIFFERENT FOR THE HCTL-2020.

Object SourceLOC Code Statements Comments

000 99 00 ANL P1, 00H Enable output and higher orderbits

002 08 INS A, BUS Load higher order bits into ACC

003 A8 MOVE R0, A Move data to register 0

004 89 02 ORL P1, 02H Enable output and lower orderbits

006 08 INS A, BUS Load order bits into AC

008 A9 MOV R1, A Move data to register 1

009 89 03 ORL P1, 03H Disable outputs

00B 93 RETR Return

Figure 18. A Typical Program for Reading HCTL-20XX with an 8748.

Actions1. ANL P1, 00H has just been

executed. The output of bits 0and 1 of Port 1 cause SEL andOE to be logic low. The datalines output the higher orderbyte.

2. The HCTL-20XX detects thatOE and SEL are low on thenext falling edge of the CLKand asserts the internal inhibitsignal. Data can be readwithout regard for the phase ofthe CLK.

3. INS A, BUS has just beenexecuted. Data is read into the8748.

4. ORL PORT 1, 02H has justbeen executed. The programsets SEL high and leaves OElow by writing the correctvalues to port 1. The HCTL-

20XX detects OE is low andSEL is high on the next fallingedge of the CLK, and thus thefirst inhibit reset condition ismet.

5. INS A, BUS has just beenexecuted. Lower order databits are read into the 8748.

6. ORL P1, 03H has just beenexecuted. The HCTL-20XXdetects OE high on the nextfalling edge of CLK. Theprogram sets OE and SEL highby writing the correct values toport 1. This causes the datalines to be tristated. Thissatisfies the second inhibit andreset condition. On the nextrising CLK edge new data istransferred from the counter tothe position data latch.

Figure 19. 8748 READ Cycle from Figure 18.

ORL P1, 02HANL P1, OOH

Additional Informationfrom AgilentTechnologiesApplication briefs are availablefrom the factory. Please contactyour local Agilent salesrepresentative for the following.M027 Interfacing the HCTL-20XX

to the 8051M019 Commonly Asked

Questions about the HCTL-2020 and Answers

M020 A Simple Interface for theHCTL-2020 with a 16-bitDAC without Using aProcessor

M023 Interfacing the MC68HCIIto the HCTL-2020

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www.semiconductor.agilent.com

Data subject to change.Copyright © 1999 Agilent Technologies, Inc.

Obsoletes 5091-9974E (3/94)

5965-5894E (11/99)