qoriq p4080 processor pre-boot loader image tool · instead, the p4080 reads the pbl image, which...

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-NET-F0402

QorIQ P4080 Processor Pre-Boot Loader Image Tool

June 23, 2010

Kelley OswaltApplications Engineer

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2

Objective

Introduce the PBL Image Tool and describe it’s features and use in assisting the user in creating a complete PBL Image for the P4080 device.

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

Agenda

3

1. P4080 introduction2. Introduction to PBL interface3. Pre-boot Initialization (PBI)4. PBL Image5. Overview of PBL tool capability6. Details about the Tools tab

• Encode PBL image• Decode PBL image• Calculate clock frequencies and data rates

7. Details on PBI tab • How to load a binary image via PBI commands

8. Examples


Introduction

Why does the P4080 implement a Reset Configuration Word (RCW)?

►The P4080 requires a significant amount of power-on-reset (POR) configuration (over 60 parameters) for proper operation.

►This would require more than 200 configuration pins.

► Instead, the P4080 reads the PBL image, which includes the RCW, from an external memory device.

►The pre-boot loader (PBL) image is the memory-based configuration data that includes both the RCW and PBI commands.

The browser-based PBL image tool helps the user create a complete PBL image for use with a P4080 device.


QorIQ P4080


Reset Configuration Pins

►RCW source location• cfg_rcw_src[0:4]

►General purpose input• Cfg_gpinput[0:15]

►eLBC FCM ECC control• Cfg_elbc_ecc

►DRAM type select• Cfg_dram_type


Introduction: P4080 Pre-Boot Loader (PBL)

The pre-boot loader (PBL): ►Performs configuration register read and write to initialize the I2C, eLBC FCM (NAND Flash), eSDHC, or SPI interface – chosen by RCW source config pins►Loads PBL image from chosen source

•Loads RCW from external memory device – waits for PLLs to lock•Loads pre-boot initialization (PBI) commands – optional

PBL block diagram showing interface command modules


PBI Commands

►What is purpose of the PBI?• Allows configuration of various interfaces before allowing the cores to

boot• Similar to bootsequencer on previous devices• Write to CCSR space (ACS = 0) • Write to alternative space such DDR or CPC SRAM (ACS = 1)• Commands

Flush – Ensure previous write has taken effectCRC Check – performs CRC check on all data since last CRC checkJump – provide next address to jump toWait - can’t poll registers but can set a number of sysclks to wait


PBL Image

Preamble(required)

RCW(required)

1st Pre-bootCommand

(optional)...

Last Pre-bootCommand

(optional)

End Command(required)


Overview of PBL Tool Capability

►Support for Rev 1.0 and Rev 2.0 silicon

►PBL tool creates entire PBL Image• RCW (Reset Configuration Word) configuration• PBI (Pre-Boot Initialization) commands

►Opens in HTML browser that supports JavaScript

• Allows for portability• User must save data and create file to load into their system

►Tool does not check validity of selections• User must make sure selections adhere to P4080RM, P4080EC

and P4080CE documents


Overview of PBL Tool Usage

►First 9 tabs represent the RCW components• Organized according to the categories in the P4080RM• (i) symbol provides additional information on each field• Checkpoint can be saved as a browser cookie only for RCW field selections

►Tools tab• Encode or decode of PBL images• Calculate clock frequencies and data rates

►PBI tab• Allows user to include PBI commands in power-on reset configuration


PBL Image Tool

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 13

Tools Tab - Encode


Tools Tab - Encode

Encoding a PBL image►PBL data formats

• XXD object dump (default)• S-record• Source code• U-boot commands – commands to type in U-boot to write PBL image

to memory• eDINK commands – commands to type in eDINK to write PBL image

to memory• HEX string

►RCW data formats - RCW only without preamble and CRC• CodeWarrior JTAG Configuration File• HEX string• Text table


Tools Tab - Decode


Tools Tab - Decode

Decoding a PBL image►PBL data formats

• XXD object dump (default)• S-record• Source code• U-boot memory dump – PBL image found in RCW source location• eDINK memory dump – PBL image found in RCW source location• HEX string

►RCW data formats• U-boot CCSR dump – RCW only settings found in RCW status registers• eDINK CCSR dump – RCW only settings found in RCW status registers• Code Warrior JTAG Configuration File• HEX string• Text table

►RCW hard-coded settings


Tools tab - Clocking

►Calculate System Clocks► Inputs

• System clock• SRDS Refclk 1/2/3

►Push “Calculate Clocks” button►Displays PLL and Clock frequencies within P4080


PBI Tab


PBI Tab

PBI data►CCSR address space

• CCSR data (4 byte) – memory mapped register write• CCSR data (1 byte) – memory mapped register write

►PBL commands• Flush• CRC check• Jump – currently not implemented• Wait

►ACS address space• ACS data (4 byte) – write to alternate configuration space such as DDR• ACS file (XXD object file)


PBI Tab – Loading an ACS File into DDR

1. CCSR writes to configure DDR controller

2. CCSR writes to ALTCBARH/L and ALTCAR registers to set up base address and target of alternative configuration space for DDR

3. Flush command to ensure write to ACS registers takes affect

4. Place ACS .xxd file into the same folder where the PBL image tool resides

5. Select “ACS File (XXD Object File)” from the drop-down list

6. Enter the offset of the DDR address space where you want the file to be downloaded

7. Browse for the file

8. Click “Add PBI Data” button


Demo - Examples


Tools Tab – Decode Example

Decoding a PBL image example► Common reset configuration file might be .bin (which is not decodable by

the PLB image tool)1. Use xxd to create an object dump of the .bin file2. Paste the object dump into the decode field3. Select “PBL XXD Object Dump” from the pulldown menu4. Click the “Decode PBL” button5. Now all RCW and PBI fields have been updated to reflect the decoded

image


Tools Tab – Encode Example

Encoding a PBL image example1. Select “PBL XXD Object Dump” from the pull down menu2. Select address offset value for the start of the image (default is 0)3. Click “Encode PBL” button4. Copy and paste data into a vi editor and save file as .xxd5. Use xxd –r command to reverse the file into a .bin file6. The .bin file can then be transferred to the preferred RCW source


PBI Tab – Example

Issuing PBI commands1. Select “CCSR Data (4 Byte)” from the drop down list, fill in ‘Offset’ and

‘Data’ for register write2. Select “Flush” from the drop down list and notice the ‘Offset’ is set for you3. Select “ACS Data (4 Byte)” from the drop down list, fill in ‘Offset’ and

‘Data’ for the address in Alternate Configuration Space you would like to write to

4. Select “ACS File (XXD Object Dump)” from the drop down list, fill in ‘Offset’ and Browse for the file to load

5. Encode new PBL image and see PBI data added to image


Notes


PLL Tab - RCW[0-127]

►SYSCLK to platform clock frequency settings

►DDR PLL frequency settings

►SYSCLK to core cluster PLL settings

• 4 core cluster PLLs• Core complex 0-3 and core

complex 4-7 must select a core cluster PLL to be used


SerDes PLL Tab – RCW[128-183]

►SerDes bank/lane assignments• SRDS_PRTCL• Bank 1 – 10 lanes

PCIe, SRIO and Aurora (few SGMII exceptions)

• Bank 2 – 4 lanesFM2 – XAUI and SGMII (few PCIe exceptions)

• Bank 3 – 4 lanesFM1 – XAUI and SGMII

►SerDes reference clock to SerDes PLL frequency settings

►Lane power down per-bank

►SerDes enable


Misc PLL Tab – RCW[184-191]

►Selects DDR mode for both controllers

• Synchronous mode Memory controller complex PLL reference clock is platform clock

• Asynchronous modeMemory controller complex PLL reference clock is SYSCLK


Boot Tab – RCW[192-223]

►PBI source settings • PBI addr/data commands are to be used for CCSR and/or local

memory space• PBI source must be same as RCW source

►Boot location• PCIe, SRIO, DDR or eLBC• Can be different from RCW and PBI source, with the exception that

only one eLBC option can be chosen as the source of RCW, PBI and boot location

►Boot holdoff mode• All cores except core0 or all cores are held in boot holdoff mode at

out of reset

►Secure boot enable


Clocking Tab – RCW[224-255]

►Pattern match engine clock select• Platform clock /2• Core cluster CC3 PLL /2

(PME will run asynchronous to the platform)

►Frame manager 1 and 2 clock select

• Platform clock /2• Core cluster CC3 PLL /2

(FMan will run asynchronous to the platform)


RCW[256-319]

►Memory I/O tab• RapidIO device ID• Agent and Host mode selections

►General purpose tab• GPIO pin selections


Pin Muxing Tabs – RCW[352-512]

►Pin muxing A tab• 1588 clock settings• RGMII / USB enabling• UART• I2C• IRQ• SPI

►Pin muxing B tab• DMA

qoriq p4080 processor pre-boot loader image tool · instead, the p4080 reads the pbl image, which...

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