qia123 spi communication guide · qia123 spi communication guide drawing number em1035 · revision...

QIA123 SPI Communication Guide

Drawing Number EM1035 · Revision B · 2020-06-16 · of 15

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Table of Contents General Description ......................................................................................................................................... 3

PIN Configurations and Function Descriptions .................................................................................................. 3

QIA123 SPI Configuration ................................................................................................................................. 4

QIA123 Internal Design Algorithm .................................................................................................................... 5

“Continuous Read” Mode ................................................................................................................................ 5

SPI Packet Structure ......................................................................................................................................... 5

Timing Diagrams .............................................................................................................................................. 6 Get Command Structure: ................................................................................................................................................ 6 Set Command Structure: ................................................................................................................................................. 7 Enable Sampling (ES) Command Structure: ...................................................................................................................... 7 𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 Period ................................................................................................................................................................. 7

System Behavior .............................................................................................................................................. 8 Start-up and Self-Calibration Mode ................................................................................................................................. 8 Wrong CRC Error ............................................................................................................................................................ 8 Wrong CMD Error ........................................................................................................................................................... 8 Error Codes .................................................................................................................................................................... 8

Sampling Rate Change ..................................................................................................................................... 9 Sampling Rates ............................................................................................................................................................... 9

Shunt Switch Feature ......................................................................................................................................10 RSHSWS (Read Shunt Switch State) ............................................................................................................................... 10 ESHSW (Enable Shunt Switch) ....................................................................................................................................... 10 DSHSW (Disable Shunt Switch)...................................................................................................................................... 10

Power Management .......................................................................................................................................10 DS (Disable Sampling; Sleep-Mode) .............................................................................................................................. 10 ES (Enable Sampling; Wake-Mode) ............................................................................................................................... 10



Command-Set List ...........................................................................................................................................11

Firmware Revision ..........................................................................................................................................15

CRC Calculations and References .....................................................................................................................15



General Description The QIA123 is a low power digital controller with UART and SPI outputs as well as an analog output. The QIA123 (slave device) can be used to communicate with any master devices through a SPI bus. It also allows the master device to control the power consumption of the system by enabling and disabling the sampling system if required by the application.

PIN Configurations and Function Descriptions

Table 1.

# Pin Description

1 𝑽𝑽𝑽𝑽𝑽𝑽 Voltage Input 5V±4%

2 GND Ground pins are connected to each other internally

3 TRIG Trigger is an input pin (slave) and output pin (master) dedicated for special applications such as programing for future development


5 𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 Active low 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 pin is used to keep all communication synchronized. It notifies the master device when new data from the sampling system is ready to ensure that the master is always collecting the latest data. When the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷pin goes low, it indicates that the data is

𝐶𝐶𝐶𝐶

𝑀𝑀𝑂𝑂𝐶𝐶𝑂𝑂

𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷

𝑀𝑀𝑂𝑂𝐶𝐶𝑂𝑂 𝐶𝐶𝐶𝐶𝑆𝑆𝑆𝑆

𝐺𝐺𝐺𝐺𝐷𝐷

𝐷𝐷𝑅𝑅

𝑉𝑉𝑂𝑂𝑉𝑉𝑉𝑉

𝐺𝐺𝐺𝐺𝐷𝐷

𝐺𝐺𝐺𝐺𝐷𝐷 𝐺𝐺𝐺𝐺𝐷𝐷

𝑉𝑉𝑂𝑂𝐺𝐺

𝑉𝑉𝐷𝐷𝑂𝑂𝐺𝐺

𝑉𝑉𝑅𝑅

Figure 1.



ready. This pin can be used to externally interrupt the master. The pin returns high when the system is in a conversion state and returns low once new data is ready. The pin does not return high once data is read—it will only return high once the system enters a conversion state.

6 𝑪𝑪𝑪𝑪�� Active low Chip Select. Do not drive the 𝐶𝐶𝐶𝐶 line low until the device has booted up completely. The LED turns off once the board has booted and is ready to communicate. This process takes 3 seconds. Also ensure that the 𝐶𝐶𝐶𝐶 line is not driven low unless the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 �� is also low.

7 SCLK Serial Clock generated by master

8 MOSI Master-Out-Slave-In

9 MISO Master-In-Slave-Out

10 TX UART Transmit

11 RX UART Receive



14 VOUT Analog voltage output calibrated between 0.2V – 2.8V

QIA123 SPI Configuration

Table 2.

Serial Word Length 16-Bit SPI Mode Mode 0, CPOL = 0, CPHA = 0, SCLK Frequency Min 3 MHz Max 8 MHz Internal Clock Frequency of MCU 32 MHz Operation Mode Slave



QIA123 Internal Design Algorithm When the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 ��pin goes high, it means the device is in the process of A/D conversion, calculating the CRC16 (see CRC Calculations and References), and generating the packet that needs to be sent per the master device’s request. 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷��goes low as soon as it fills out the SPI TX buffer. The following algorithm is being executed while 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� is high:

• Receives the latest ADC data from the highest interrupt priority • Slave Service Function

o Keeps reading the RX FIFO until it is empty o Saves the last six bytes of data in a software buffer o Checks the CRC16 and CMD

If the CRC16 or CMD is incorrect • Go to the Default state

Else • Replies with the corresponding packet

Default State: • Stop and reset the SPI module • Initialize the SPI module • Calculate the CRC16 • Load six bytes of data (including the Error Code bytes and latest ADC counts) into the TX

FIFO buffer • 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 ��goes low

It is important to note that when a packet is clocked into the QIA123 via the MOSI line, the response to that packet must be clocked out in the very next 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� period. If it is not clocked out in the next 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� period, the response will be lost, and the system will go back to clocking out ADC data.

“Continuous Read” Mode RADC Command may be sent for each 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� period to continuously read the ADC data

*Note: If the CRC bytes or the CMD bytes are incorrect, the device still fills out the buffer with the Error Code in addition of ADC data

SPI Packet Structure The packet structure stays consistent during all transactions and always includes six bytes of data for both receiving or transmitting. The first byte is dedicated for the Error Code (see Table 4.); in other words, if the system receives a packet



with a wrong CRC or an undefined CMD, it will return an Error Code for the first byte followed by ADC data and the CRC for the next five bytes.

*Note: Each word (16-bits) can be clocked out with or without delay, but the entire transaction must be completed within a single 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷��period.

The first byte of the packet (Error Code) is used to acknowledge the command response when the packet is sent properly. Refer to the Command Set Table.

Figure 2.

Timing Diagrams

Get Command Structure:

Figure 3.

3rd Byte 4th Byte 5th Byte 6th Byte 1st Byte 2nd Byte

Payload Mid-Byte

Payload LSB

CRC MSB CRC LSB Error Code

Payload MSB



Set Command Structure:

Enable Sampling (ES) Command Structure:

𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫�� Period

Table 3.

𝐭𝐭𝟏𝟏 (µ𝒔𝒔) 𝐭𝐭𝟐𝟐 (µ𝒔𝒔) 𝐭𝐭𝟑𝟑 (µ𝒔𝒔) Description

0 to …*

99600

80

10 SPS 16600 60 SPS 9926 100 SPS 912 1000 SPS 130 4800 SPS 26 9600 SPS

* No delay or any delay as long as all 6 bytes are clocked out prior to 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷��going high. (See 𝑡𝑡2 )

Figure 4.

Figure 5.

Figure 6.



System Behavior

Start-up and Self-Calibration Mode When the system powers ON, it starts reading the data from EEPROM and goes to the internal calibration mode. The LED indicator starts blinking until it receives the first sample from the ADC. *Note: Do not drive the 𝐶𝐶𝐶𝐶 line low until the device has booted up completely. The WHITE LED turns off once the board has booted and is ready to communicate. This process takes ~3 seconds. Also ensure that the 𝐶𝐶𝐶𝐶 line is not driven low unless the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� is also low. *Note: When power is applied to the system, it enters Sleep-Mode and 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� stays high until it receives the ES command. Wrong CRC Error When the system receives a packet with an incorrect CRC, it goes to the default state that replies with the first byte of the packet as an Error Code followed by the ADC data and CRC.

Wrong CMD Error When the system receives a packet with an undefined command, unexpected command*, and undefined payload it goes to the default state that replies with the first byte of the packet as an Error Code followed by the ADC data and CRC.

* When unexpected command happens, the system returns Error Code following with zeros and the CRC values.

Error Codes

Table 4.

Error Code Description

CMD No Error Occurred (See Table 7./CMD Column) 0xFF Wrong CMD Value** 0xFE Wrong CRC Value 0xFD Wrong CMD Value + Wrong CRC Value

**Wrong CMD can occur for the following scenarios:

• Undefined commands • Unexpected commands (I.E. sending a command other than enable sampling (ES) when in Sleep-Mode) • Undefined payload (occurs in ADC sampling rate command ONLY (WADCSPS))



Sampling Rate Change When a sampling rate change is requested it will take no more than 1 second to see the change in the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� period.

Sampling Rates

Table 5.

SPS Code (Payload) Sampling Rate

0x04 10 SPS 0x05 60 SPS 0x06 100 SPS 0x07 1000 SPS 0x08 4800 SPS 0x09 9600 SPS

Error Code

No Error Occurred

Undefined Command Unexpected Command Undefined Payload

Wrong CMD Value Wrong CRC Value Wrong CMD Value

+ Wrong CRC Value

Figure 7.



Shunt Switch Feature

RSHSWS (Read Shunt Switch State) RSHSWS command returns the current state of the shunt switch in the last byte of the payload (LSB)

Table 6.

Shunt Switch (Payload) State

0x00 OFF 0x01 ON

ESHSW (Enable Shunt Switch) ESHSW command enables the shunt switch.

DSHSW (Disable Shunt Switch) DSHSW command disables the shunt switch.

*Note: Using both of ESHSW and DSHSW commands will increase the high period of the 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� line by a maximum of 120ms after the command is sent.

Power Management ES and DS commands have been implemented to turn OFF/ON the sampling system to manage the power consumption.

DS (Disable Sampling; Sleep-Mode) DS command with a correct CRC makes the system go to Sleep-Mode. The device shuts down the sampling system after replying to the master device in the next 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷��period.

*Note: When the system is in the Sleep-Mode, 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷�� stays high and the current draw (instrument only) drops down to ~12mA.

ES (Enable Sampling; Wake-Mode) It requires 32 bytes of data to be sent to exit Sleep-Mode, where the first 26 bytes will be discarded (dummy bytes just to fill the FIFO buffer), and the last 6 bytes must follow the ES command structure (see Table 7.). If the system is woken up with an incorrect CRC or command, it will reply to master with an Error Code (first byte) followed by three zeros followed by a CRC, it will then go back to Sleep-Mode.

*Note: The ES command must be sent to enable the sampling system. The current draw in this state (instrument only) is ~19mA.



Command-Set List Table 7.

Type Name Description

MOSI Line Packet Structure (Master to QIA123) MISO Line Packet Structure (QIA123 to Master)

Payload Payload Payload CMD CRC MSB

CRC LSB Error Code

Payload Payload Payload CRC MSB

CRC LSB

1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte

Get RADC Read ADC Value 0xXX 0xXX 0xXX 0x00 CRC MSB CRC LSB See

Table 4.

ADC-

MSB

ADC-

Mid-Byte ADC-LSB CRC MSB CRC LSB

Get RCWCALNZ

Read Clockwise

Calibration

Natural Zero

0xXX 0xXX 0xXX 0x01 CRC MSB CRC LSB

See

Table 4. MSB Mid-Byte LSB CRC MSB CRC LSB

Get RCWCALP1

Read Clockwise

Calibration Point

One


See


Get RCWCALP2

Read Clockwise

Calibration Point

Two


See


Get RCWCALP3

Read Clockwise

Calibration Point

Three


See




Get RCWCALP4

Read Clockwise

Calibration Point

Four


See


Get RCWCALP5

(+Span)

Read Clockwise

Calibration Point

Five (Span)

0xXX

0xXX

0xXX 0x06 CRC MSB CRC LSB

See


Get RCCWCALP1

Read Counter

Clockwise

Calibration Point

One


See


Get RCCWCALP2

Read Counter

Clockwise

Calibration Point

Two


See


Get RCCWCALP3

Read Counter

Clockwise

Calibration Point

Three


See


Get RCCWCALP4

Read Counter

Clockwise

Calibration Point

Four

0xXX 0xXX 0xXX 0x0A CRC MSB CRC LSB

See


Get RCCWCALP5

(-Span)

Read Counter

Clockwise

Calibration Point

0xXX 0xXX 0xXX 0x0B CRC MSB CRC LSB

See




Five (Span)

Get RFSSN

Read FUTEK

Sensor Serial

Number

0xXX 0xXX 0xXX 0x0C CRC MSB CRC LSB

See


Get RFISN

Read FUTEK

Instrument Serial

Number

0xXX 0xXX 0xXX 0x0D CRC MSB CRC LSB

See


Get RFRN Read Firmware

Revision Number 0xXX 0xXX 0xXX 0x0E CRC MSB CRC LSB

See


Get RADCSPS Read ADC

Sampling Rate 0xXX 0xXX 0xXX 0x0F CRC MSB CRC LSB

See

Table 4. 0x00 0x00

See

Table 5. CRC MSB CRC LSB

Set WADCSPS Write ADC

Sampling Rate 0xXX 0xXX

See

Table 5. 0x10 CRC MSB CRC LSB

See

Table 4.

ADC-

MSB

ADC-


Set ES Enable Sampling 0xXX 0xXX 0xXX 0x11 CRC MSB CRC LSB See

Table 4. 0x00 0x00 0x00 CRC MSB CRC LSB

Set DS Disable Sampling 0xXX 0xXX 0xXX 0x12 CRC MSB CRC LSB See

Table 4.

ADC-

MSB

ADC-


Get RSHSWS Read Shunt

Switch State 0xXX 0xXX 0xXX 0x13 CRC MSB CRC LSB

See

Table 4. 0x00 0x00

See

Table 6. CRC MSB CRC LSB

Set ESHSW Enable Shunt

Switch 0xXX 0xXX 0xXX 0x14 CRC MSB CRC LSB

See

Table 4.

ADC-

MSB

ADC-


Set DSHSW Disable Shunt

Switch 0xXX 0xXX 0xXX 0x15 CRC MSB CRC LSB

See

Table 4.

ADC-

MSB

ADC-


*Note: 0xXX = Don’t care



Packet and CRC Examples RFSSN Command (Read FUTEK Sensor Serial Number):

u16 crc16(u16 crc, const u8 *buffer, size_t len); function (see CRC Calculations and References) has been used as a reference to calculate the CRC for the example above: // CRC calculation for the second MISO transaction, MSB = 0x0C and LSB = 0x12 u8 BUFFER[] = {0x12, 0xE3, 0x01, 0x0C}; u16 crc16(0xFFFF, BUFFER, 4);

then function returns 0x3FF5

MISO 0x00 0x80 0x01 0xCE 0xCC 0x0E

MOSI 0x00 0x00 0x00 0x0C 0x74 0x03

0x0C 0x01 0xE3 0x12 0x3F 0xF5

0x00 0x00 0x00 0x00 0x24 0x00

DRDY 1st (MSB)

2nd 3rd 4th (LSB)

Figure 8.



Firmware Revision Revision 1.6

CRC Calculations and References The CRC calculation has been implemented (full duplex) per the links below.

https://github.com/torvalds/linux/blob/master/include/linux/crc16.h

https://github.com/torvalds/linux/blob/master/lib/crc16.c

https://github.com/torvalds/linux/blob/master/include/linux/crc16.h

https://github.com/torvalds/linux/blob/master/lib/crc16.c

qia123 spi communication guide · qia123 spi communication guide drawing number em1035 · revision...

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