putting fpgas to work in software defined radio systems

8/7/2019 putting fpgas to work in software defined radio systems

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EE Times-India | eetindia.com

By Rodger H. Hosking

Pentek, Inc.

FPGAs are becoming an in-

creasingly important resource

for software radio systems. Thisseries of articles introduces the

basics of software radio fol-

lowed by a brief review of the

evolution of programmable

logic technology which now

offers significant advantages

for implementing software

radio functions. We begin ourdiscussion with the basic ele-

ments of a software radio re-

ceiver system.

The front end usually con-tains an analogue RF ampli-

fier and often an analogue RF

translator (Figure 1). This trans-

lates the high frequency RF sig-

nals down to a frequency that

an A/D converter can handle.

This is usually below 100 MHz

and is often an IF output. The

A/D output feeds the digitaldownconverter (DDC) stage,

which is typically contained in

a monolithic chip which formsthe heart of a software radio

system. Notice, that after the

signal is digitized by the A/D

converter, all further opera-

tions are performed by digital

signal processing hardware.

In Figure 2 we ranked

some of the popular signal

processing tasks associatedwith software-defined ra-

dio (SDR) systems on a two

axis graph, with computeProcessing Intensity on the

vertical axis and Flexibility on

the horizontal axis.

What we mean by process

intensity is the degree of high-

ly-repetitive and rather primi-

tive operations. At the upper

left are dedicated functions

like A/D converters and DDCs

that require specialized hard-

ware structures to complete

the operations in real time.ASICs (Application Specific

ICs) are usually chosen for

these functions.Flexibility pertains to the

uniqueness or variability of

the processing and how likely

the function may have to bechanged or customized for

any specific application. At

the lower right are tasks like

analysis and decision mak-

ing which are highly vari-

able and often subjective.

Programmable general pur-

pose processors or DSPs are

usually chosen for these taskssince these tasks can be easily

changed by software.

Now let’s temporarily stepaway from the software radio

tasks and take a deeper look at

programmable logic devices.

Programmable Logic

As true programmable gate

functions became available

in the 1970s, they were used

extensively by hardware en-gineers to replace control

logic, registers, gates and

state machines which oth-erwise would have required

many discrete, dedicated ICs.

Often these programmable

logic devices were onetime

factory-programmed parts

that were soldered down and

never changed after the de-

sign went into production.

These programmable

logic devices were mostly

the domain of hardware

engineers and the softwaretools were tailored to meet

their needs. You had toolsfor accepting Boolean equa-

tions or even schematics to

help generate the intercon-

nect pattern for the growing

number of gates.

Then, programmable logic

vendors started offering

predefined logic blocks for

flip-flops, registers and coun-ters, giving the engineer a

leg up on popular hardware

functions. Nevertheless, thehardware engineer was still

intimately involved with

testing and evaluating the

design using the same skills

he needed for testing dis-

crete logic designs. He had

to worry about propagation

delays, loading, clocking and

synchronizing, which were

all tricky problems that usu-

ally had to be solved the hard

way: with oscilloscopes orlogic analyzers.

FPGAs

It’s virtually impossible to keep

up to date on FPGA technol-

ogy, since new advancements

are being made every day. The

hottest features are processor

cores inside the chip, computa-

tion clocks of up to 500 MHz,

and lower core voltages to keep

power and heat down.About five years ago, dedi-

cated hardware multipliers

started appearing and nowyou’ll find literally hundreds

of them on-chip as part of the

DSP initiative launched by vir-

tually all FPGA vendors. High

memory densities coupled

with very flexible memory

structures meet a wide range

of data flow strategies. Logic

slices with the equivalent of

over 10 million gates result

from silicon geometries shrink-

ing down to 0.1 micron.BGA and flip chip packages

Putting FPGAs to work in software radio systems

Software radio

Figure 1: Block diagram of a typical software radio system.

Figure 2: Software radio tasks.

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provide plenty of I/O pins tosupport on-board gigabit se-

rial transceivers and other

user-configurable system in-terfaces. New announcements

seem to be coming out every

day from chip vendors like

Xilinx and Altera in a never-

ending game of outperform-

ing the competition.

To support such powerful

devices, new design tools are

appearing that now open upFPGAs to both hardware and

software engineers. Instead

of just accepting logic equa-tions and schematics, these

new tools accept entire block

diagrams as well as VHDL and

Verilog definitions.

Choosing the best FPGA

vendor often hinges heavily on

the quality of the design tools

available to support the parts.

To minimize some of the tricky

timing work for hardware engi-

neers, excellent simulation and

modelling tools help to quicklyanalyze worst case propagation

delays and suggest alternaterouting strategies to minimize

them within the part. This can

really save one hours of tedioustroubleshooting, not only dur-

ing design verification but also

for production testing.

In the last few years, a

new industry of third party

intellectual property (IP) core

vendors now offers thou-

sands of application-specific

algorithms. These are readyto drop into the FPGA de-

sign process to help beat the

time-to-market crunch andto minimize risk.

FPGAs for Software Radio

Like ASICs, all the logic ele-

ments in FPGAs can execute in

parallel. This includes the hard-

ware multipliers, and you can

now get over 500 of them on

a single FPGA. This is in sharp

contrast to programmable

DSPs, which normally have just

a handful of multipliers thatmust be operated sequentially.

FPGA memory can now beconfigured with the design

tool to implement just the

right structure for tasks thatinclude dual port RAM, FIFOs,

shift registers and other

popular memory types. These

memories can be distributed

along the signal path or inter-

spersed with the multipliers

and math blocks, so that the

whole signal processing task

operates in parallel in a sys-tolic pipelined fashion.

Again, this is dramatically

different from sequentialexecution and data fetches

from external memory as

in a programmable DSP. As

we said, FPGAs now have

specialized serial and paral-

lel interfaces to match re-

quirements for high- speed

peripherals and buses.

As a result, FPGAs have

significantly invaded the

application task space as

shown by the centre bubblein Figure 3. They offer the

advantages of parallel hard-ware to handle some of

the high process intensity

functions like DDCs and thebenefit of programmability

to accommodate some of

the decoding and analysis

functions of DSPs. These

advantages may come at the

expense of increased power

dissipation and increased

product costs. However,

these considerations areoften secondary to the per-

formance and capabilities of

these remarkable devices.Figure 4 shows represen-

tative members from four

generations of Xilinx de-

vices currently used in Pentek

Products: the Virtex-E, Virtex-II,

Virtex-II Pro, and Virtex-4. The

Virtex-E family includes a mix

of configurable logic blocks,

logic cells, system gates and

block memory.

The Virtex-II family added

built in hardware multipliersthat support digital filters,

Figure 3: FPGAs Bridge the SDR Application Task Space.

Figure 4: Evolving FPGA Generations.Figure 5: Unused system gates and RAM available allows users to include

custom algorithms.





EE Times-India | eetindia.com

averagers, demodulators and

FFTs, a major benefit for soft-ware radio signal processing.

The Virtex-II Pro family dramat-

ically increased the number of

hardware multipliers and also

added embedded PowerPC

microcontrollers.

The Virtex-II Pro is also thefirst family to incorporate

RocketIO multigigabit serial

transceivers to support the new

switched gigabit serial fabrics.The Virtex-4 family is offered as

three subfamilies that dramati-

cally boost clock speeds and

reduce power dissipation overprevious generations.

The Virtex-4 LX family

delivers maximum logic and

I/O pins while the SX family

boasts of 512 hardware mul-

tipliers for maximum DSP per-

formance. The FX family is agenerous mix of all resources

and is the only family to of-

fer RocketIO, PowerPC cores,

and the newly added gigabitEthernet ports.

Figure 5 shows a sampling

of FPGAs and various Pentek

hardware products that usethem. Each hardware prod-

uct uses some of the FPGA

resources to implement stan-

dard factory functions of the

products such as interfaces,

data formatting, state ma-

chines, and operating modes.However, since many of the

newer FPGAs are so large,

even after all the standard

factory functions have beenimplemented, a significant

percentage of FPGA resources

remain unused and available

for customer use.This chart shows the per-

centage of unused system

gates and RAM available to

the user for extending the

FPGA to include custom

algorithms. To address this

requirement, Pentek has de-veloped the GateFlow FPGA

Design Resources.



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