project sram stevo bailey kevin linger roger lorenzo john thompson ece 4332: intro to vlsi
TRANSCRIPT
Project SRAM
Stevo BaileyKevin Linger
Roger LorenzoJohn Thompson
ECE 4332: Intro to VLSI
PICo’s Projects
1. 1 Mb low-power SRAM– (Ea)2(tp)(A)(Pidle)
2. 64 kb high-speed cache– (Ea)(tp)2(A)(Pidle)
ECE 4332: Intro to VLSI
Problem Description
• 1 Mb SRAM• 32-bit words• Inputs: address, input word, read, write, clock• Outputs: output word• Robust across process, voltage, and temp• Special features optional• Minimize power
ECE 4332: Intro to VLSI
Claim
ECE 4332: Intro to VLSI
We designed and simulated a competitive 1 Mb SRAM.
1. SRAM Architecture
2. Bitcell Optimizations
3. SRAM Model Simulations
4. Layout Optimizations
5. Results and Further Work
SRAM Block Diagram
[final block diagram]
ECE 4332: Intro to VLSI
Block 0 Block 1 Block 63
Precharge Precharge Precharge
Sense/Write Amps
Row Decoder
to Write Amp to Write Amp to Write Amp
Block MUX
Block DeMUX
MUX
Sense/Write Amps
MUX
Sense/Write Amps
MUX
Claim
ECE 4332: Intro to VLSI
1. SRAM Architecture
2. Bitcell Optimizations
3. SRAM Model Simulations
4. Layout Optimizations
5. Results and Further Work
Bitcell
• 6T-bitcell – 0.816 µm2
ECE 4332: Intro to VLSI
WL WL
BL BLB
2x2 bitcell array
Bitcell
ECE 4332: Intro to VLSI
Bitcell
ECE 4332: Intro to VLSI
Bitcell
[SNM monte carlo]
ECE 4332: Intro to VLSI
Claim
ECE 4332: Intro to VLSI
1. SRAM Architecture
2. Bitcell Optimizations
3. SRAM Model Simulations
4. Layout Optimizations
5. Results and Further Work
SRAM Model
ECE 4332: Intro to VLSI
bitcellm=1
bitcellm=r-2
bitcellm=1
bitcellm=c-2
bitcellm=1
bitcellm=r-2
bitcellm=c-2
bitcellm=1
VDD
LWL2
LWL1
BL1 BLB1 BL2 BLB2
BLOCK 0
SRAM Model
Rαb·c
Cαb·c
BDRαc
CαcGWL
LWL
m=1
m=b-1
WORD LINES (x2)
5
VDD VDDBL BLB
SA SAB
READ/ WRITE MUX (x2)
c 32
m= -1c 32
m= -1
BL BLB
CD
WAO WAOB
CDW
VDD VDD
5
ECE 4332: Intro to VLSI
• C values obtained from parasitic extraction• R values from NCSU wiki on FreePDK45 (http://www.eda.ncsu.edu/wiki/FreePDK45:Metal_Layers)
SRAM ModelVDD
BLBBL
SAE
SAE SAE
Out OutB
SENSE AMP 2
BLBBL
VDD
Out OutB
SAE
SENSE AMP 1
Sense Amp Delay1 192 ps2 147 ps
ECE 4332: Intro to VLSI
ECE 4332: Intro to VLSI
SRAM Model
Example decoder with predecoding stage
[We omitted this figure because of copyright laws. The image is in the Rabaey book and available online. If you really, really need to see it, go to http://bwrc.eecs.berkeley.edu/icbook/slides.htm, download the power point slides for chapter 12, and go to slide 57.]
ECE 4332: Intro to VLSI
SRAM Model
A
VDD
m=7
m=7
BD
m=6
m=6
m=34
6:64 BLOCK DECODER
(x2)
VDD
A
m=15
m=15
GWLm=193
m=14 for each
8:256 ROW DECODER
(x2)
SRAM Model Results
ECE 4332: Intro to VLSI
SRAM Model Results
ECE 4332: Intro to VLSI
256 Rows, 64 Columns, 64 Blocks
ECE 4332: Intro to VLSI
Timing Diagram
Claim
ECE 4332: Intro to VLSI
1. SRAM Architecture
2. Bitcell Optimizations
3. SRAM Model Simulations
4. Layout Optimizations
5. Results and Further Work
ECE 4332: Intro to VLSI
Layouts
Addr
ess
Dec
oder
s
Write/Sense AmpsBlock DeMuxWrite/Sense Amps Block DeMux
256 by 64 Block
ECE 4332: Intro to VLSI
Layouts
2x2 Bit Cells
2x Read/Write Mux
Sense Amp
WL[0]
WL[1]
BL[0] BLB[0] BL[1] BLB[1]VDDGND VDD GNDGNDGND
SA[0] SAB[0] SA[1] SAB[1]
WAB[1]WA[1]WAB[0]WA[0]
Enable Enable
SAOB[1]SAO[1]
SAOB[0]SAO[0]
Claim
ECE 4332: Intro to VLSI
1. SRAM Architecture
2. Bitcell Optimizations
3. SRAM Model Simulations
4. Layout Optimizations
5. Results and Further Work
ECE 4332: Intro to VLSI
Results
• verified functionality at
• all process corners (TT, FF, FS, SF, SS)
• VDD = { 0.54, 0.60, 0.66, 1.0, 1.1, 1.2 } volts
• temp = { 0°, 27°, 54° } Celsius
• SS forced a longer clock period for a read
ECE 4332: Intro to VLSI
MetricsTotal Energy 1.46 pJ
Read Energy 1.43 pJ
Write Energy 1.57 pJ
Read Delay 2.9 ns
Write Delay 1.97 ns
Total Delay 2.9 ns
Idle Power 208 µW
Sleep Power 99.2 µW
Bitcell Area 0.819 µm2
Total Area 1.04 mm2
Final Metric 1.337x10-36 J2·s·mm2·W
ECE 4332: Intro to VLSI
Error Correcting Code
1234567891011
1213
1415
161718
1920
2122
232425
2627
2829
3031
P0
P1
P2
P3
P4
P5
P6 0
OutputP0
Error
detected
Double
error
Single
error
P1
P2
P3
P4
P5
P6
32
Input
32
Corrected
output
32
Input
= 4-input XOR
Delay 0.3634 ns
Energy 53.4 fJ
Error Correcting Code
SEC-DED
ECE 4332: Intro to VLSI
SourcesB. Jacob, S. W. Ng, and D. T. Wang, Memory systems: Cache, DRAM, disk, Burlington, MA: Morgan Kaufmann, 2008, p. 282.
B. S. Amrutur and M. A. Horowitz, “Fast low-power decoders for RAMs,” JSSC, vol. 36, no. 10, 2001.
J. F. Ryan and B. H. Calhoun, “Minimizing offset for latching voltage-mode sense amplifiers for sub-threshold operation,” ISQED, 2008.
J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits, 2nd ed., Upper Saddle River: Pearson, 2003, p. 508.
J. Yeung and H. Mahmoodi, "Robust sense amplifier design under random dopant fluctuations in nano-scale CMOS technologies," SOC Conference, 2006 IEEE International , 2006, pp. 261-264.
L. Hamouche and B. Allard, “Low power options for 32nm always-on SRAM architecture,” Solid State Electronics, 2011.
ECE 4332: Intro to VLSI
Acknowledgements
Benton Calhoun, PICo liason
Team XOR (2010)• Dominic Carr• Jae Park• Daniel Reyno
Team 2 (2010)• Yanran Chen• Cary Converse• Chenqian Gan• David Moore
Questions?
ECE 4332: Intro to VLSI