project: ieee p802.15 working group for wireless personal area networks (wpans)
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Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANS). Submission Title: [Implementation of Viterbi decoder for MB-OFDM System] Date Submitted: [November 2004] Revised: [] Source: [Sang-sung Choi, Sung-woo Choi] - PowerPoint PPT PresentationTRANSCRIPT
November 2004
ETRISlide 1Submission
doc.: IEEE 802. 15-04-0623-00-003a
Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANS)
Submission Title: [Implementation of Viterbi decoder for MB-OFDM System]
Date Submitted: [November 2004]Revised: []
Source: [Sang-sung Choi, Sung-woo Choi] Company [Electronics and Telecommunications Research Institute] Address [161 Gajeong-dong, Yuseong-gu, Daejeon, 305-350 Korea] Voice : [+82-42-860-6722], FAX : [+82-42-860-5199], E-mail [[email protected]]
Re: [Technical contribution]
Abstract: [This presentation presents the implementation result of Viterbi decoder for MB-OFDM UWB system]
Purpose: [Technical contribution to implement Viterbi decoder proposed for MB-OFDM UWB system]
Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual or organization. The material in this document is subject to change in form and content after further study. The contributor reserves the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15.
November 2004
ETRISlide 2Submission
doc.: IEEE 802. 15-04-0623-00-003a
Implementation of Viterbi Decoder for MB-OFDM System
Sang-Sung Choi ([email protected])
Sung-Woo Choi ([email protected])
E T R I
www.etri.re.kr
November 2004
ETRISlide 3Submission
doc.: IEEE 802. 15-04-0623-00-003a
Introduction
Implemented architecture
Implementation result
Consideration for full rate
Conclusion
Outline
November 2004
ETRISlide 4Submission
doc.: IEEE 802. 15-04-0623-00-003a
MB-OFDM UWB system uses rate 1/3, k=7 convolutional code
Information bit rates up to 480Mbps
- Very high speed Viterbi decoder is needed
ETRI is developing MB-OFDM UWB chip with 200Mbps data rate
Modem architecture based on 4-parallel architecture
Viterbi decoder is designed using 2-parallel architecture
In this presentation,
- Implementation of Viterbi decoder architecture for mandatory
mode
- Simulation results for important parameters
- Hardware synthesis result
- Consideration for full rate Viterbi decoder implementation
Introduction
November 2004
ETRISlide 5Submission
doc.: IEEE 802. 15-04-0623-00-003a
Viterbi Decoder Target Performance
Basic Coding gain of R=1/3 , K=7 convolutional code -> 5.7 dB at BER 10-5 Reference : Irwin M. Jacobs, “Practical Applications of Coding”, IEEE Trans. Comm. , May 1974
5.7 dB
0 1 2 3 4 5 6 7 8 9 1010
-6
10-5
10-4
10-3
10-2
10-1
100
Eb/No
UncodedTheo. uncodedSoft decision
November 2004
ETRISlide 6Submission
doc.: IEEE 802. 15-04-0623-00-003a
Max data rate
Operation clock
MinimumRequired
2 ParallelSame clock
source
Mandatory 200 Mbps 200 MHz 100MHz 132MHz *
Full spec. 480 Mbps 480 MHz 240MHz 264MHz **
* Mandatory mode minimum sampling time - 7.58ns (1/132M) ** Full spec. mode minimum sampling time - 3.79ns (1/264M)
Viterbi Decoder Requirement
November 2004
ETRISlide 7Submission
doc.: IEEE 802. 15-04-0623-00-003a
Implemented Architecture Block diagram
Input data for 2-parallel Architecture
- n-th data input Rn(r0, r1, r2 ), (n+1)-th data input Rn+1(r0, r1, r2)
- input clock is 132MHz for mandatory mode chip
Full parallel ACS (64 states)
each ACS – radix-4 architecture
Trace back method : depth(L) = 42
Decoded output data - 2 bits per 132MHz
BMRn
Rn+1
bm000000
bm000001
bm111111
ACS TBsel
minst
output
November 2004
ETRISlide 8Submission
doc.: IEEE 802. 15-04-0623-00-003a
Performance comparison of soft/hard decision decoding - r=1/3 , AWGN
Input bits decision
3 bit soft decision has similar performance to 4 bit soft decisionSoft decision is 2dB superior to hard decision at BER=10-5 This architecture - 3 bit soft decision
0 1 2 3 4 5 6 7 8 910
-6
10-5
10-4
10-3
10-2
10-1
100
Eb/No
Thoe. uncodedUncodedHardSoft 3bitSoft 4bit
November 2004
ETRISlide 9Submission
doc.: IEEE 802. 15-04-0623-00-003a
Trace-back Depth Simulation
r=11/32 , AWGN Trace back depth (L) >=36 have similar performance This architecture – L=42
0 0.5 1 1.5 2 2.5 3 3.5 410
-6
10-5
10-4
10-3
10-2
10-1
100
Eb/No
BE
R
UncodedL = 56L = 48L = 42L = 36L = 28L = 24
November 2004
ETRISlide 10Submission
doc.: IEEE 802. 15-04-0623-00-003a
Timing diagram
Total Viterbi decoder latency – 47xTclk (about 2L)
Internal Delay
Tclk x 47
CLK
VD_en
Valid_in
Out_ind
OutBits
Input_5..0
Tclk
. . .
. . .
. . .. . .
. . .
November 2004
ETRISlide 11Submission
doc.: IEEE 802. 15-04-0623-00-003a
Device : Xilinx x2v6000 ff1152 -5
Constraint : Time constraint 100MHz
Logic Utilization:- Number of Slice Flip Flops : 5,675 out of 67,584 8%- Number of 4 input LUTs : 4,588 out of 67,584 6%
Logic Distribution:- Number of occupied Slices 5,110 out of 33,792 15%
Total equivalent gate count for design : 87,084
Maximum operation frequency : 92.5MHz - Mandatory mode chip with 132MHz is possible- Full rate mode chip with 264MHz is difficult
Implementation Result
November 2004
ETRISlide 12Submission
doc.: IEEE 802. 15-04-0623-00-003a
Critical Path Analysis
BM[5:0]
PM[8:0]
D9bit
9bit
BM0[4:0]
BM1[4:0]
D
D
D
BM Module ACS Module
Route delay
BM[5:0]
Post Map timing report- Critical path delay time is about 5ns- 9 bit adder 2 stage + (4x1 multiplexer) + other delay- Less than mandatory mode minimum time(7.58ns)
Post Place & Route timing report
- 2.7 ns (logic) + 7.8 ns (route) + other delay
Route delay is big in FPGA!
It can be avoided in chip design
November 2004
ETRISlide 13Submission
doc.: IEEE 802. 15-04-0623-00-003a
Implemented Viterbi decoder Performance
Coding gain of rate 1/3 is 5.7 dB, equivalent to theoretical performance.Rate 11/32 is 0.5 dB inferior to rate 1/3 code.
0 1 2 3 4 5 6 7 8 910
-6
10-5
10-4
10-3
10-2
10-1
100
EbNo
Uncodedr = 1/3r = 11/32
November 2004
ETRISlide 14Submission
doc.: IEEE 802. 15-04-0623-00-003a
Consideration for Full Rate
To implement using current architecture- 9bit Adder 2 + (4x1MUX) is possible in 3.79ns- But implementation is difficult due to additional delay
Extend current architecture to 4-parallel (radix-16) architecture- 9bit Adder 2 + (16x1MUX) is possible in 7.58ns- Implementation is possible- Number of adders increase 4 times over that of 2-parallel - Much more complex BM control and other control logic- Expect 100% increase in hardware complexity
More Solution- Bit-level : Input pipeline in feed-back path - Algorithm-level : cascaded feed-forward and backward method, etc.
November 2004
ETRISlide 15Submission
doc.: IEEE 802. 15-04-0623-00-003a
Conclusion
Suggested architecture of Viterbi decoder for MB-OFDM mandatory mode
To verify the architecture, hardware design using FPGA is done
FPGA synthesis result show mandatory mode chip is possible using current architecture
Estimated gate count of Viterbi decoder is 90K
From synthesis result, full rate Viterbi decoder needs 4-parallel architecture or other algorithms to implement