prof. ian o'connor lyon institute of nanotechnology

Institut des Nanotechnologies de Lyon UMR CNRS 5270 http://inl.cnrs.fr

Photonic Interconnect Solutions for Manycore architectures

Prof. Ian O'ConnorLyon Institute of Nanotechnology

[email protected]

IRT Nanoelec Workshop Photonique sur Silicium

Paris, 27th November 2017


”On-chip optical interconnect could become reality in five years” (I. O’Connor, 2001)

My life with optical interconnect

”On-chip optical interconnect could become reality ” (I. O’Connor, 2017)

IEEE Transactions on Emerging Topics in Computing, 2016

one day


Kilo-core processors and dark silicon

MPPA,1024 cores?

20052003

Intel,Polaris,80cores

Tilera64

TILE-Gx72

TILE-Gx100

Single-chipCloudComputer,48cores

CELL

2001 2007 2009 2011

MPPA,256 cores, 28nm,2012

Num

ber

of c

ores

2013 2015 year

Challenge: it costs more energy to move data than to compute with them

3 Tera-operations/sec 64b x 9 Tera-operands moved/sec Av. wire distance 1mm 0.1pJ/bit x 576 Tbits/s -> 58W! [Intel Core i7 family (Haswell architecture, 22nm) : [email protected] , [email protected])]


Progress over 10 years

First worldwide demonstrator Vladimir Stojanović,

Nature 528, Dec. 2015

Scalable and realistic design Jiang Xu, IEEE JETC, 2014

Interposer-like implementation Yvain Thonnart,

Leti Innovation Days, 2013

Massive integration Raymond Beausoleil,

ISCA, 2008

First system level study Ian O’Connor, DATE, 2005


Hype cycle

First worldwide demonstrator Vladimir Stojanović,

Nature 528, Dec. 2015

Scalable and realistic design Jiang Xu, IEEE JETC, 2014

Interposer-like implementation Yvain Thonnart,

Leti Innovation Days, 2013

Massive integration Raymond Beausoleil,

ISCA, 2008

Very first system level study Ian O’Connor, DATE, 2005


multiple

multiple

Approaches

1.  Replace electrical wires with waveguides (single wavelength, single signal per waveguide, no runtime reconfiguration)

2.  Replace electrical network with wavelength-dependent topology (multiple wavelengths, multiple signals per waveguide, no runtime reconfiguration)

3.  Replace electrical network with energy-efficient wavelength topology (multiple wavelengths, multiple signals per waveguide, ) runtime reconfiguration

multiple

multiple


Approach 1

•  Single writer single reader (SWSR)

Electrical data

Electrical data

λr

Tx

λr

Rx

L. Chen et al., Optics Express, 17, 15248 (2009)


device characteristics

system specifications

Optical-electrical specifications

•  Identical specifications for optical and electrical links (length, frequency)

•  ITRS technology data used

•  (65-45-32nm gate length predictive models)


Exploration results

Gate area reduction factor vs. interconnect length

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25Length (mm)

BPT65 - 1.1um pitchBPT45 - 1.1um pitchBPT32 - 1.1um pitchBPT65 - 1.1um pitch D13BPT45 - 1.1um pitch D13BPT32 - 1.1um pitch D13

Power reduction factor vs. interconnect length

0

1

2

3

4

5

6

7

8

9

10

0 5 10 15 20 25Length (mm)

BPT65 - 1.1um pitchBPT45 - 1.1um pitchBPT32 - 1.1um pitchBPT65 - 1.1um pitch D13BPT45 - 1.1um pitch D13BPT32 - 1.1 um pitch D13

Delay reduction factor vs. interconnect length

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25Length (mm)

BPT65 - 1.1um pitchBPT45 - 1.1um pitchBPT32 - 1.1um pitchBPT65 - 1.1um pitch D13BPT45 - 1.1um pitch D13BPT32 - 1.1um pitch D13

Gate area reduced by 60x-90x wrt electrical

Total power reduced by 6x-10x wrt electrical

Link delay reduced by 2x-3x wrt electrical

world's

first

demonstr

ation of

wafer-bo

nded

integrat

ed optic

al

intercon

nect

IMEC/ LETI / INL


Approach 2

•  Multiple writer multiple reader (MWMR)

Electrical data

Electrical data

Electrical data

Electrical data

λr

Tx

λr λr

Rx

λg

Rx

λb

Rx

λr

Rx

λg

Rx

λb

Rx Tx

λg

Tx

λb

Tx

λr

Tx

λg

Tx

λb

λg

λb

A. Kazmierczak et al., Photonics Technology Letters, 17(7), 1447 (2005)


λ1 w1

w2

w3

w4

w5

w6

w7

w8

λ1

λ2

λ3

λ3

λ4

λ5

λ5

λ6

λ7

λ7

λ8

λ1

λ1

λ2

λ3

λ3

λ4

λ2

λ5

λ5

λ6

λ7

λ7

λ8

λ4 λ6 λ8

r1

r2

r3

r4

r5

r6

r7

r8

w1 à r4 : λ6 w1 à r6 : λ7 w4 à r1 : λ6

etc.

Crossbar!

λ-router


System-level virtual prototype •  NxN initiators (i) and targets (j): one pair of emitter-receiver circuits

per IP block •  multi-domain architecture: electronic (D/A), optoelectronic,

photonic (λ-router), software –  technologies : 0.13µm CMOS + III-V + SOI –  VCI protocol: optical transmission of 36 data bits,

electrical transmission of 8 control bits (wavelength selection)

W R A P P E R

VCI

VCI initiator i

36

SER

8

λ-router

λ,P

PDES

W R A P P E R

VCI

VCI target j

clk

in j/out j

Decoder

Demux

256

in i Drivers Lasers

TIA Comp

out i

I

photocurrent

36

36

SER

8

λ,P

PDES

photodiode

Decoder

Demux

256

in j Drivers Lasers

TIA Comp

clk1=36*clk

out j

photocurrent

V 36

clk

clk1=36*clk

system validation

max data rate 2*3Gbit/s BER < 10-18

latency ≈ 420ps power ≈ 10mW / link (one-

way, toggle factor 0.5) zero contention

parametric exploration


Approach 3 – CHAMELEON

•  Scalable reconfigurable ring architecture – Dynamic allocation of optical channel segments – Adaptive mechanisms to handle energy and

datarate constraints – up to 50% energy savings

S. Le Beux et al., Design Automation and Test in Europe (2014)


System-level assessment

•  Adaptive – 12 interface

architecture – 4-16 wavelengths/

channel – 10Gb/s data rate – Chip activity 15%

•  Energy-efficient – % savings with /

without laser tuning – 53% average saving


Need for Design Methodologies

1-models

2-simulations

3-exploration

Key enabler: Design

methodologies

Challenges: higher performances, higher power efficiency, higher integration

Key enabler: Emerging

technologies ring lasers 3D

Easily programmable and

power efficient processors

To

p-d

ow

n B

ott

om

-up


Last mile: challenges at physical level

•  Physical design tools – Curvilinear structures – Structure-functionality

entanglement •  Source integration strategy

– Off-chip source + on-chip modulators

– On-chip sources + direct modulation

•  Information coding strategy – Level-based coding – Pulse-based coding

•  Silicon real estate

Source: Mentor Graphics

Source: INL

Source: Technical University of Denmark


Last mile: challenges at system level •  Scale of integration

–  Optical I/O –  3D interposers –  On-chip interconnect

•  Simulation and design tools –  Vector-based optical signals –  Heterogeneous system

•  Network topology –  One size fits all (ring? mesh?) –  Adapting to requirements –  Intelligence in the routing

•  Killer application + ecosystem –  Manycore cache coherency? –  "Long" synapses in neural

accelerator hardware?

Source: Fraunhofer

Source: University of Colorado at Boulder

Source: HKUST


Thanks to

Sébastien Le Beux, Xavier Letartre, Hui Li, Christelle Monat, Zhen Li

Olivier Sentieys, Daniel Chillet, Cédric Killian, Jiating Luo, Van Dung Pham

Gabriela Nicolescu, Alain Fourmigue

Yvain Thonnart

Jiang Xu, Mahdi Nikdast (now at Colorado)


OPTICS 2018: 4th International workshop on Optical/Photonic Interconnects for Computing Systems

•  Co-located with DATE, Dresden, March 23rd 2018•  http://www.ece.ust.hk/~eexu/OPTICS.html •  General chairs: Jiang Xu, Sébastien Le Beux, Gabriela Nicolescu•  Some speakers from past editions

prof. ian o'connor lyon institute of nanotechnology

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