product data sheet stmp36xx - rockbox · 2 5-36xx-d1-1.02-050306 stmp36xx official product...

OFFICIAL PRODUCT DOCUMENTATION 5/3/06

PRODUCT DATA SHEET

Copyright © 2003-2006 SigmaTel, Inc.

All rights reserved.

SigmaTel, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makesno commitment to update the information contained herein. SigmaTel reserves the right to change or discontinue this product at any time, without no-tice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document.

The following are trademarks of SigmaTel, Inc., and may be used to identify SigmaTel products only: SigmaTel, the SigmaTel Logo, C Major, D Majorand Go-Chip. Windows Media and the Windows logo are trademarks or registered trademarks of Microsoft Corporation in the United States and/orother countries. Other product and company names contained herein may be trademarks of their respective owners.

5-36xx-D1-1.02-050306

STMP36xxAudio System on Chip

with USB OTG, LCD, Hard Drive, and Battery ChargerFourth-Generation Audio Decoder

Version 1.02 May 3, 2006

Host Processor (Optional)

FM Tuner

MicrophoneVoice Record

NAND Flash

Buttons/SwitchesHard Drive

HeadphonesSD/SDIO/MS

SDRAM/NOR

SPDIF

RechargeableBattery

LED/LCD/ColorDisplay

Hi-Speed USBOn-the-Go

ISO9001:2000 CertifiedIEC QC 080000:2005

(IECQ HSPM) Certified

2 5-36xx-D1-1.02-050306

STMP36xx

O F F I C I A L P R O D U C T D O C U M E N T A T I O N 5 / 3 / 0 6

The product shown in this data sheet is not designed for use in life support appliances, devices, or systemswhere malfunction of these products can reasonably be expected to result in personal injury. Any use ordistribution of this product in such applications is at your own risk. SigmaTel, Inc. does not assume any lia-bility arising out of the application or use of any product or circuit shown herein, and specifically disclaimsany and all liability, including without limitation special, consequential, or incidental damages. Supply of thisImplementation of AAC technology does not convey a license nor imply any right to use this Implementa-tion in any finished end-user or ready-to-use final product. An independent license for such use is required.

CUSTOMER SUPPORTAdditional product and company information can be obtained by going to the SigmaTel website at:http://www.sigmatel.com

Additional product and design information is available for authorized customers at: http://extranet.sigmatel.com

http://www.sigmatel.comhttp://extranet.sigmatel.com

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CONTENTSREVISION HISTORY..................................................................................................................... 21

1. PRODUCT OVERVIEW .................................................................................................................231.1. Hardware Features ......................................................................................................................... 231.2. Application Capability ...................................................................................................................... 241.3. Design Support ............................................................................................................................... 251.4. Additional Documentation ............................................................................................................... 251.5. STMP36xx System Block Diagram ................................................................................................. 261.6. STMP36xx Product Features .......................................................................................................... 27

1.6.1. ARM 926 Processor Core ................................................................................................. 271.6.2. On-Chip RAM and ROM ................................................................................................... 291.6.3. Interrupt Collector .............................................................................................................. 301.6.4. Default First-Level Page Table .......................................................................................... 301.6.5. External Memory Interface (SDRAM/NOR Flash Controller) ............................................ 301.6.6. DMA Controller .................................................................................................................. 311.6.7. Clock Generation Subsystem ............................................................................................ 311.6.8. Power Management Unit ................................................................................................... 321.6.9. USB Interface .................................................................................................................... 331.6.10. General-Purpose Media Interface (GPMI) ...................................................................... 331.6.11. Hardware Acceleration for ECC for Robust External Storage ......................................... 341.6.12. Memory Copy Unit .......................................................................................................... 341.6.13. Mixed Signal Audio Subsystem ....................................................................................... 351.6.14. Master Digital Control Unit (DIGCTL) .............................................................................. 351.6.15. Synchronous Serial Port (SSP) ....................................................................................... 351.6.16. I2C Interface .................................................................................................................... 351.6.17. General-Purpose Input/Output (GPIO) ............................................................................ 361.6.18. LCD Controller ................................................................................................................ 371.6.19. SPDIF Transmitter .......................................................................................................... 371.6.20. Rotary Decoder ............................................................................................................... 371.6.21. Dual UARTs .................................................................................................................... 371.6.22. Infrared Interface ............................................................................................................. 371.6.23. Low-Resolution ADC and Touch-Screen Interface ......................................................... 371.6.24. Pulse Width Modulator (PWM) Controller ....................................................................... 371.6.25. Camera Interface ............................................................................................................ 38

2. CHARACTERISTICS AND SPECIFICATIONS ............................................................................392.1. Absolute Maximum Ratings ............................................................................................................ 392.2. Recommended Operating Conditions ............................................................................................. 40

2.2.1. Recommended Operating Conditions for Specific Clock Targets ..................................... 412.3. DC Characteristics .......................................................................................................................... 42

3. ARM CPU COMPLEX ...................................................................................................................433.1. ARM 926 Processor Core ............................................................................................................... 433.2. JTAG Debugger .............................................................................................................................. 45

3.2.1. JTAG READ ID ................................................................................................................. 453.2.2. JTAG Hardware Reset ...................................................................................................... 453.2.3. JTAG Interaction with CPUCLK ........................................................................................ 45

3.3. Embedded Trace Macrocell (ETM) Interface .................................................................................. 46

4. CLOCK GENERATION AND CONTROL .....................................................................................474.1. Overview ......................................................................................................................................... 474.2. Crystal Oscillators ........................................................................................................................... 474.3. Clock Domains ................................................................................................................................ 474.4. Power Saving Features of the Clock Architecture ........................................................................... 494.5. Clock Dividers ................................................................................................................................. 49

4.5.1. Automatic HCLK Divider ................................................................................................... 494.6. Phase-Locked Loop (PLL) .............................................................................................................. 51

4.6.1. Frequency Program .......................................................................................................... 524.6.2. PLL Use in USB and SPDIF Modes .................................................................................. 524.6.3. VCO and Phase Followers ................................................................................................ 534.6.4. PFD and Charge Pump ..................................................................................................... 53

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4.7. Integrated USB 2.0 PHY Initialization Flow Charts ......................................................................... 544.8. Clocking During Reset .................................................................................................................... 554.9. Programmable Registers ................................................................................................................ 56

4.9.1. PLL Control Register 0 Description ................................................................................... 564.9.2. PLL Control Register 1 Description ................................................................................... 584.9.3. CPU Clock Control Register Description ........................................................................... 584.9.4. AHB, APBH Bus Clock Control Register Description ........................................................ 594.9.5. APBX Clock Control Register Description ......................................................................... 614.9.6. XTAL Clock Control Register Description ......................................................................... 624.9.7. On-Chip SRAM Clock Control Register Description .......................................................... 634.9.8. UTMI Clock Control Register Description .......................................................................... 634.9.9. Synchronous Serial Port Clock Control Register Description ............................................ 644.9.10. General-Purpose Media Interface Clock Control Register Description ........................... 654.9.11. SPDIF Clock Control Register Description ...................................................................... 664.9.12. EMI Clock Control Register Description .......................................................................... 674.9.13. IR Clock Control Register Description ............................................................................. 67

5. INTERRUPT COLLECTOR ...........................................................................................................695.1. Overview ......................................................................................................................................... 695.2. Nesting of Multi-Level IRQ Interrupts .............................................................................................. 725.3. FIQ Generation ............................................................................................................................... 735.4. Interrupt Sources ............................................................................................................................ 755.5. CPU Wait-for-Interrupt Mode .......................................................................................................... 775.6. Behavior During Reset .................................................................................................................... 775.7. Programmable Registers ................................................................................................................ 78

5.7.1. Interrupt Collector Interrupt Vector Address Register Description .................................... 785.7.2. Interrupt Collector Level Acknowledge Register Description ............................................ 785.7.3. Interrupt Collector Control Register Description ................................................................ 795.7.4. Interrupt Collector Status Register Description ................................................................. 815.7.5. Interrupt Collector Raw Interrupt Input Register 0 Description .......................................... 825.7.6. Interrupt Collector Raw Interrupt Input Register 1 Description .......................................... 835.7.7. Interrupt Collector Priority Register 0 Description ............................................................. 835.7.8. Interrupt Collector Priority Register 1 Description ............................................................. 855.7.9. Interrupt Collector Priority Register 2 Description ............................................................. 865.7.10. Interrupt Collector Priority Register 3 Description ........................................................... 885.7.11. Interrupt Collector Priority Register 4 Description ........................................................... 905.7.12. Interrupt Collector Priority Register 5 Description ........................................................... 915.7.13. Interrupt Collector Priority Register 6 Description ........................................................... 935.7.14. Interrupt Collector Priority Register 7 Description ........................................................... 955.7.15. Interrupt Collector Priority Register 8 Description ........................................................... 965.7.16. Interrupt Collector Priority Register 9 Description ........................................................... 985.7.17. Interrupt Collector Priority Register 10 Description ....................................................... 1005.7.18. Interrupt Collector Priority Register 11 Description ....................................................... 1015.7.19. Interrupt Collector Priority Register 12 Description ....................................................... 1035.7.20. Interrupt Collector Priority Register 13 Description ....................................................... 1055.7.21. Interrupt Collector Priority Register 14 Description ....................................................... 1065.7.22. Interrupt Collector Priority Register 15 Description ....................................................... 1085.7.23. Interrupt Collector Interrupt Vector Base Address Register Description ....................... 1105.7.24. Interrupt Collector Debug Register 0 Description .......................................................... 1105.7.25. Interrupt Collector Debug Read Register 0 Description ................................................ 1125.7.26. Interrupt Collector Debug Read Register 1 Description ................................................ 1125.7.27. Interrupt Collector Debug Flag Register Description ..................................................... 1135.7.28. Interrupt Collector Debug Read Request Register 0 Description .................................. 1135.7.29. Interrupt Collector Debug Read Request Register 1 Description .................................. 114

6. DEFAULT FIRST-LEVEL PAGE TABLE FOR ARM926 MMU ..................................................1156.1. Overview ....................................................................................................................................... 1156.2. 16-Megabyte Page-Mapped Virtual Memory (0xFFXXXXXX) ...................................................... 117

6.2.1. Default First-Level Page Table Entry 4095 ..................................................................... 1186.2.2. Default First-Level Page Table Entries 4094–4080 ........................................................ 1196.2.3. Default First-Level Page Table PIO Register Map Entry 2048 ........................................ 1206.2.4. Default First-Level Page Table Entry 0000 V==R SRAM Access ................................... 121

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7. DIGITAL CONTROL AND ON-CHIP RAM .................................................................................1237.1. Overview ....................................................................................................................................... 1237.2. SRAM Controls ............................................................................................................................. 124

7.2.1. SRAM BIST Control ........................................................................................................ 1267.3. ROM Controls ............................................................................................................................... 1277.4. Miscellaneous Controls ................................................................................................................. 127

7.4.1. Performance Monitoring .................................................................................................. 1277.4.2. High-Entropy PRN Seed ................................................................................................. 1277.4.3. Write-Once Register ........................................................................................................ 1287.4.4. Microseconds Counter .................................................................................................... 128

7.5. Behavior During Reset .................................................................................................................. 1287.6. Programmable Registers .............................................................................................................. 128

7.6.1. DIGCTL Control Register Description ............................................................................. 1287.6.2. DIGCTL Status Register Description .............................................................................. 1307.6.3. Free-Running HCLK Counter Register Description ......................................................... 1317.6.4. On-Chip RAM Control Register Description .................................................................... 1317.6.5. On-Chip RAM Repair Data 0 Register Description ......................................................... 1337.6.6. On-Chip RAM Repair Data 1 Register Description ......................................................... 1347.6.7. Software Write-Once Register Description ...................................................................... 1357.6.8. AHB Transfer Count Register Description ...................................................................... 1367.6.9. AHB Performance Metric for Stalled Bus Cycles Register Description ........................... 1367.6.10. Entropy Register Description ........................................................................................ 1377.6.11. Digital Control ROM Shield Read Enable Register Description .................................... 1387.6.12. Digital Control Microseconds Counter Register Description ......................................... 1387.6.13. Digital Control Debug Read Test Register Description ................................................. 1397.6.14. Digital Control Debug Register Description ................................................................... 1397.6.15. SRAM BIST Control and Status Register Description ................................................... 1407.6.16. SRAM BIST Repair Register 0 Description ................................................................... 1407.6.17. SRAM BIST Repair Register 1 Description ................................................................... 1417.6.18. SRAM Status Register 0 Description ............................................................................ 1427.6.19. SRAM Status Register 1 Description ............................................................................ 1427.6.20. SRAM Status Register 2 Description ............................................................................ 1437.6.21. SRAM Status Register 3 Description ............................................................................ 1437.6.22. SRAM Status Register 4 Description ............................................................................ 1447.6.23. SRAM Status Register 5 Description ............................................................................ 1447.6.24. SRAM Status Register 6 Description ............................................................................ 1457.6.25. SRAM Status Register 7 Description ............................................................................ 1457.6.26. SRAM Status Register 8 Description ............................................................................ 1467.6.27. SRAM Status Register 9 Description ............................................................................ 1467.6.28. SRAM Status Register 10 Description .......................................................................... 1477.6.29. SRAM Status Register 11 Description .......................................................................... 1477.6.30. SRAM Status Register 12 Description .......................................................................... 1487.6.31. SRAM Status Register 13 Description .......................................................................... 1497.6.32. Digital Control Scratch Register 0 Description .............................................................. 1507.6.33. Digital Control Scratch Register 1 Description .............................................................. 1507.6.34. Digital Control ARM Cache Register Description .......................................................... 1517.6.35. SigmaTel Copyright Identifier Register Description ....................................................... 1517.6.36. Digital Control Chip Revision Register Description ....................................................... 152

8. USB HIGH-SPEED ON-THE-GO (HOST/DEVICE) CONTROLLER ..........................................1558.1. Overview ....................................................................................................................................... 1558.2. USB Controller Core ..................................................................................................................... 1558.3. USB Programmed I/O (PIO) Target Interface ............................................................................... 1578.4. USB DMA Interface ....................................................................................................................... 1578.5. USB UTMI Interface ...................................................................................................................... 157

8.5.1. Exporting the PHY ........................................................................................................... 1578.5.2. Digital/Analog Loopback Test Mode ............................................................................... 157

8.6. USB Controller Flowcharts ............................................................................................................ 158

9. INTEGRATED USB 2.0 PHY ......................................................................................................1619.1. Overview ....................................................................................................................................... 1619.2. External Signals ............................................................................................................................ 1619.3. UTMI and Digital Circuits .............................................................................................................. 162

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6 Contents 5-36xx-D1-1.02-050306

9.3.1. UTMI Block ...................................................................................................................... 1629.3.2. Digital Transmitter Block ................................................................................................. 1629.3.3. Digital Receiver Block ..................................................................................................... 1629.3.4. Programmable Registers Block ....................................................................................... 162

9.4. Analog Transceiver ....................................................................................................................... 1639.4.1. Analog Receiver .............................................................................................................. 1639.4.2. Analog Transmitter .......................................................................................................... 164

9.5. Behavior During Reset .................................................................................................................. 1699.6. Programmable Registers .............................................................................................................. 169

9.6.1. USB PHY Power-Down Register Description .................................................................. 1699.6.2. USB PHY Transmitter Control Register Description ....................................................... 1709.6.3. USB PHY Receiver Control Register Description ........................................................... 1729.6.4. USB PHY General Control Register Description ............................................................. 1739.6.5. USB PHY Status Register Description ............................................................................ 1759.6.6. USB PHY Debug Register Description ........................................................................... 1769.6.7. UTMI Debug Status Register 0 Description .................................................................... 1779.6.8. UTMI Debug Status Register 1 Description .................................................................... 1789.6.9. UTMI Debug Status Register 2 Description .................................................................... 1799.6.10. UTMI Debug Status Register 3 Description .................................................................. 1809.6.11. UTMI Debug Status Register 4 Description .................................................................. 1819.6.12. UTMI Debug Status Register 5 Description .................................................................. 1819.6.13. UTMI Debug Status Register 6 Description .................................................................. 1829.6.14. UTMI Debug Status Register 7 Description .................................................................. 1839.6.15. UTMI Debug Status Register 8 Description .................................................................. 184

10. AHB-TO-APBH BRIDGE WITH DMA .........................................................................................18510.1. Overview ..................................................................................................................................... 18510.2. AHBH DMA ................................................................................................................................. 18610.3. Implementation Examples ........................................................................................................... 190

10.3.1. HWECC Example Command Chain .............................................................................. 19010.3.2. NAND Read Status Polling Example ............................................................................ 19110.3.3. APBH DMA and PIO Bus Implementation Example ..................................................... 193

10.4. Behavior During Reset ................................................................................................................ 19410.5. Programmable Registers ............................................................................................................ 195

10.5.1. AHB-to-APBH Bridge Control and Status Register 0 Description ................................. 19510.5.2. AHB-to-APBH Bridge Control and Status Register 1 Description ................................. 19610.5.3. AHB-to-APBH DMA Device Assignment Register Description ...................................... 19810.5.4. APBH DMA Channel 0 Current Command Address Register Description .................... 19910.5.5. APBH DMA Channel 0 Next Command Address Register Description ......................... 19910.5.6. APBH DMA Channel 0 Command Register Description ............................................... 20010.5.7. APBH DMA Channel 0 Buffer Address Register Description ........................................ 20210.5.8. APBH DMA Channel 0 Semaphore Register Description ............................................. 20210.5.9. AHB-to-APBH DMA Channel 0 Debug Register 1 Description ..................................... 20310.5.10. AHB-to-APBH DMA Channel 0 Debug Register 2 Description ................................... 20510.5.11. APBH DMA Channel 1 Current Command Address Register Description .................. 20610.5.12. APBH DMA Channel 1 Next Command Address Register Description ....................... 20710.5.13. APBH DMA Channel 1 Command Register Description ............................................. 20710.5.14. APBH DMA Channel 1 Buffer Address Register Description ...................................... 20910.5.15. APBH DMA Channel 1 Semaphore Register Description ........................................... 21010.5.16. AHB-to-APBH DMA Channel 1 Debug Register 1 Description ................................... 21110.5.17. AHB-to-APBH DMA Channel 1 Debug Register 2 Description ................................... 21210.5.18. APBH DMA Channel 2 Current Command Address Register Description .................. 21310.5.19. APBH DMA Channel 2 Next Command Address Register Description ....................... 21410.5.20. APBH DMA Channel 2 Command Register Description ............................................. 21410.5.21. APBH DMA Channel 2 Buffer Address Register Description ...................................... 21610.5.22. APBH DMA Channel 2 Semaphore Register Description ........................................... 21710.5.23. AHB-to-APBH DMA Channel 2 Debug Register 1 Description ................................... 21810.5.24. AHB-to-APBH DMA Channel 2 Debug Register 2 Description ................................... 21910.5.25. APBH DMA Channel 3 Current Command Address Register Description .................. 22010.5.26. APBH DMA Channel 3 Next Command Address Register Description ....................... 22110.5.27. APBH DMA Channel 3 Command Register Description ............................................. 22110.5.28. APBH DMA Channel 3 Buffer Address Register Description ...................................... 22310.5.29. APBH DMA Channel 3 Semaphore Register Description ........................................... 224

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10.5.30. AHB-to-APBH DMA Channel 3 Debug Register 1 Description ................................... 22510.5.31. AHB-to-APBH DMA Channel 3 Debug Register 2 Description ................................... 22610.5.32. APBH DMA Channel 4 Current Command Address Register Description .................. 22710.5.33. APBH DMA Channel 4 Next Command Address Register Description ....................... 22810.5.34. APBH DMA Channel 4 Command Register Description ............................................. 22810.5.35. APBH DMA Channel 4 Buffer Address Register Description ...................................... 23010.5.36. APBH DMA Channel 4 Semaphore Register Description ........................................... 23110.5.37. AHB-to-APBH DMA Channel 4 Debug Register 1 Description ................................... 23210.5.38. AHB-to-APBH DMA Channel 4 Debug Register 2 Description ................................... 23310.5.39. APBH DMA Channel 5 Current Command Address Register Description .................. 23410.5.40. APBH DMA Channel 5 Next Command Address Register Description ....................... 23510.5.41. APBH DMA Channel 5 Command Register Description ............................................. 23510.5.42. APBH DMA Channel 5 Buffer Address Register Description ...................................... 23710.5.43. APBH DMA Channel 5 Semaphore Register Description ........................................... 23810.5.44. AHB-to-APBH DMA Channel 5 Debug Register 1 Description ................................... 23910.5.45. AHB-to-APBH DMA Channel 5 Debug Register 2 Description ................................... 24010.5.46. APBH DMA Channel 6 Current Command Address Register Description .................. 24110.5.47. APBH DMA Channel 6 Next Command Address Register Description ....................... 24210.5.48. APBH DMA Channel 6 Command Register Description ............................................. 24210.5.49. APBH DMA Channel 6 Buffer Address Register Description ...................................... 24410.5.50. APBH DMA Channel 6 Semaphore Register Description ........................................... 24510.5.51. AHB-to-APBH DMA Channel 6 Debug Register 1 Description ................................... 24610.5.52. AHB-to-APBH DMA Channel 6 Debug Register 2 Description ................................... 24710.5.53. APBH DMA Channel 7 Current Command Address Register Description .................. 24810.5.54. APBH DMA Channel 7 Next Command Address Register Description ....................... 24910.5.55. APBH DMA Channel 7 Command Register Description ............................................. 24910.5.56. APBH DMA Channel 7 Buffer Address Register Description ...................................... 25110.5.57. APBH DMA Channel 7 Semaphore Register Description ........................................... 25210.5.58. AHB-to-APBH DMA Channel 7 Debug Register 1 Description ................................... 25310.5.59. AHB-to-APBH DMA Channel 7 Debug Register 2 Description ................................... 254

11. AHB-TO-APBX BRIDGE WITH DMA .........................................................................................25711.1. Overview ..................................................................................................................................... 25711.2. APBX DMA ................................................................................................................................. 25811.3. DMA Chain Example ................................................................................................................... 26111.4. Behavior During Reset ................................................................................................................ 26211.5. Programmable Registers ............................................................................................................ 263

11.5.1. AHB-to-APBX Bridge Control and Status Register 0 Description ................................. 26311.5.2. AHB-to-APBX Bridge Control and Status Register 1 Description ................................. 26411.5.3. AHB-to-APBX DMA Device Assignment Register Description ...................................... 26611.5.4. APBX DMA Channel 0 Current Command Address Register Description .................... 26711.5.5. APBX DMA Channel 0 Next Command Address Register Description ......................... 26711.5.6. APBX DMA Channel 0 Command Register Description ............................................... 26811.5.7. APBX DMA Channel 0 Buffer Address Register Description ........................................ 27011.5.8. APBX DMA Channel 0 Semaphore Register Description ............................................. 27011.5.9. AHB-to-APBX DMA Channel 0 Debug Register 1 Description ...................................... 27111.5.10. AHB-to-APBX DMA Channel 0 Debug Register 2 Description .................................... 27311.5.11. APBX DMA Channel 1 Current Command Address Register Description .................. 27411.5.12. APBX DMA Channel 1 Next Command Address Register Description ....................... 27511.5.13. APBX DMA Channel 1 Command Register Description ............................................. 27511.5.14. APBX DMA Channel 1 Buffer Address Register Description ...................................... 27711.5.15. APBX DMA Channel 1 Semaphore Register Description ........................................... 27711.5.16. AHB-to-APBX DMA Channel 1 Debug Register 1 Description .................................... 27811.5.17. AHB-to-APBX DMA Channel 1 Debug Register 2 Description .................................... 28011.5.18. APBX DMA Channel 2 Current Command Address Register Description .................. 28111.5.19. APBX DMA Channel 2 Next Command Address Register Description ....................... 28211.5.20. APBX DMA Channel 2 Command Register Description ............................................. 28211.5.21. APBX DMA Channel 2 Buffer Address Register Description ...................................... 28411.5.22. APBX DMA Channel 2 Semaphore Register Description ........................................... 28411.5.23. AHB-to-APBX DMA Channel 2 Debug Register 1 Description .................................... 28511.5.24. AHB-to-APBX DMA Channel 2 Debug Register 2 Description .................................... 28711.5.25. APBX DMA Channel 3 Current Command Address Register Description .................. 28811.5.26. APBX DMA Channel 3 Next Command Address Register Description ....................... 289

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8 Contents 5-36xx-D1-1.02-050306

11.5.27. APBX DMA Channel 3 Command Register Description ............................................. 28911.5.28. APBX DMA Channel 3 Buffer Address Register Description ...................................... 29111.5.29. APBX DMA Channel 3 Semaphore Register Description ........................................... 29111.5.30. AHB-to-APBX DMA Channel 3 Debug Register 1 Description .................................... 29211.5.31. AHB-to-APBX DMA Channel 3 Debug Register 2 Description .................................... 29411.5.32. APBX DMA Channel 4 Current Command Address Register Description .................. 29511.5.33. APBX DMA Channel 4 Next Command Address Register Description ....................... 29611.5.34. APBX DMA Channel 4 Command Register Description ............................................. 29611.5.35. APBX DMA Channel 4 Buffer Address Register Description ...................................... 29811.5.36. APBX DMA Channel 4 Semaphore Register Description ........................................... 29811.5.37. AHB-to-APBX DMA Channel 4 Debug Register 1 Description .................................... 29911.5.38. AHB-to-APBX DMA Channel 4 Debug Register 2 Description .................................... 30111.5.39. APBX DMA Channel 5 Current Command Address Register Description .................. 30211.5.40. APBX DMA Channel 5 Next Command Address Register Description ....................... 30311.5.41. APBX DMA Channel 5 Command Register Description ............................................. 30311.5.42. APBX DMA Channel 5 Buffer Address Register Description ...................................... 30511.5.43. APBX DMA Channel 5 Semaphore Register Description ........................................... 30511.5.44. AHB-to-APBX DMA Channel 5 Debug Register 1 Description .................................... 30611.5.45. AHB-to-APBX DMA Channel 5 Debug Register 2 Description .................................... 30811.5.46. APBX DMA Channel 6 Current Command Address Register Description .................. 30911.5.47. APBX DMA Channel 6 Next Command Address Register Description ....................... 31011.5.48. APBX DMA Channel 6 Command Register Description ............................................. 31011.5.49. APBX DMA Channel 6 Buffer Address Register Description ...................................... 31211.5.50. APBX DMA Channel 6 Semaphore Register Description ........................................... 31211.5.51. AHB-to-APBX DMA Channel 6 Debug Register 1 Description .................................... 31311.5.52. AHB-to-APBX DMA Channel 6 Debug Register 2 Description .................................... 31511.5.53. APBX DMA Channel 7 Current Command Address Register Description .................. 31611.5.54. APBX DMA Channel 7 Next Command Address Register Description ....................... 31711.5.55. APBX DMA Channel 7 Command Register Description ............................................. 31711.5.56. APBX DMA Channel 7 Buffer Address Register Description ...................................... 31911.5.57. APBX DMA Channel 7 Semaphore Register Description ........................................... 31911.5.58. AHB-to-APBX DMA Channel 7 Debug Register 1 Description .................................... 32011.5.59. AHB-to-APBX DMA Channel 7 Debug Register 2 Description .................................... 322

12. EXTERNAL MEMORY INTERFACE (EMI) .................................................................................32512.1. Overview ..................................................................................................................................... 32512.2. Dynamic Memory Controller ........................................................................................................ 326

12.2.1. DRAM Timing ................................................................................................................ 32712.3. Static Memory Controller (SMC) ................................................................................................. 32712.4. EMI Operation Example .............................................................................................................. 32812.5. Behavior During Reset ................................................................................................................ 32912.6. Programmable Registers ............................................................................................................ 329

12.6.1. EMI Control Register Description .................................................................................. 32912.6.2. EMI Status Register Description ................................................................................... 33012.6.3. EMI Debug Register Description ................................................................................... 33112.6.4. EMI DRAM Status Register Description ........................................................................ 33212.6.5. EMI DRAM Control Register Description ...................................................................... 33312.6.6. EMI DRAM Address Configuration Register Description .............................................. 33412.6.7. EMI DRAM Mode Configuration Register Description ................................................... 33512.6.8. EMI DRAM Timing Control Register 1 Description ........................................................ 33612.6.9. EMI DRAM Timing Control Register 2 Description ........................................................ 33812.6.10. EMI Static Memory Control Register Description ........................................................ 33812.6.11. EMI Static Memory Timing Control Register Description ............................................ 339

13. GENERAL-PURPOSE MEDIA INTERFACE (GPMI) ..................................................................34113.1. Overview ..................................................................................................................................... 34113.2. GPMI ATA Mode ......................................................................................................................... 341

13.2.1. Basic ATA Operation ..................................................................................................... 34113.2.2. GPMI ATA Clocking and Timing ................................................................................... 34113.2.3. GPMI ATA Pin Sharing ................................................................................................. 34213.2.4. ATA PIO Mode Timing .................................................................................................. 34313.2.5. ATA UDMA Mode .......................................................................................................... 34313.2.6. UDMA Timings .............................................................................................................. 344

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13.2.7. ATA Command/IRQ/Check Status Example ................................................................. 34413.3. GPMI NAND Mode ...................................................................................................................... 345

13.3.1. Multiple NAND Support ................................................................................................. 34513.3.2. GPMI NAND Timing and Clocking ................................................................................ 34513.3.3. Basic NAND Timing ...................................................................................................... 34613.3.4. NAND Command and Address Timing Example ........................................................... 34613.3.5. NAND Read Timing ....................................................................................................... 346


13.5.1. GPMI Control Register 0 Description ............................................................................ 34813.5.2. GPMI Compare Register Description ............................................................................ 35113.5.3. GPMI Control Register 1 Description ............................................................................ 35113.5.4. GPMI Timing Register 0 Description ............................................................................. 35313.5.5. GPMI Timing Register 1 Description ............................................................................. 35413.5.6. GPMI Timing Register 2 Description ............................................................................. 35513.5.7. GPMI DMA Data Transfer Register Description ............................................................ 35613.5.8. GPMI Status Register Description ................................................................................ 35613.5.9. GPMI Debug Information Register Description ............................................................. 357

14. HARDWARE ECC ACCELERATOR (HWECC) .........................................................................36114.1. Overview ..................................................................................................................................... 36114.2. Reed-Solomon ECC Accelerator ................................................................................................ 362

14.2.1. Reed-Solomon Encoding .............................................................................................. 36414.2.2. Reed-Solomon Decoding .............................................................................................. 36614.2.3. Reed-Solomon Decoding Using PIO Debug Mode ....................................................... 371


14.4.1. Hardware ECC Accelerator Control Register Description ............................................. 37314.4.2. Hardware ECC Accelerator Status Register Description .............................................. 37414.4.3. Hardware ECC Accelerator Debug Register 0 Description ........................................... 37514.4.4. Hardware ECC Accelerator Debug Register 1 Description ........................................... 37714.4.5. Hardware ECC Accelerator Debug Register 2 Description ........................................... 37814.4.6. Hardware ECC Accelerator Debug Register 3 Description ........................................... 37814.4.7. Hardware ECC Accelerator Debug Register 4 Description ........................................... 37914.4.8. Hardware ECC Accelerator Debug Register 5 Description ........................................... 38014.4.9. Hardware ECC Accelerator Debug Register 6 Description ........................................... 38014.4.10. Hardware ECC Accelerator DMA Read/Write Data Register Description ................... 381

15. SYNCHRONOUS SERIAL PORT (SSP) .....................................................................................38315.1. Overview ..................................................................................................................................... 38315.2. External Pins ............................................................................................................................... 38415.3. Bit Rate Generation .................................................................................................................... 38415.4. Frame Format for SPI, SSI, and Microwire ................................................................................. 38415.5. Motorola SPI Mode ..................................................................................................................... 385

15.5.1. SPI DMA Mode ............................................................................................................. 38515.5.2. Motorola SPI Frame Format .......................................................................................... 38515.5.3. Motorola SPI Format with Polarity=0, Phase=0 ............................................................ 38615.5.4. Motorola SPI Format with Polarity=0, Phase=1 ............................................................ 38715.5.5. Motorola SPI Format with Polarity=1, Phase=0 ............................................................ 38815.5.6. Motorola SPI Format with Polarity=1, Phase=1 ............................................................ 389

15.6. Texas Instruments Synchronous Serial Interface (SSI) Mode .................................................... 39015.7. National Semiconductor Microwire Mode .................................................................................... 39115.8. SD/SDIO/MMC Mode .................................................................................................................. 393

15.8.1. SD/MMC Command/Response Transfer ....................................................................... 39315.8.2. SD/MMC Data Block Transfer ....................................................................................... 39415.8.3. SDIO Interrupts ............................................................................................................. 39715.8.4. SD/MMC Mode Error Handling ..................................................................................... 39715.8.5. SD/MMC Clock Control ................................................................................................. 398

15.9. MS Mode ..................................................................................................................................... 39815.9.1. MS Mode I/O Pins ......................................................................................................... 39815.9.2. Basic MS Mode Protocol ............................................................................................... 39815.9.3. MS Mode High-Level Operation .................................................................................... 39915.9.4. MS Mode Four-State Bus Protocol ............................................................................... 399

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10 Contents 5-36xx-D1-1.02-050306

15.9.5. Wait for Card IRQ .......................................................................................................... 40115.9.6. Checking Card Status ................................................................................................... 40115.9.7. MS Mode Error Conditions ............................................................................................ 40215.9.8. MS Mode Details ........................................................................................................... 402

15.10. Behavior During Reset .............................................................................................................. 40215.11. Programmable Registers .......................................................................................................... 403

15.11.1. SSP Control Register 0 Description ............................................................................ 40315.11.2. SD/MMC and MS Command Register 0 Description .................................................. 40515.11.3. SD/MMC Command Register 1 Description ................................................................ 40715.11.4. SD/MMC and MS Compare Reference Register Description ...................................... 40715.11.5. SD/MMC and MS Compare Mask Register Description .............................................. 40815.11.6. SSP Timing Register Description ................................................................................ 40815.11.7. SSP Control Register 1 Description ............................................................................ 40915.11.8. SSP Data Register Description ................................................................................... 41215.11.9. SD/MMC Card Response Register 0 Description ....................................................... 41315.11.10. SD/MMC Card Response Register 1 Description ..................................................... 41315.11.11. SD/MMC Card Response Register 2 Description ..................................................... 41415.11.12. SD/MMC Card Response Register 3 Description ..................................................... 41415.11.13. SSP Status Register Description .............................................................................. 41415.11.14. SSP Debug Register Description .............................................................................. 416

16. LCD INTERFACE (LCDIF) ..........................................................................................................41916.1. Overview ..................................................................................................................................... 41916.2. LCD Interface Operation Example .............................................................................................. 420

16.2.1. Initialization Steps ......................................................................................................... 42116.2.2. Run Time Steps ............................................................................................................ 421

16.3. LCDIF Pin Timing Diagrams ....................................................................................................... 42216.4. Behavior During Reset ................................................................................................................ 42216.5. Programmable Registers ............................................................................................................ 423

16.5.1. LCD Interface Control and Status Register Description ................................................ 42316.5.2. LCD Interface Timing Register Description ................................................................... 42516.5.3. LCD Interface Data Register Description ...................................................................... 42516.5.4. LCD Interface Debug Register Description ................................................................... 426

17. PIN CONTROL AND GPIO .........................................................................................................42917.1. Overview ..................................................................................................................................... 42917.2. Pin Interface Multiplexing ............................................................................................................ 42917.3. Pin Drive Strength Selection ....................................................................................................... 43417.4. GPIO Interface ............................................................................................................................ 434

17.4.1. Output Operation ........................................................................................................... 43417.4.2. Input Operation ............................................................................................................. 43517.4.3. Input Interrupt Operation ............................................................................................... 436


17.6.1. PINCTRL Block Control Register Description ............................................................... 43917.6.2. PINCTRL Bank 0 Lower Pin Mux Select Register Description ...................................... 44017.6.3. PINCTRL Bank 0 Upper Pin Mux Select Register Description ...................................... 44117.6.4. PINCTRL Bank 0 Drive Strength Register Description ................................................. 44117.6.5. PINCTRL Bank 0 Data Output Register Description ..................................................... 44217.6.6. PINCTRL Bank 0 Data Input Register Description ........................................................ 44317.6.7. PINCTRL Bank 0 Output Enable Register Description ................................................. 44317.6.8. PINCTRL Bank 0 Interrupt Select Register Description ................................................ 44417.6.9. PINCTRL Bank 0 Interrupt Mask Register Description ................................................. 44517.6.10. PINCTRL Bank 0 Interrupt Level/Edge Register Description ...................................... 44617.6.11. PINCTRL Bank 0 Interrupt Polarity Register Description ............................................ 44617.6.12. PINCTRL Bank 0 Interrupt Status Register Description .............................................. 44717.6.13. PINCTRL Bank 1 Lower Pin Mux Select Register Description .................................... 44817.6.14. PINCTRL Bank 1 Upper Pin Mux Select Register Description .................................... 44817.6.15. PINCTRL Bank 1 Drive Strength Register Description ............................................... 44917.6.16. PINCTRL Bank 1 Data Output Register Description ................................................... 45017.6.17. PINCTRL Bank 1 Data Input Register Description ...................................................... 45117.6.18. PINCTRL Bank 1 Output Enable Register Description ............................................... 45217.6.19. PINCTRL Bank 1 Interrupt Select Register Description .............................................. 452

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17.6.20. PINCTRL Bank 1 Interrupt Mask Register Description ............................................... 45317.6.21. PINCTRL Bank 1 Interrupt Level/Edge Register Description ...................................... 45417.6.22. PINCTRL Bank 1 Interrupt Polarity Register Description ............................................ 45517.6.23. PINCTRL Bank 1 Interrupt Status Register Description .............................................. 45617.6.24. PINCTRL Bank 2 Lower Pin Mux Select Register Description .................................... 45617.6.25. PINCTRL Bank 2 Upper Pin Mux Select Register Description .................................... 45717.6.26. PINCTRL Bank 2 Drive Strength Register Description ............................................... 45817.6.27. PINCTRL Bank 2 Data Output Register Description ................................................... 45917.6.28. PINCTRL Bank 2 Data Input Register Description ...................................................... 45917.6.29. PINCTRL Bank 2 Output Enable Register Description ............................................... 46017.6.30. PINCTRL Bank 2 Interrupt Select Register Description .............................................. 46117.6.31. PINCTRL Bank 2 Interrupt Mask Register Description ............................................... 46117.6.32. PINCTRL Bank 2 Interrupt Level/Edge Register Description ...................................... 46217.6.33. PINCTRL Bank 2 Interrupt Polarity Register Description ............................................ 46317.6.34. PINCTRL Bank 2 Interrupt Status Register Description .............................................. 46317.6.35. PINCTRL Bank 3 Lower Pin Mux Select Register Description .................................... 46417.6.36. PINCTRL Bank 3 Upper Pin Mux Select Register Description .................................... 46517.6.37. PINCTRL Bank 3 Drive Strength Register Description ............................................... 46617.6.38. PINCTRL Bank 3 Data Output Register Description ................................................... 46717.6.39. PINCTRL Bank 3 Data Input Register Description ...................................................... 46817.6.40. PINCTRL Bank 3 Output Enable Register Description ............................................... 46917.6.41. PINCTRL Bank 3 Interrupt Select Register Description .............................................. 46917.6.42. PINCTRL Bank 3 Interrupt Mask Register Description ............................................... 47017.6.43. PINCTRL Bank 3 Interrupt Level/Edge Register Description ...................................... 47117.6.44. PINCTRL Bank 3 Interrupt Polarity Register Description ............................................ 47217.6.45. PINCTRL Bank 3 Interrupt Status Register Description .............................................. 473

18. TIMERS AND ROTARY DECODER ...........................................................................................47518.1. Overview ..................................................................................................................................... 47518.2. Timers ......................................................................................................................................... 476

18.2.1. Using External Signals as Inputs .................................................................................. 47718.2.2. Timer 3 and Duty Cycle Mode ....................................................................................... 47818.2.3. Testing Timer 3 Duty Cycle Modes ............................................................................... 479

18.3. Rotary Decoder ........................................................................................................................... 48018.3.1. Testing the Rotary Decoder .......................................................................................... 48218.3.2. Behavior During Reset .................................................................................................. 482

18.4. Programmable Registers ............................................................................................................ 48318.4.1. Rotary Decoder Control Register Description ............................................................... 48318.4.2. Rotary Decoder Up/Down Counter Register Description .............................................. 48418.4.3. Timer 0 Control and Status Register Description .......................................................... 48518.4.4. Timer 0 Count Register Description .............................................................................. 48718.4.5. Timer 1 Control and Status Register Description .......................................................... 48718.4.6. Timer 1 Count Register Description .............................................................................. 48918.4.7. Timer 2 Control and Status Register Description .......................................................... 49018.4.8. Timer 2 Count Register Description .............................................................................. 49118.4.9. Timer 3 Control and Status Register Description .......................................................... 49218.4.10. Timer 3 Count Register Description ............................................................................ 494

19. REAL-TIME CLOCK, ALARM, WATCHDOG, AND PERSISTENT BITS ..................................49719.1. Overview ..................................................................................................................................... 49719.2. Real-Time Clock ......................................................................................................................... 502

19.2.1. Behavior During Reset .................................................................................................. 50219.3. Millisecond Resolution Timing Facility ........................................................................................ 50219.4. Alarm Clock ................................................................................................................................. 50219.5. Watchdog Reset Register ........................................................................................................... 50319.6. Laser Fuse Bits ........................................................................................................................... 50319.7. Programmable Registers ............................................................................................................ 503

19.7.1. Real-Time Clock Control Register Description .............................................................. 50319.7.2. Real-Time Clock Status Register Description ............................................................... 50519.7.3. Real-Time Clock Milliseconds Counter Description ...................................................... 50619.7.4. Real-Time Clock Seconds Counter Register Description .............................................. 50719.7.5. Real-Time Clock Alarm Register Description ................................................................ 50819.7.6. Watchdog Timer Register Description .......................................................................... 508

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12 Contents 5-36xx-D1-1.02-050306

19.7.7. Persistent State Register 0 Description ........................................................................ 50919.7.8. Persistent State Register 1 Description ........................................................................ 51119.7.9. Persistent State (On-Chip RAM Configuration) Register 2 Description ........................ 51219.7.10. Persistent State (On-Chip RAM Configuration) Register 3 Description ...................... 51319.7.11. Real-Time Clock Debug Register Description ............................................................. 51319.7.12. RTC Unlock Register Description ............................................................................... 51419.7.13. HW Laser Fuse Register 0 Description ....................................................................... 51519.7.14. HW Laser Fuse Register 1 Description ....................................................................... 51619.7.15. HW Laser Fuse Register 2 Description ....................................................................... 51619.7.16. HW Laser Fuse Register 3 Description ....................................................................... 51719.7.17. HW Laser Fuse Register 4 Description ....................................................................... 51719.7.18. HW Laser Fuse Register 5 Description ....................................................................... 51819.7.19. HW Laser Fuse Register 6 Description ....................................................................... 51819.7.20. HW Laser Fuse Register 7 Description ....................................................................... 51919.7.21. HW Laser Fuse Register 8 Description ....................................................................... 52019.7.22. HW Laser Fuse Register 9 Description ....................................................................... 52019.7.23. HW Laser Fuse Register 10 Description ..................................................................... 52119.7.24. HW Laser Fuse Register 11 Description ..................................................................... 521

20. PULSE-WIDTH MODULATOR (PWM) CONTROLLER .............................................................52320.1. Overview ..................................................................................................................................... 52320.2. Operation .................................................................................................................................... 52320.3. Multi-Chip Attachment Mode ....................................................................................................... 52620.4. Behavior During Reset ................................................................................................................ 52720.5. Programmable Registers ............................................................................................................ 527

20.5.1. PWM Control and Status Register 0 Description .......................................................... 52720.5.2. PWM Channel 0 Active Register Description ................................................................ 52820.5.3. PWM Channel 0 Period Register Description ............................................................... 52920.5.4. PWM Channel 1 Active Register Description ................................................................ 53020.5.5. PWM Channel 1 Period Register Description ............................................................... 53120.5.6. PWM Channel 2 Active Register Description ................................................................ 53220.5.7. PWM Channel 2 Period Register Description ............................................................... 53320.5.8. PWM Channel 3 Active Register Description ................................................................ 53420.5.9. PWM Channel 3 Period Register Description ............................................................... 53520.5.10. PWM Channel 4 Active Register Description .............................................................. 53620.5.11. PWM Channel 4 Period Register Description ............................................................. 537

21. I2C INTERFACE ..........................................................................................................................53921.1. Overview ..................................................................................................................................... 53921.2. I2C Interface External Pins .......................................................................................................... 53921.3. I2C Interrupt Sources .................................................................................................................. 54021.4. I2C Bus Protocol ......................................................................................................................... 542

21.4.1. Simple Device Transactions .......................................................................................... 54321.4.2. Typical EEPROM Transactions ..................................................................................... 54421.4.3. Master Mode Protocol ................................................................................................... 54521.4.4. Slave Mode Protocol ..................................................................................................... 549

21.5. Programming Examples .............................................................................................................. 55221.5.1. Five Byte Master Write Using DMA ............................................................................... 55221.5.2. Reading 256 bytes from an EEPROM .......................................................................... 553


21.7.1. I2C Control Register 0 Description ................................................................................ 55521.7.2. I2C Timing Register 0 Description ................................................................................ 55821.7.3. I2C Timing Register 1 Description ................................................................................ 55821.7.4. I2C Timing Register 2 Description ................................................................................ 55921.7.5. I2C Control Register 1 Description ................................................................................ 56021.7.6. I2C Status Register Description .................................................................................... 56321.7.7. I2C Controller DMA Read and Write Data Register Description ................................... 56721.7.8. I2C Device Debug Register 0 Description ..................................................................... 56721.7.9. I2C Device Debug Register 1 Description ..................................................................... 569

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5-36xx-D1-1.02-050306 Contents 13

22. APPLICATION UART .................................................................................................................57122.1. Overview ..................................................................................................................................... 57122.2. Operation .................................................................................................................................... 572

22.2.1. Fractional Baud Rate Divider ........................................................................................ 57222.2.2. UART Character Frame ................................................................................................ 57322.2.3. DMA Operation ............................................................................................................. 57322.2.4. Data Transmission or Reception ................................................................................... 57322.2.5. Error Bits ....................................................................................................................... 57422.2.6. Overrun Bit .................................................................................................................... 57422.2.7. Disabling the FIFOs ...................................................................................................... 574


22.4.1. UART Receive DMA Control Register Description ........................................................ 57522.4.2. UART Transmit DMA Control Register Description ....................................................... 57622.4.3. UART Control Register Description .............................................................................. 57722.4.4. UART Line Control Register Description ....................................................................... 58022.4.5. UART Interrupt Register Description ............................................................................. 58122.4.6. UART Data Register Description .................................................................................. 58322.4.7. UART Status Register Description ................................................................................ 58422.4.8. UART Debug Register Description ............................................................................... 586

23. DEBUG UART .............................................................................................................................58923.1. Overview ..................................................................................................................................... 58923.2. Operation .................................................................................................................................... 590

23.2.1. Fractional Baud Rate Divider ........................................................................................ 59023.2.2. UART Character Frame ................................................................................................ 59123.2.3. Data Transmission or Reception ................................................................................... 59123.2.4. Error Bits ....................................................................................................................... 59223.2.5. Overrun Bit .................................................................................................................... 592

23.3. Disabling the FIFOs .................................................................................................................... 59223.4. Programmable Registers ............................................................................................................ 592

23.4.1. UART Data Register Description .................................................................................. 59223.4.2. UART Receive Status Register (Read) and Error Clear Register (Write) Description .. 59423.4.3. UART Flag Register Description ................................................................................... 59423.4.4. UART IrDA Low-Power Counter Register Description .................................................. 59523.4.5. UART Integer Baud Rate Divisor Register Description ................................................. 59623.4.6. UART Fractional Baud Rate Divisor Register Description ............................................ 59723.4.7. UART Line Control Register, High Byte Description ..................................................... 59723.4.8. UART Control Register Description .............................................................................. 59923.4.9. UART Interrupt FIFO Level Select Register Description ............................................... 60023.4.10. UART Interrupt Mask Set/Clear Register Description ................................................. 60123.4.11. UART Raw Interrupt Status Register Description ....................................................... 60223.4.12. UART Masked Interrupt Status Register Description .................................................. 60323.4.13. UART Interrupt Clear Register Description ................................................................. 60423.4.14. UART DMA Control Register Description .................................................................... 606

24. IRDA CONTROLLER ..................................................................................................................60724.1. Overview ..................................................................................................................................... 60724.2. Operation .................................................................................................................................... 608

24.2.1. DMA Operation ............................................................................................................. 60824.2.2. IR Transmit Processing ................................................................................................. 60824.2.3. IR Receive Processing .................................................................................................. 60924.2.4. IR Serial Interface ......................................................................................................... 60924.2.5. IR Clock Configuration .................................................................................................. 610


24.4.1. IR Control Register Description ..................................................................................... 61124.4.2. IR Transmit DMA Control Register Description ............................................................. 61224.4.3. IR Receive DMA Register Description .......................................................................... 61324.4.4. IR Debug Control Register Description ......................................................................... 61424.4.5. IR Interrupt Register Description ................................................................................... 61524.4.6. IR RX Data Register Description ................................................................................... 61724.4.7. IR Status Register Description ...................................................................................... 618

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14 Contents 5-36xx-D1-1.02-050306

24.4.8. IR Transceiver Control Register Description ................................................................. 61924.4.9. IR Serial Interface Read Data Register Description ...................................................... 62024.4.10. IR Debug Register Description .................................................................................... 620

25. AUDIOIN/ADC .............................................................................................................................62325.1. Overview ..................................................................................................................................... 62325.2. Operation .................................................................................................................................... 625

25.2.1. AUDIOIN DMA .............................................................................................................. 62625.3. ADC Sample Rate Converter and Internal Operation ................................................................. 62725.4. Microphone ................................................................................................................................. 63025.5. Behavior During Reset ................................................................................................................ 63125.6. Programmable Registers ............................................................................................................ 631

25.6.1. AUDIOIN Control Register Description ......................................................................... 63125.6.2. AUDIOIN Status Register Description ........................................................................... 63425.6.3. AUDIOIN Sample Rate Register Description ................................................................ 63425.6.4. AUDIOIN Volume Register Description ......................................................................... 63625.6.5. AUDIOIN Debug Register Description .......................................................................... 63825.6.6. ADC Mux Volume and Select Control Register Description .......................................... 64025.6.7. Microphone and Line Control Register Description ....................................................... 64125.6.8. Analog Clock Control Register Description ................................................................... 64325.6.9. AUDIOIN Read Data Register Description .................................................................... 644

26. AUDIOOUT/DAC .........................................................................................................................64726.1. Overview ..................................................................................................................................... 64726.2. Operation .................................................................................................................................... 648

26.2.1. AUDIOOUT DMA .......................................................................................................... 64926.3. DAC Sample Rate Converter and Internal Operation ................................................................. 65026.4. Reference Control Settings ..............

product data sheet stmp36xx - rockbox · 2 5-36xx-d1-1.02-050306 stmp36xx official product...

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