procurement specification for intel printed circuit...

FOR REFERENCE USE ONLY UNLESS COVER SHEET IS STAMPED 'CONTROLLED'OR 'CONTROLLED COPY' IS CONTAINED IN FOOTERREFERENCE COPY VALID ONLY ON DATE PRINTED

__________________________________________________________________________________

DESCRIPTION of CHANGES: See last page of spec.

Title: Intel Printed Circuit Board Procurement Specification

APPROVALSOwner: David W Boggs ISSUE DATE: April-2010Materials: Pan Michael REVIEW CYCLE: 1 YearQuality/Reliability: Eric Shi EXPIRATION DATE: April- 2011GMPO: Wang Yip Kong GROUP RESP: GMPO

DOCUMENT NUMBER: A84501 Rev 10 Sheet 1 of 40INTEL CORPORATION CONFIDENTIAL INFORMATION -- DO NOT REPRODUCE


__________________________________________________________________________________

1.0 PURPOSE/SCOPE:

1.1 Purpose: To define the functional, quality, and material (i.e. visual, dimensional, physical) requirements and specifications of Intel Printed Circuit Boards. To provide manufacturing with Printed Circuit Boards that meets or exceeds applicable standards and Intel manufacturing criteria. To define Intel lot acceptance criteria and Intel quality levels.

1.2 Scope: This document specifies the finished product acceptance criteria for printed circuit boards designed to meet Intel requirements. This specification applies to rigid multi-layer printed boards consisting of two or more copper conductive patterns separated by an insulating epoxy glass laminate. This specification does not apply to flexible circuits, ceramic substrates, or other exotic materials.

This specification is for the procurement of printed circuit boards from the printed circuit board manufacturer and does not apply to printed board assemblies. PTP and Intel consign projects must follow this specification unless otherwise approved by Intel.

Any requirements not included in this specification shall meet the conditions specified for Performance Class 2, as defined by the IPC Association Connecting Electronics Industries.

1.3 This document supersedes all earlier revisions. This document replaces procurement specification 454979.

2.0 INDEX:

CATEGORY PARA # Purpose/Scope 1.0Index 2.0Reference Documents 3.0Definitions 4.0Material Requirements 5.0

Visual 5.1Dimensional 5.2Functional 5.3

Quality Assurance Requirements 6.0Special Requirements 7.0Packaging/Labeling/Handling Requirements 8.0Appendices 9.0

3.0 REFERENCE DOCUMENTS:The current version of the following documents of the issue in effect on the date of the request for purchase, forms a part of this specification to the extent specified. In the event of conflict between the reference documentation, the order of precedence shall be defined by the documents below:

3.1 Purchase order/receiver

3.2 Applicable Printed Circuit Board Fabrication CAD data

3.3 Applicable Printed Circuit Board Fabrication Drawing / Photo Tools

3.4 Current Temporary Engineering Instructions (TEI)

3.5 Current revision of A84501 GMPO Procurement Specification for Intel Printed Circuit Boards

3.6 IPC Standards:



__________________________________________________________________________________

IPC-6011 Generic performance specification for PWB’sIPC-6012 Qualification and Performance Specification for Rigid Printed BoardsIPC-6016 Qualification and Performance Specification for High Density Interconnect (HDI) layers or boardsIPC/JPCA-4104 Specification for High Density Interconnect (HDI) and Microvia MaterialsIPC-T-50 Terms & definitions for interconnecting and packaging electronic circuitsIPC-A-600 Acceptability of Printed boardsIPC-7711/7721 Repair & Modification of Printed Boards & Electronic AssembliesIPC-D-300 Printed board dimensions and tolerancesIPC-TM-650 PWB test methods manualIPC-4101 Specification for base materials for rigid and multi-layer PWB’sIPC-SM-840 Qualification & Performance of Permanent Polymer Coating (Solder mask) For PWB’sIPC-MF-150 Metal foil for PWB’s J-STD-003 Solderability tests for PWB’s

3.7 American National Standards Institute Standards:ASME Y14.5 Dimensioning and Tolerancing for Engineering DrawingsANSI/ASQ Z1.4 Sampling Procedures and Tables for Inspection by Attributes

3.8 Underwriters Laboratory Standard:UL 796 Standard for Safety, Printed Wiring BoardsUL 94 Standard for Safety, Tests for Flammability of Plastic Materials

3.9 Intel Specifications:

405-3109 Intel Environmental and Lead-Free Solder System Requirements for Purchased Electronic Components (including Restriction on Hazardous Substances, RoHS)

BS-MTN-0001 Intel Environmental Product Content Specification

4.0 DEFINITIONS:

Terms and definitions used in this document are as specified in IPC-T-50. The following Intel terms are provided for clarification.

4.1 Annular Ring: remaining metal land surrounding a plated-through hole.

4.2 Barcode Block: Solid rectangles of (typically) legend ink applied to the board for adding laser etched barcodes during assembly.

4.3 Blind via: Plated hole open to one side of the board and terminating at an internal board layer.

4.4 BGA: Ball Grid Array

4.5 Breakaway: Synonymous with “outrigger”. A (typically) non-functional laminate area supporting two or more PCBs within the multipack that is discarded after assembly de-panelization. Also the non-functional supporting area of a uni-pack.

4.6 Capture Pad: Outer layer microvia pad.

4.7 Certificate of Conformance (C of C): A document that lists key information and data about a specific shipment and certifies that the material conforms to this procurement specification. Parameters outlined in the example of the C of C in Appendix A of this specification are to be used as the indicators for lot acceptance. NOTE: The terms Certificate of Analysis (C of A) and Certificate of Compliance are synonymous.

4.8 Critical to Function (CTF) parameter: A PCB characteristic defined by Intel as critical to assembly and/or function of the PCB. A Frozen CTF parameter is defined as a characteristic that meets the capability and stability requirements during



__________________________________________________________________________________

development and must meet all Lot Acceptance criteria shown on the C of C on all subsequent lots. Non-frozen CTF parameters must have an improvement plan to meet capability and stability requirements approved by Intel.

4.9 CSP: Chip Scale Package: BGA less than 1.0 mm pitch.

4.10 Delamination: separation between any of the layers of the base material and/or between the base material and copper.

4.11 DPM = Defects per Million

4.12 Diameter True Position (DTP): Geometric tolerance notation describing the allowable tolerance zone (expressed as circular with given diameter) for the location of features from datum. Reference ASME Y14.5 Geometric Dimensioning and Tolerancing.

4.13 Element symbols:Cu: Copper Ni: Nickel Au: Gold Ag: Silver Sn: Tin Pb: Lead

4.14 Encroached via: Solder mask partially covers the PTH/via metal pad up to the plated hole, but solder mask is not allowed in the hole. Design is typically nominal finished hole size plus six mils. Function is to minimize exposed metal and maximize solder mask web between adjacent vias or solder lands while leaving via barrel open for optimum processing and reliability.

4.15 Fiducial: A solid metal feature on the external layers of a board used for the alignment of surface mount assembly equipment.

4.16 Functional Land: A land required for circuit interconnection or termination.

4.17 Gold Fingers: Strips of conductive material that are a part of the external etch layers of a board and form a male edge-connector. The strips are normally plated with gold, but sometimes plated with other conductive material.

4.18 LPI: Liquid Photo Imagible Solder Mask

4.19 Metal Defined Pad or Land: The entire SMT/BGA/CSP land is available as a solderable surface (including edges of pads).

4.20 Microvia: Layer to layer interconnect that is less than 10 mils in diameter produced by laser drilling. Other methods of microvia formation are excluded from this specification for clarity. Laser via ablation is the current approved process for Intel and is the method specified within this document.

4.21 Microvia in pad (mVIP or μVIP): microvia placed within the solder land or pad of a SMT/BGA/CSP device.

4.22 Multipack: A standard Intel panel used as a carrier for either a smaller board or an array of multiple boards.

4.23 Non-Functional Land: A PTH land on an internal layer without a connecting trace or conductor.

4.24 Outrigger: Synonymous with “breakaway”. A (typically) non-functional laminate area supporting two or more PCBs within the multipack that is discarded after assembly de-panelization. Also the non-functional supporting area of a uni-pack.

4.25 PTP: Pass Through Pricing, Intel negotiated pricing with PCB supplier and then extend the pricing to the subcontractors who procure PCBs for integration into Intel products.

4.26 PWB: Printed Wire Board, which is synonymous with Printed Circuit Board (PCB).

4.27 Resin Coated Foil (RCF) also know as Resin Coated Copper (RCC): Thin layer of non-reinforced dielectric coated with copper typically used for redistribution layers of microvia printed circuit boards.



__________________________________________________________________________________

4.28 Selective Gold Plating: Any gold plated area that must be manufactured without the aid of plating bars. These gold plated features are typically located in the center regions of Intel boards, preventing standard tab plating processes.

4.29 Solder Mask Defined Pad or Land (SMDP): Solder mask defines the amount of solderable surface on a SMT/BGA/CSP land.

4.30 Solder Mask Foreign Material: Material not present by design either embedded in or attached to the surface in the solder mask.

4.31 Solder Mask Residue: Excess solder mask material typically from a capping or touch up repair operation.

4.32 Solder Mask Scratches: Disruptions in the surface of the solder mask and surrounding area due to mechanical damage.

4.33 Solder Mask Voids: Pinholes, scratches, or bubbles that cause an interruption in the solder mask coverage.

4.34 Target Pad: Inner layer microvia pad.

4.35 Test Point: There are two types of test points: plated through holes (PTH) and surface pads. The PTH is the most common type. It is an uncapped via that also serves as a test point. A surface test point is a conductive pad placed directly on the PCB surface.

4.36 True Position: The theoretically exact location of a feature established by basic dimensions. [Reference ASME Y14.5]

4.37 Uni-pack: A single board having material separated by tab routing or V-grooves that later will be removed from the assembly. The extra material is designed as an assembly aid.

4.38 Vendor Design Change Request (VDCR): A closed loop system for tracking any design changes requested by the supplier. All changes must be reviewed and signed off by Intel before start of fabrication

4.39 Via Cap: Intel defines as a post-solder mask via tenting process with no via barrel fill requirement.

4.40 Via Plug: Intel defines as a pre or post- solder mask via fill and tent process with a specified via barrel fill requirement.


http://dfx.intel.com/dfx/app/entry.asp?ref=via

http://dfx.intel.com/dfx/app/entry.asp?ref=PTH


__________________________________________________________________________________

5.0 MATERIAL REQUIREMENTS:

5.1 VISUAL INSPECTION:

5.1.1 Visual Inspection Method:

5.1.1.1 Visual inspection criteria per IPC-A-600 unless otherwise specified within this document.

5.1.1.2 The breakaway section of the multipack is a non-functional area however it may contain some Intel designed features. Defects found in this area, which are not associated with the Intel designed features, are considered to be acceptable if defect does not impact assembly (i.e. large solder mask voids over metal). In addition, the supplier may add features, such as coupons, provided there is no impact to Intel designated features or edge profile quality. Any changes to the breakaway require Intel notification.

5.1.2 Solder Mask

5.1.2.1 The areas of the board defined by CAD design shall be completely covered with green solder mask material that meets the requirements of IPC-SM-840, class 2.

5.1.2.2 The clearances surrounding conductive features may be modified if necessary, provided that adjacent conductors are completely covered and other requirements of this section are satisfied. Specific requirements for fiducials are covered in section 7. Refer to section 5.2 for maximum allowable solder mask clearance pad compensation.

5.1.2.3 Large plated-through holes (.156" and larger) may contain minor solder mask residue provided it does not reduce dimensions below the minimum hole size specification.

5.1.2.4 No more than one application layer of solder mask shall be permitted over the bare laminate or traces with the exception of any small areas of touch up (see section 7) and via cap overlap areas.

5.1.2.5 With the exception of via capping/plugging in accordance with other requirements of this section there shall be no solder mask residue in the holes.

5.1.2.6 Using the primary solder mask to flood vias is NOT permitted. Via cap and via plug operations require a separate operation.

5.1.2.7 VOIDS: Minor scratches, pinholes or voids in the solder mask which occur before surface finish application and are thus coated, shall be acceptable provided there is no exposed adjacent metal within 0.020" of the defect. Minor scratches, pinholes or voids in the solder mask which occur after surface finish application resulting in exposed copper will be acceptable provided:

5.1.2.7.1 The exposed copper area is no larger than 0.125" in any direction.

5.1.2.7.2 There is no exposed metal adjacent to the void within 0.020" or less.

5.1.2.8 TOUCH UP: Solder mask touchup is allowed per section 7 and to a maximum of 5% of the surface area per board side. Thickness of the touchup must not exceed 0.006” from the board surface, unless the void is closer than 0.250” from a sub 0.050” pitch SMT land or BGA pad. Under this condition, touchup thickness must not exceed 0.003” thickness.

5.1.3 Electrolytic Gold Contacts

5.1.3.1 Scratches, pits and dents are acceptable provided there is no exposed nickel and/or copper. Refer to IPC-600 and 6012 for additional gold finger requirements.



__________________________________________________________________________________

5.1.3.2 There shall be no solder residue allowed on the contact area of the gold fingers.

5.1.3.3 Cosmetic stains affecting more than 20% of the area of any single gold finger contact are not allowed without written permission from Intel (see example in Figure 5-6).

5.1.4 Plating Thieves

5.1.4.1 Unless otherwise stated on the fabrication drawing, plating thieves may be added to external layers of the board, and to the multi-pack breakaway section to achieve more uniform electrolytic plating.

5.1.4.2 For embedded microstrip designs, no external layer thieving is allowed within 1” of internal impedance traces on adjacent layers.

5.1.4.3 Metallization added shall be square pads, sized 0.050" to 0.080" and placed on 0.100" centers.

5.1.4.4 Layer tabs, barcode blocks and Intel logo must not be obstructed.

5.1.4.5 Added metal must be covered with solder mask.

5.1.4.6 Minimum spacing to traces/pads shall be 0.050”.

5.1.5 Legend

5.1.5.1 Legend shall be legible unless otherwise stated on the fab drawing.

5.1.5.2 Legend shall be on the primary and/or secondary side of the board, over the solder mask.

5.1.5.3 Legend ink on any SMT/BGA/CSP lands will be treated the same as solder mask (see sections 5.1 and 5.2)

5.1.5.4 If the legend design overlaps the component holes, the vendor is permitted to adjust the artwork to prevent ink from covering them. Ink will be permitted in the smaller via holes that are not used for lead attachment.

5.1.5.5 All legend shall be white epoxy ink and shall be non-flammable, non conductive, and non-hydroscopic.

5.1.6 Board Edges

5.1.6.1 There shall be no fraying of the board edges. All edges must be smooth and free of continuous burrs.

5.1.7 Via Capping for gold surface finishing

5.1.7.1 When via capping is required, a CAD file with the title "Via Cap" will be provided. This file will identify which vias to cap.

5.1.7.2 Unless otherwise specified, the following process will be followed for via capping:

5.1.7.2.1 The via capping process must occur after the final surface finish.

5.1.7.2.2 Vias will be capped from the secondary side (solder side) only.

5.1.7.2.3 The vias will be capped with an epoxy or solvent type solder mask and completely cured. Typical via cap depth is 15% – 25% of the thickness of the board. The maximum allowed via cap depth is 80%.



__________________________________________________________________________________

5.1.7.2.4 There will be no smearing of the via cap material onto any adjacent SMT pads or test points and via capping must completely cover the pad, ensuring no exposed metal.

5.1.7.2.5 100% of the vias must be capped. Up to 5% of the vias are permitted to have broken caps that do not expose surface metal.

5.1.8 Via Plugging

5.1.8.1 Via plugging is required when a) an Immersion Silver or OSP surface finish is specified and b) a CAD file with the title “Via Cap” is provided, or when otherwise specified. The hole locations provided in the “Via Cap” file indicate the holes which require via plugging, in the case of the Immersion Silver or OSP finish.

5.1.8.2 Via plugging for Immersion Silver or OSP boards requires a separate operation from the primary soldermask coating, prior to the Immersion Silver or OSP application.

5.1.8.3 Boards with via plugging prior to a horizontal conveyorized Immersion Silver or OSP process must be processed with the via plug side facing up.

5.1.8.4 Via plugs must not protrude above the surface of the via pad.

5.1.8.5 A high-solids material is recommended for the via plugging to comply with requirements of Section 5.2.20

5.1.9 Microvia

5.1.9.1 Resin residue at the base of the microvia is not allowed (see figure 5-9).

5.1.9.2 Final surface finish plating within the microvia is preferred, but it is acceptable to have incomplete coverage inside the microvia.

5.1.9.3 Foreign material contamination inside the microvia is not allowed.

5.1.9.4 Microvia hole-to-pad breakout is NOT allowed on external or internal laser lands or pads.

5.2 DIMENSIONAL INSPECTION / MATERIAL CHARACTERISTICS:All dimensions and tolerances specified herein are applicable to the finished board only. A summary of dimensional information is given in Table I. The symbols listed refer to physical descriptions shown in Figure 5-1.

TABLE IDIMENSIONS AND TOLERANCES


CF

B

GE

A

K


__________________________________________________________________________________

Symbol(FIG. 5-1)

Characteristic Para.

A

Conductors/Lands - Feature Size Tolerance - Feature Location - Copper Thickness, Inner Layer - Copper Thickness, Outer Layer

5.2.25.2.55.2.65.2.7

B Nominal Trace Width General Reductions 5.2.2 Defect Reductions 5.2.4

C Space Reductions from Defects 5.2.11D Min. Plated Hole to Conductor or

Plane Spacing5.2.8

E Min. Dielectric Spacing 5.2.10F Overall Board Thickness 5.2.13.1G Hole Location Tolerance 5.2.12.1H Plated Hole Dia. Tolerance 5.2.12.2I Non-Plated Dia. Tolerance. 5.2.12.2K Annular Ring (Min.) 5.2.12.3

Bow and Twist 5.2.13.2Connector / Edge Bevel 5.2.13.3PTH Copper Thickness 5.2.15.3Final Surface Finish 5.2.16Electrical Gold Contacts 5.2.17Solder Mask 5.2.18Legend 5.2.19Board Profile 5.2.13.4

FIGURE 5-1: Circuit Board Basic Dimensions


D

HI


__________________________________________________________________________________

5.2.1 Requirements

5.2.1.1 The supplier shall have and supply documented measurement procedures and proven measurement capability for the metrology used to measure and/or monitor all parameters defined in this specification and appropriate printed circuit board fabrication drawings.

5.2.1.2 All of the finished, unpopulated, printed circuit boards shall meet the dimensional requirements as specified in this document and mechanical drawing.

5.2.2 Conductor Feature Size Tolerance: Unless otherwise stated, conductor size tolerances and measurement locations shall be as specified in Table II. If not defined in Table II or elsewhere, the default feature size tolerance is +/-20% for features < 25 mils, and +/-5.0 mils for features > 25 mils, with respect to the design data provided by Intel.

TABLE IICONDUCTOR SIZE TOLERANCE

Size Shape Conductor Type

Trace Width or Pad Pitch

Size Tolerance(From Nominal CAD

Dimension)

Measurement

Location>0.005” All Trace All Smaller of +/-20% or +/-5 mils Base

<0.005” All Trace All +/-0.001” Base

All All Gold fingers All +/-0.002” Base

All All SMT Pad No Pitch Smaller of +/-20% or +/-5 mils Base

All All SMT Pad >0.050” Smaller of +/-20% or +/-5 mils Base

All Rectangular SMT Pad < 0.050” +0.002” / -0.0005” Base

> 0.012” Round or non-rectangular SMT Pad < 0.050” +/- 0.0023” Base

< 0.012” Round or non-rectangular SMT Pad < 0.050” +0.0005” / -0.002” Base

Measurement locations of base refer to the interface of the copper to the laminate.

5.2.3 Plated-through hole pads smaller of +/- 20% or +/- 5 mil and internal plane clearances (anti-pads) diameter must be +/- 2 mil of their nominal CAD dimension

5.2.4 Trace Width Reductions from Defects: Any combination of edge roughness, nicks, pinholes and scratches exposing the base material shall not reduce the conductor width by more than 30% of the CAD trace width. There shall be no occurrence spanning a distance greater than the trace width. Minimum trace widths will be measured at the base laminate/foil interface.

5.2.5 Conductor Feature Location Tolerance (Outer Layers): Lands, traces, pads and other conductive features shall be located within 8 mil diameter true position (DTP) tolerance (equal to 4mil radial true position) to the design grid. Datum’s A & B on the fabrication drawing will serve as reference points for validation measurements.

5.2.6 The default, nominal, internal copper weight is 1 oz/ft2, unless otherwise specified. The minimum internal copper thickness shall be in accordance with IPC, class 2. The following values are shown for reference only.



__________________________________________________________________________________

COPPER WEIGHT NOMINAL THICKNESS PROCESSED MINIMUM

1/2 oz/ft2 .0007" .0005”

1 oz/ft2 .00135" .001”

2 oz/ft2 .0028" .0022”

5.2.7 The default, nominal, external copper weight prior to plating is 1/2 oz/ft2, unless otherwise specified. The minimum external conductor thickness after plating is 0.001”. The electrodeposited copper shall be no less than 99.5% pure, as tested by IPC-TM-650, method 2.3.15.

5.2.8 Plated through hole to conductive feature [Fig. 5-1, D] minimum spacing shall be >= 0.004”.

5.2.9 Non-plated through hole to conductive feature minimum spacing shall be >= 0.004”.

5.2.10 Dielectric Spacing [Fig. 5-1, E]: Unless otherwise specified on the drawing, the minimum dielectric spacing shall be 0.002” distance between copper-copper peaks.

5.2.11 Space Reductions from Defects: Any isolated defect shall not reduce the space by more than 30% of the CAD dimension. Defect shall not be longer than the width of the nominal space.

5.2.12 Holes and Slots

5.2.12.1 Hole Location Tolerance [Fig. 5-1, G]:

5.2.12.1.1 Plated-Through Holes shall be located within 8 mil (0.2mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing.

5.2.12.1.2 Non plated holes <0.200” shall be located within 8 mil (0.2mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing.

5.2.12.1.3 Non plated holes >0.200” shall be located within 12 mil (0.3mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing.

5.2.12.1.4 Non plated slots <0.100” in narrow axis by <0.200” in long axis shall be located within 8 mil (0.2mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing

5.2.12.2 Hole Diameter Tolerance [Fig. 5-1, H & I]: The required plated and non-plated hole diameter tolerances will be specified on the fabrication drawing.

5.2.12.3 Annular Ring and Breakout [Fig. 5-1, K]:

5.2.12.3.1 Inner Layer and Outer Layer Annular Ring: There shall be no more than 90 degrees breakout on inner layer and outer layer pads on any plated through hole.

5.2.12.3.2 Breakout in the region of the trace / pad junction shall not reduce the trace width by more than 20%. (See Figure 5-2.)



__________________________________________________________________________________

5.2.13 Mechanical Features

5.2.13.1 Overall Board Thickness (Fig. 5-1, F): Unless otherwise specified on the PCB drawing, the board supplier shall target for a nominal thickness of 0.062”, with a tolerance range of +0.008”/ -0.005” provided to allow for standard process and material variations. For boards with a nominal thickness >0.062”, the PCB supplier shall use +/-10% thickness tolerance unless otherwise specified. For boards with a nominal thickness <0.062”, the PCB supplier shall use +/-10% or +/-4mils, whichever is greater. Unless defined on the PCB drawing, the thickness shall be defined as the total thickness including external plating and solder mask, measured over soldermask covered metal.

5.2.13.2 Bow and Twist: Bow and twist shall be no greater than 0.0075”/inch (0.75%) for surface mount boards and 0.015” / inch (1.5%) for all others, or as specified on the drawing. This to be determined by IPC-TM-650, Test Method 2.4.22.

5.2.13.3 Connector Edge Bevel: bevel per mechanical drawing.

5.2.13.4 Board Profile: Unless otherwise specified, board profile dimensions shall be per Table III.

5.2.13.5 Mini-PCI Gold Finger uNotch: The preferred method of creating the micro-notch on Mini-PCI connectors is by using a multi-hit drilling. Sampling of the last drilled hole size should be done with a pin gauge. Routing is not recommended.


Maximum drill Breakout

90 degrees of drilled hole circumference

Addition of tear dropping allowed

Maximum trace reduction20% of the nominal trace (before

plating)

FIGURE 5-2: Annular Ring and Drill Breakout Allowance

+/- 0.006”


__________________________________________________________________________________

TABLE IIIBOARD PROFILE

Figure 5-3: Gold Finger Slot Width and Center-Center Tolerance


Dimension Tolerance

Inside corner 0.065" radius maximumOutside corner

(Preferred rounded)0.020” - .065" radius

Center of Hole to Edge +/- 0.005”

Edge to Edge +/- 0.010”Gold finger slot width

(see figures 5.3) +/- 0.002”

Edge slot to gold finger(center to center; see figures 5-3) +/- 0.006”

Angle +/- 5 deg.

The table refers to 0.062” nominal and below boards, thicker boards may require wider tolerances

+/- 0.002”


__________________________________________________________________________________

5.2.14 Base Laminate and Copper Foil

5.2.14.1 Boards shall be fabricated from copper clad laminate per, IPC 4101. Copper shall be at least 99.5% pure.

5.2.14.2 Boards shall be fabricated from E-glass woven, epoxy flame resistant FR-4. Unless otherwise specified on the fabrication drawing, material Tg shall be chosen per the following table for boards using a pb-free process, not halogen free.

Nominal thickness Tg requirement

<0.070” Between 130° C -145° C as measured by DSC

>= 0.070” and < 0.093” Between 145° C -160° C as measured by DSC

>= 0.093” and < 0.150” Between 160° C -180° C as measured by DSC



__________________________________________________________________________________

5.2.15 Plated Holes

5.2.15.1 Plating Voids: There shall be no more than one void per board with the void being no larger than 5% of the total board thickness. There shall be no voids at the interface of an internal conductive layer and plated through hole wall. There shall be no circumferential plating voids. Sampling for plated through hole voids shall be per IPC-6012, Section 3.6.2.2.

5.2.15.2 Plating folds, nodules, cracks, separation, wicking, and other defects shall be in accordance with IPC-A-600 and IPC-6012, Class 2.

5.2.15.3 PTH Copper Thickness: Copper plating thickness of the surface and through holes is to be minimum average thickness of 0.0008” (0.8 mils) with a single point thickness minimum of 0.0007” (0.7 mils) per IPC Class 2.

Electrodeposited Copper Plating Thickness Requirement

Feature Minimum Average Thickness Absolute Minimum ThicknessPlated Through Holes 0.0008” 0.0007”

5.2.16 Final Surface Finish

5.2.16.1 Electroless Nickel / Immersion Gold (ENIG):

5.2.16.1.1 Electroless Nickel Thickness: 0.000100” minimum (100 microinches)

5.2.16.1.2 Immersion Gold Thickness: 0.000002” – 0.000010” (2 – 10 microinches)

5.2.16.1.3 Solderability requirements shall be per J-STD-003.

5.2.16.2 Immersion Silver (ImAg):

5.2.16.2.1 Enthone “AlphaLevel” and “AlphaStar”, MacDermid “Sterling” are the only Intel approved immersion silver processes.

5.2.16.2.2 Immersion Silver Thickness:

Enthone “AlphaStar” 0.000006 - 0.000012” (6-12 microinches)MacDermid “Sterling” 0.000006 – 0.000018” (6-18 microinches)

5.2.16.2.3 Immersion Silver thickness measurements should be made on a pad approximately .040”x.040” (1mm square).

5.2.16.2.4 The total copper thickness removed during the immersion silver process must not exceed 0.1 mils (2.5 micron).

5.2.16.2.5 Galvanic corrosion at the silver/soldermask interface must not result in copper thickness less than 1 mil (25 micron).

5.2.16.2.6 Solderability requirements shall be per J-STD-003.



__________________________________________________________________________________

5.2.16.2.7 The final surface finish shall be free from all cosmetic defects and there shall be no discoloration such as tarnish or oxidation that affects solderability. Some discoloration or “yellowing” seen after assembly is acceptable.

5.2.16.2.8 See section 7 for immersion silver handling requirements.

5.2.16.2.9 See section 5.2.20 for via plug requirements when immersion silver is specified.

5.2.16.3 Organic Solderabibility Preservative (OSP):

5.2.16.3.1 Formochem/Everchem F22-G, Entek 106 A(X) HT (Entek Plus HT), Shikoku Glicoat SMD F2LX, Tamura WPF21 (H) are the only Intel approved OSP chemical.

5.2.16.3.3 OSP thickness (measured with standard coupon method provided by chemical vendors) OSP Chemistry Type: OSP Chemistry Thickness Range Formochem/Everchem F22-G 0.20 – 0.40 microns Entek 106 A(X) HT (Entek Plus HT) 0.20 – 0.60 microns Shikoku Glicoat SMD F2LX 0.15 – 0.35 microns Tamura WPF21 (H) 0.20 – 0.40 microns

5.2.16.3.3 OSP color need even across PCB and no copper oxidation be observed.

Below photo cosmetic are rejectable.

Figure 5-4

5.2.16.4 Solder de-wetting, caused by PCB fabrication processes, after assembly shall not exceed 5% on SMT/BGA/CSP lands and test pads. For a PCB, de-wetting refers to the state of poor solder wetting caused by poor final surface finish quality

5.2.17 Electrolytic Gold Contacts

5.2.17.1 Unless otherwise stated, contacts shall be plated with 0.000100" (100 microinches) minimum of low-stress nickel directly over the copper pattern.

5.2.17.2 Unless otherwise stated, contacts shall be plated with 0.000020" (20 microinches) minimum thickness of hard gold directly over nickel.

5.2.17.3 Unless otherwise stated, the edge connectors shall be a minimum depth of 0.260”, as measured from the edge of the beveled board to the end of the contact or the edge of the solder mask coverage. (See Figure 5-5.)



__________________________________________________________________________________

Figure 5-5: Edge Connector Depth Requirement

5.2.17.4 Scratches, pits and dents are acceptable provided there is no exposed nickel and/or copper per IPC 600 and 6012 requirements.

5.2.17.5 There shall be no solder, immersion silver, or residue of any sort allowed on the contact area of the gold fingers.

5.2.17.6 Cosmetic stains or discolorations affecting more than 20% of the area of any single gold finger contact are not allowed without written permission from Intel. Examples of rejectable gold fingers are shown in Figure 5-6.

Figure 5-6: Rejectable Stains and Discoloration on Gold Fingers (examples)

5.2.17.7 The adhesion of the gold plating shall be determined in accordance with Test Method 2.4.10 of IPC-TM-650. Gold particles shall not be on the tape nor shall there be any separation, fracturing or delamination of the gold surface.



__________________________________________________________________________________

5.2.18 Solder Mask

5.2.18.1 The clearances surrounding conductive features may be modified if necessary, provided that adjacent conductors are completely covered and other requirements of this section are satisfied. The maximum allowed nominal clearance on the finished boards around any solder land/pad shall be 0.003” per side. The largest clearance due to misregistration will be 0.006”.

Optimum Registration Maximum Allowed Misregistration

5.2.18.2 Unless otherwise stated, a minimum solder mask web of 0.004” is to be present between all exposed metal pads within a BGA or CSP region. This requirement applies to metal defined pads, solder mask defined pads, encroached solder mask pads, and any combination there of (see figure 5-7).

Figure 5-7: Minimum Solder Mask Web within BGA/CSP Regions

5.2.18.3 Unless otherwise stated, an encroached via design shall have a finished solder mask clearance that is 0.006” diameter larger than the nominal finished hole size. Solder mask residue must not be left in the holes. Encroached via locations shall be referenced on the fab drawing.

5.2.18.4 Misregistration or smear must not cover more than 0.002" of a component through-hole pad to which a solder connection is to be made, provided that a minimum of 0.001” annular ring is left uncovered (see figure 5.8).



__________________________________________________________________________________

5.2.18.5 Unless otherwise stated, misregistration or smear must not cover more than 0.002” of a surface mount pad except as noted below: All BGA lands greater than or equal to 1.0 mm pitch, coverage must not exceed 0.001”. SMT devices less than 0.050” pitch, coverage must not exceed 0.001”. For BGA/CSP less than 1.0 mm pitch, no solder mask allowed on the solder lands.

5.2.18.6 The thickness of solder mask over the top of conductors shall be 0.0001” minimum to 0.002” maximum. This includes solder mask defined pads.

5.2.18.7 The maximum height of solder mask measured over bare fiberglass must be flush with or lower than the total height of SMT or BGA pads. Do not measure solder mask thickness in a location within 0.005” of a solder mask covered copper feature. This requirement is not applicable to fine pitch component with < 10 mil pad to pad spacing.

5.2.18.8 The size tolerance of soldermask defined pads is the same as for metal defined pads, given in Section 5.2.2, Table II. Measurements should be taken at the top of the soldermask opening, rather than at the metal/soldermask interface.

5.2.18.9 Maximum soldermask undercut must not exceed 1 mil (25 micron).

5.2.18.10 Adhesion: The solder mask shall be capable of withstanding Intel assembly processes (see Section 7) followed by tape testing per IPC-TM-650. There shall be no fracturing, separation or delaminating of the solder mask from the surfaces of the bare material or conductors.

5.2.18.11 Chemical Resistance: The solder mask shall not exhibit degradation in surface characteristics such as delaminating, surface roughness, blistering, non-uniform color change or tackiness when tested per IPC-SM-840.

5.2.18.12 Thermal Cycling: The solder mask shall be capable of withstanding 100 thermal cycles from -40 øC to +125 øC as per IPC-TM-650, 2.6.7.1, without visual crazing, blistering, or delaminating when viewed at 10x.

5.2.18.13 Approved Black and Blue Solder Mask MaterialsThe following blue and black solder mask materials are approved for Intel. The use of any unlisted materials will not be permitted prior to qualification tests to ensure assembly process compatibility. It is not permissible to change solder mask on production parts without written Intel approval.



__________________________________________________________________________________

5.2.18.13.1 Black Colored Solder Masks Onstatic R500 4KA Tamura DSR2200 19BL Tamura DSR2200 TT19BR Nan Ya LP4G K-65

5.2.18.13.2 Blue Colored Solder Masks Onstatic R500 BL TAMURA DSR2200 TL06BL

5.2.19 Legend

5.2.19.1 Legend line widths shall be 0.006” minimum to 0.012" maximum and shall be legible. Nominal character heights less than 0.040”are not required to be legible.

5.2.19.2 Legend must be registered within +/- 0.010”.

5.2.19.3 Legend must withstand thermal and chemical conditions of Intel’s manufacturing processes (see section 7).

5.2.19.4 Adhesion of the legend ink shall be determined in accordance with IPC-TM-650. None of the legend shall be removed when subjected to the tape test.

5.2.19.5 Discoloration of the legend after assembly level processing is acceptable provided that the legend remains well adhered and legible.

5.2.20 Via Plug

5.2.20.1 For via plug and Immersion Silver surface finish:

5.2.20.1.1 The via plug must fill >50% of the hole volume. Both sides of the via hole solder mask top surface shall be visible under 10X eyepiece inspection.

5.2.20.1.2 Cracks or voids in the via plug material are allowed if they a) are not located within .005” (0.13mm) of the surface of the via plug, and b) do not touch the hole wall at any point.

5.2.20.1.3 Separation between the via plug material and the hole wall is not allowed.

5.2.21 Breakaway

5.2.21.1 There shall be no dimensional defects in the x, y, or z directions in the breakaway area. Unless otherwise noted, visual defects shall be acceptable provided that the dimensional requirements are met

5.2.22 Microvia



__________________________________________________________________________________

FIGURE 5-9

5.2.22.1 Microvia hole diameter is defined as the laser drilled size of the hole as measured from the topside of the via (Dtop) excluding plating (see Figure 5-9).

5.2.22.2 Bottom hole diameter (Dbottom) shall not be less than 0.0025 inch for typical 4-5mil microvia, and smaller microvias can produce a smaller hole diameter.

5.2.22.3 Resin residue, as depicted in Figure 5-9, at the base of the microvia is not allowed.

5.2.22.4 Copper thickness of the microvia (hole wall and base) shall be minimum 0.0005 inch (0.5 mil) thick for any single point measurement.

5.2.22.5 Burnt Dielectric: The dielectric material directly beneath or adjacent to the inner layer laser pad shall not be melted, separated, contain voids, or otherwise damaged due to the heat generated by the laser process (see figure 5-9).

5.2.22.6 Enclosed voids, as illustrated in Figure 5-10, are not allowed within the microvia holes. Unless otherwise specified, the minimum opening is 0.001 inch (1 mil), when measured at the center of the microvia.

FIGURE 5-10

5.3 FUNCTIONAL INSPECTION

5.3.1 Electrical

5.3.1.1 Measurement equipment used shall have sufficient precision to ensure measurements made are within stated tolerances.

5.3.1.2 100% of the boards shall be tested for continuity using the test method described in IPC-6012, Class 2, section 3.9.2.1. 100% electrical test shall consist of probing every end of the net feature.

5.3.1.3 Continuity and Isolation – Test requirements shall be as follows:

5.3.1.3.1 Test voltage shall be a minimum of 100 Vdc.



__________________________________________________________________________________

5.3.1.3.2 Resistance between isolated conductors shall be a minimum of 5 M.

5.3.1.3.3 Resistance between points measured on the same net shall not exceed 0.5 per inch of circuit length.

5.3.1.3.4 There shall be no circuits with resistance that exceeds 25 ohms.

5.3.1.4 Fixture Requirements: Boards shall be tested using a fixture or flying probe. For a fixture, the test shall be conducted with all probes simultaneously in contact with the board. This means that dual-sided testing is required if there are surface pads on both sides. As a minimum, the test fixture shall include probes that contact the board at the locations listed below. The fixture may contain additional probes, at the manufacturer's discretion.

5.3.1.4.1 Every component through hole.

5.3.1.4.2 Every surface pad that has zero or one trace connected to it.

5.3.1.4.3 Both through holes for each alignment target on the board, if applicable.

5.3.2 Underwriter’s Laboratory Requirements

5.3.2.1 Boards shall be recognized by UL in accordance with UL 796 with a flammability classification of V-0 as defined in UL 94. Boards shall be UL certified for 130 degree C maximum operating temperature.

5.3.2.2 The Vendors UL designation, as defined in section 7, shall be located without interfering with circuitry or nomenclature on the secondary side of the board in copper and shall not be plane areas.

6.0 QUALITY ASSURANCE REQUIREMENTS

6.1 Certificate of Conformance (C of C) data shall be collected on a date code basis and a copy for each date code included with every shipment. A sample Certificate of Conformance showing the minimum requirements is given as Appendix A. Intel will notify supplier of any additional requirements. Any additional information on the material, such as supporting test analyses and traceability information for raw materials, must be maintained at the supplier and available to Intel upon request.

6.1.1 The C of C shall be signed by the quality manager, an engineer, or a person of authority with that person's appropriate title stated below their signature.

6.1.2 The supplier must keep a copy of the C of C on file for a minimum of 12 months. Electronic copy to be available upon request.

6.2 The supplier shall provide monthly process capability information as requested by Intel.

6.3 Supplier shall maintain traceability for raw materials and manufacturing equipment/lines by date code and be available upon request.

6.4 Supplier Outgoing Quality Metrology:

6.4.1 Measurement capability shall be demonstrated for all metrologies used to monitor C of C parameters. Intel must approve measurement capability results. The supplier shall have and supply documented measurement procedures and proven measurement capability for all parameters defined in this specification and appropriate drawings. The supplier shall have documented maintenance and calibration records for all measurement equipment. The supplier shall also have documented records that reflect equipment performance over time (stability) and equipment performance to specifications (capability). These records shall be made available to Intel upon request

6.4.2 Metrology Correlation



__________________________________________________________________________________

When requested by the Intel Materials Engineer, successful correlation of C of C parameter metrology with Intel metrology must be completed.

6.4.3 Visual Inspection CapabilityUpon request, the supplier shall supply documented visual inspection procedures and proven inspection capability for all visual defect criteria defined in this specification. The supplier shall have a documented inspector training and certification program. The supplier shall also have documented records that reflect inspector training and performance over time. The supplier shall have documented maintenance and calibration records for all automated visual inspection equipment. The supplier shall also have documented records that reflect equipment performance over time. These records shall be made available to Intel upon request.

6.4.4 Inspection CorrelationDeviation from the inspection methods indicated may be performed by correlated alternative methods, with approval from Intel. The supplier will furnish acceptable visual inspection correlation data to (and approved by) the Intel materials quality engineer.

6.5 Supplier Change Control Requirements:

6.5.1 The supplier shall maintain suitable manufacturing process controls, and quality assurance to assure that these requirements are met. Intel’s PCB Commodity Management shall be notified prior to any changes in materials or manufacturing processes. This applies to all subcontractors used in the process and the metrologies used to monitor the quality of the product. All projected changes must be supplied to Intel in the form of Supplier Change Horizon in advance of implementing changes.

6.5.2 The supplier is required to forecast and update all known changes (see checklist in appendix B) on a Change Horizon spanning a rolling quarterly period.

6.5.3 Intel must provide written approval of all changes prior to supplier implementation.

6.5.4 If requested by Intel, the supplier shall submit a detailed process flow to assist in the judgment of the classification of changes made.

6.6 Supplier Corrective Action Format

6.6.1 Supplier corrective action may be requested from Intel for quality issues that meet Intel excursion criteria or require supplier corrective action. Intel must approve the supplier’s corrective action report (CAR) format.

6.7 Revision Control:

6.7.1 Intel shall provide a complete Gerber package including Intel part number(s), all file layers, fab drawings, and multipack drawings if applicable. The supplier should reference these part numbers to ensure the proper part number and three-digit revision number is included, If the three-digit revision number (example E78435-002) is not included in the CAD for either the single board or multipack, the supplier will be required to add it.

6.8 Lot Acceptance Criteria

6.8.1 Supplier Expectations:

6.8.1.1 Greater than 5000 DPM for any date code will trigger a supplier excursion.

6.8.1.2 Compliance to Intel’s target Cpk ≥ 1.33 for all critical to function parameters requested by Intel. For CpKs less than 1.33, supplier will provide an improvement plan to Intel upon request.

6.8.2 The criteria for lot acceptance are defined in the C of C.



__________________________________________________________________________________

6.8.3 Intel shall be notified and will provide written approval of any lot that fails C of C criteria prior to shipping.

6.9 Quality Indicators

6.9.1 The following indicators relating to the PCB specifically will be reported to Intel upon request:

6.9.1.1 End of Line Yield (Y) as calculated by the following formula:

Y = total good units into OQA inspection total units inspected

Calculate for each lot and report as an average for the month.

6.9.1.2 Visual Inspection Yield and Defect Pareto

6.9.1.2.1 Report previous month yield percentage of total good vs total inspected.

6.9.1.2.2 Accumulate previous month defect pareto from all defects found in 100 % screening inspection area.

6.9.1.3 Electrical Test Yield and Defect Pareto

6.9.1.3.1 Report previous month yield percentage of total good vs. total tested.

6.9.1.3.2 Provide defect pareto of electrical testing failure modes.

6.9.1.4 In Process Parameter Cpk

6.9.1.4.1 Record Cpk data according to the content and format requested by Intel.

6.10 Qualification

6.10.1 Each supplier shall be qualified by Intel for the level of product technology that they will supply.

6.10.1.1 Qualification requirements may include IPC reliability tests such as thermal shock, solderability, T-260, etc. as well as IST (Interconnect Stress Testing) depending on the technology envelope to be qualified. Typical IST test will require preconditioning at lead-free temperatures (3 passes through reflow oven; peak temperature of 260°C; 60-90 seconds time above liquidous); typical passing criteria is minimum average of 150 cycles for all coupons and no coupon failing before 100 cycles.

6.10.1.2 Intel will provide a comprehensive qualification expectation document whenever a bare board qualification is required

6.10.2 First Article Inspection:

6.10.2.1 If requested, a First Article Inspection will be performed and results sent to the Materials Engineer.

6.10.2.2 First Article Inspections must include results from the following measurements / tests, if applicable, at a minimum:Overall multipack length and width SolderabilityOverall PCB length and width SMT/BGA/CSP pad sizesHole size/position of datum tooling hole(s) Gold plating adhesion (tape test)Overall PCB thickness Impedance by layerFinal surface finish plating thickness Dielectric thickness each layerGold finger plating thickness Solder mask thicknessPCB and/or Multipack warp PTH Cu wall thickness



__________________________________________________________________________________

Solder mask type Solder mask registrationInner layer lines/spaces dimensions Outer layer lines/spaces dimensionsVia percent filled Raw material specificationsStack up construction

6.10.2.3 Micro-section samples taken for the First Article Inspection must be kept for minimum 6 months and made available upon request.

6.10.3 Processes qualified as producing acceptable printed circuit boards shall be the same processes used in the manufacture of production lots.

6.11 Records:

6.11.1 Suppliers shall have established procedures to ensure that boards supplied to Intel comply with the requirements of the purchase order, CAD files, fabrication drawing(s), TEIs, and this specification.

6.11.2 Supplier quality records shall be retained for a minimum period of one year.

6.12 Audits:

6.12.1 The suppliers’ facility shall be available for audit by members of Intel’s PCB Commodity Team as required.

6.13 Environmental Compliance:

6.13.1 All suppliers and their products shipped to Intel are required to comply with Intel’s specification 405-3109 “Environmental and Lead-Free Solder System Requirements for Purchased Electronic Components (including Restriction on Hazardous Substances, RoHS)”, including submission of attachments.

6.13.2 All suppliers are required to comply with Intel’s Environmental Product Content Specification (BS-MTN-0001), including submission of attachments.

6.13.3 RoHS compliance is optional for quick turn suppliers who only supply non-revenue product PCB.

6.13.4 Halogen free PCB raw materials, which include laminates, prepregs, via-plug material and solder mask, are defined as containing less than 900 PPM bromine and 900 PPM chlorine, and less than 1500 PPM combined bromine + chlorine. No red phosphorous to be used as a flame retardant for halogen free materials.

6.13.5 All suppliers are requested to declare environmental compliance by uploading IPC-1752 form through supplier portal, within 3 business days after receiving Intel environmental data requesting notification.

7.0 SPECIAL REQUIREMENTS

7.1 Tools and Documentation:All engineering changes, deviations and off-specifications must be documented and approved by Intel PCB Commodity Management. A document control system must provide for the tracking, purging and status of changes to specific Purchase Orders or Part Numbers.

7.1.1 CAD Data

7.1.1.1 Intel will supply CAD data in Gerber format for generation of film master, drill program and electrical test fixture. Included with the procurement package will be a text file containing the Engineering Parts List (EPL). The EPL is a record of all revision levels for each data file. Any discrepancy between the EPL and data provided must be resolved prior to proceeding with fabrication. When a net list is provided (IPC-D-356,



__________________________________________________________________________________

etc), the supplier shall perform a comparison of supplier-generated net list to the original Intel version supplied. All discrepancies shall be reported to Intel. These items are the property of Intel.

7.1.2 Fabrication drawings:Intel will supply fabrication drawings that define the mechanical features of the board. The main elements of the fabrication drawing are:

7.1.2.1 Profile dimensions and tolerances.

7.1.2.2 Hole chart and location map.

7.1.2.3 Stack up construction dimensions and tolerances (if required).

7.1.2.4 Notes and special requirements.

7.1.3 Film Discrepancies / Changes:

7.1.3.1 The supplier shall be responsible for ensuring that the final generation film is suitable for the production of printed boards in accordance with the fabrication drawing, this specification and the purchase order. All change requests are to be communicated to Intel using VDCR document number E76649. Fabrication shall not commence until all items are addressed and signed off by both Intel and the supplier

7.1.3.2 Any discrepancies found in the film shall be reported immediately to Intel Printed Circuit Board Commodity for resolution.

7.1.3.3 With the following exceptions, no further changes shall be made to the film without prior authorization from Intel.

7.1.3.3.1 Non-functional pads may be removed at the supplier’s discretion.

7.1.3.3.2 Unless otherwise noted on the fabrication drawing or Purchase Order, plating thieves may be added per the requirements outlined in this specification.

7.1.3.3.3 Teardrops may be added to external and internal layers as long as other requirements within this specification, such as minimum spacing, are met.

7.1.4 Drill Discrepancies / Changes

7.1.4.1 If the engineering supplied drill data contains multiple holes at the same X-Y coordinate, the supplier may delete the duplicate holes. If the holes are different sizes, the smaller size shall be deleted.

7.2 Via in Pad for Passive Components (VIP-P) – Obsoleted and intentionally removed from this document

7.3 Via Between Pad (VBP) – Obsoleted and intentionally removed from this document

7.4 Marking Requirements:

7.4.1 General

7.4.1.1 No hand-written markings are acceptable on the PCB

7.4.2 Legend: see section 5 for specific visual, material, and dimensional requirements.



__________________________________________________________________________________

7.4.3 Date Code

7.4.3.1 The secondary side of each board shall contain a permanent date code stating the week and year of manufacture in the format WWYY.WW: WeekYY: YearExample: 1202 = week 12, year 2002

7.4.3.2 For multipacks, each individual board shall contain this code.

7.4.3.3 If required, controlled impedance coupons will also contain a matching date code.

7.4.4 Part number (base and dash) for individual PCB and multipack, if applicable, must be permanently marked on the secondary side of the individual PCBs per mechanical drawing.

7.4.5 Vendor / UL Logo

7.4.5.1 The secondary side of each individual board shall be permanently marked with the vendors’ UL logo and V-0 flammability rating.

7.4.5.2 Marking must not be located in an area that will be routed off or separated from the finished assembly. Marking shall not be etched in plane areas of the board

7.4.6 Electrical Test Mark

7.4.6.1 Each individual board must have a permanent mark as evidence of passing Intel’s requirements for bare board electrical test (see section 5.3).

7.4.6.2 This mark can be a stamp on the surface of the boards or along an edge.

7.4.7 Customs:

7.4.7.1 Unless otherwise specified on the fabrication drawing, all reference to the country of origin (Made in ______ ) shall be removed from the film leaving no such wording on the finished board.

7.4.7.2 The packaging material must be marked with country of origin on each box.

7.4.7.3 If the supplier is required to mark inside bundles of boards this is permitted provided the bags are marked and not the boards.

7.5 Multipack X-outINTEL DOES NOT ALLOW X-OUTS UNLESS OTHERWISE NEGOTIATED.

7.6 Post Processing Requirements:

7.6.1 Rework: There shall be no rework allowed on any PCB unless approved by Intel Corporation.

7.6.1.1 Any rework not authorized in Table IV must be pre-approved in writing by Intel.

7.6.1.1.1 Non-standard rework authorization is to include marking instructions to identify reworked boards.

7.6.1.2 Supplier is to maintain rework records.

7.6.1.2.1 The record shall include work order number, date code, rework process, and quantity reworked.DOCUMENT NUMBER: A84501 Rev 10 Sheet 27 of 40

INTEL CORPORATION CONFIDENTIAL INFORMATION -- DO NOT REPRODUCE


__________________________________________________________________________________

7.6.1.2.2 Records must be retained for a minimum of one year.

7.6.1.2.3 Records must be supplied to Intel upon request.

7.6.1.3 Rework must be inspected.



__________________________________________________________________________________

TABLE IV: REWORK

ReworkType

Allowedor

Not allowed

Method Inspection Limitation

Black oxide Allowed Reprocess Visual 1 oz max. 2X reprocessH oz max. 1X reprocess

Drill missing hole Allowed ReprocessX-ray for PTH

Coordinate measuring machine for NPTH

Panel copper too thin Allowed Manual or auto control of chemical line Cross-section/XRF

Electroless Allowed Reprocess VisualCross-section

Photoresist Allowed Strip & reprocess VisualUnder etching before etch resist removal Allowed Reprocess Visual Record line width and spacing and

report to Intel upon request.

Uncured solder mask Allowed Strip & recoat Visual Max. 1X reprocess

Pre surface finish solder mask touch-up Allowed Brush coat or stencil coat Visual

Max 5% of board area and not to exceed requirements of section 5.1

and 5.2.

Missing via cap Allowed Re-screen/fill VisualBoards must be marked to indicate

extra bake cycle



__________________________________________________________________________________

TABLE IV: REWORK (continued)

ReworkType

Allowedor

Not allowed

Method Inspection Limitation

Gold finger rework Allowed Strip & re-plateNi/Au thickness

Peel strengthVisual

Max. 1X reprocess

Immersion Silver reprocessing Not allowed NA NA

No immersion silver rework without written permission from Intel

Outline dimension Allowed Reprocess Visual/dimensionalOpen trace Allowed IPC-R-700 Visual/Ohm Meter Not allowed for RAMBUS tracesShort trace Allowed IPC-R-700 Visual

Gold finger touch up (solder on gold) Allowed Remove solder spot & re-

plateVisual

Peel strengthMust meet requirements of Section

5.1Solder pad touch up

(insufficient & excess solder)

Allowed Soldering Iron Visual

Warpage (bow and twist) Allowed Stress relief bake Visual/dimensional Must report the bake cycle to Intel

OSP Allowed Strip and Re-coat Visual Max. 1 time and need marking for identification

Panel copper too thick

Not allowed Mechanical removalVisual

Cross-section/XRFElectrical test

Not allowed without written permission from Intel.

Pattern copper Plating Not allowed Strip resist and/or reprocess

Solder FloatCross-section

Not allowed without written permission from Intel.

Solder mask double coat Not allowed

Cured soldermask Not allowed Strip and recoat

PCBA open trace rework Not allowed

Surface finish cleaning Not allowed Jet scrubbing VisualNot allowed on immersion or flash

gold surface



__________________________________________________________________________________

7.6.2 Assembly Process Compatibility: Boards shall be capable of withstanding all Intel assembly process times and temperatures without evidence of delaminating, cracking, blistering, resin recession, or scorching (visible discoloration). Table V is for reference only. Built-in stresses of the materials shall not result in warp as specified in section 5.2 after thermal assembly processes.

Table VReference PROCESS CONDITIONS (subject to change)

MAXIMUM CONDITIONSPROCESS STEP oF oC TIME

Board Baking 230 110 4 hours Wave solder preheat 240 116 2 minutes

Wave Soldering 518* 270* 5 seconds

Manual (de)solder 500 260 10 seconds

SMT reflow 500 260 4 minutesStatic burn-in 260 126 24 hoursRework 500 260 1 minuteSolvent clean (TMS) 110 43 4 minutesAqueous clean 170 77 5 minutes

* Solder Pot Temp - Top side of board and components do not exceed 190oC (374F)

* Typical lead-free thermal cycles shall include 2 passes reflow, one wave solder, and one rework all at maximum board temperature of 260oC.

7.6.3 Rework Simulation:

7.6.3.1 Boards shall be capable of withstanding rework simulation per IPC-TM-650.

7.6.3.2 The test shall be performed after stabilizing the specimens at 23oC, 40 to 60% relative humidity.

7.6.4 Solderability

7.6.4.1 Boards shall meet solderability requirements per J-STD-003. When tested, the specimens shall exhibit proper wetting of the wall of the plated-through hole and associated land.

7.6.5 Thermal Stress

7.6.5.1 Boards shall be capable of withstanding thermal stress per IPC-TM-650, Method 2.6.8. Test temperature shall be 550° +/-10°F for 10 seconds (288°C).

7.6.6 Cleanliness:

7.6.6.1 Per IPC-TM-650, Method 2.3.25 paragraph 4.0. Prior to assembly, bare boards shall have a maximum ionic contamination of 1.56 micrograms per cm2 of NaCl equivalent (10.06 micrograms per in2) of board surface area.

7.7 Special Performance Requirements:DOCUMENT NUMBER: A84501 Rev 10 Sheet 31 of 40

INTEL CORPORATION CONFIDENTIAL INFORMATION -- DO NOT REPRODUCE


__________________________________________________________________________________

7.7.1 Controlled Impedance

7.7.1.1 For boards requiring controlled impedance, the supplier will be responsible for testing to insure that the impedance is controlled within the specified limits. Upon request, supplier shall provide critical process control data.

7.7.1.2 Coupons are required for the following tolerances:

Impedance Type Tolerance Impedance Coupons RequiredSingle Ended < 15% YesStripline Differential < 15% YesMicrostrip Differential < 17.5% Yes

7.7.1.3 For boards requiring coupons :

7.7.1.3.1 Supplier will add test coupons, a minimum of one for each manufacturing working panel, unless the engineering drawing specifies an on-board coupon. The preferred location of the panel coupon is the center of the panel.

7.7.1.3.2 Minimum trace length of each coupon shall be 6.0 inches, and the supplier should measure 50%-70% of the trace.

7.7.1.3.3 The TDR coupon shall have the Intel part number, date code, and vendor permanently marked.

7.7.1.3.4 100% testing of panel coupons required, unless on-board coupons are specified on the engineering drawing and then 100% of the on-board coupons require test. Test data must be made available upon request.

7.7.1.3.5 Test coupons shall be retained at the supplier site for a minimum period of 90 days after shipment of boards.

7.7.2 Fiducials

7.7.2.1 On surface mount boards, fiducials may be located on the boards usually at three corner locations. These features are typically 0.040" round pads surrounded by a 0.120" solder mask clearance. These fiducials are not to be adjusted in size from what is provided in CAD.

7.7.2.2 On multi-pack panels, the board supplier may be required to add fiducials per the dimensions and locations shown on the multi-pack drawing. In order to maintain consistency, these multi-pack fiducials added by the supplier must match the size of the fiducial on the CAD data provided by Intel.

7.7.3 Workmanship

7.7.3.1 Workmanship characteristics shall be in accordance with the preferred or acceptable levels of quality as specified by IPC-A-600, current revision.

7.7.3.2 Outgoing visual inspection shall be conducted at 1.75X (approximately 3 diopters).

7.7.4 Immersion Silver Handling

7.7.4.1 Board shall be handled with clean gloves after the application of immersion silver. Immersion silver coated boards shall not be exposed to sulfur or acids.

7.7.4.2 No labels, stickers, defect markers, ink stamps, markers, or rubber bands should come in contact with solderable areas of the immersion silver board



__________________________________________________________________________________

7.7.5 Compliancy Coupons

7.7.5.1 Certain boards will have registration compliancy coupons located in the corners. A drawing note will identify these locations and specify no custom edits. Only etch compensation is allowed in order to target the exact dimensions provided in the CAD for the finished board.

7.7.5.2 The compliancy coupons must be drilled with the same bit size and drill settings (feeds and speeds) as the vias within the board.

7.7.5.3 The compliancy coupons must be included in the electrical testing of each board.7.7.5.4 The purpose of the compliancy coupon is to serve as a reference to the registration of the drilled via holes to

adjacent copper. Shorted coupons must be reported to Intel and proof of registration compliance must be provided before lot acceptance can be granted.

8.0 PACKAGING/LABELING/SHIPPING REQUIREMENTS

8.1 Packaging Requirements

8.1.1 Packaging materials shall be selected to prevent any degradation, contamination, or mechanical damage of the material.

8.1.2 All boards shall be securely packaged in plastic bags, preferably 10 per bag, not to exceed 15 boards per bag. Package only one date code per bag.

8.1.3 The required package is vacuum pack for non-HAL surface finishing PCB. This requirement is not applicable for Quick turn/NPI builds.

8.1.4 For overseas shipments, each bag must contain a desiccant to minimize moisture absorption during transportation/storage.

8.1.5 The preferred material for packing filler is corrugated cardboard or some other form of paper product and not Styrofoam or CFC materials.

8.1.6 Boards shall be packed in a substantial container to ensure acceptance by common carrier at time of shipment.

8.1.7 Containers shall conform to the requirements of the consolidated freight classification rules in effect at the time of shipment, 25 lbs. recommended maximum per box. Boxes that exceed 25 lbs must be labeled "CAUTION, HEAVY PACKAGE; LIFT WITH CARE". No box shall exceed 35 lbs. in weight.

8.1.8 Each box must be labeled on the outside with the date code(s) of the boards contained therein.

8.1.9 Repackaging must comply with requirements within this section.

8.1.10 8.1.10 Individual paper separation is not required for immersion silver PCB however the top and bottom of each pack must be enclosed with sulfur and acid free paper. Vacuum pack is preferred. See esction 7 for immersion silver handling requirements.

8.1.11 OSP boards don’t need paper separation but need to put paper on top and bottom for each pack.

8.1.12 Use of rubber bands is not allowed.

8.1.13 More than 4 date codes in a shipment is not allowed.

8.2 Labeling Requirements: refer to Intel specification 08-2110 “Incoming Direct Materials Bar-coding Specification” for barcode requirements.



__________________________________________________________________________________

8.3 Shelf Life – Board Supplier

8.3.1 Boards must have date codes showing date of manufacture was less than six months prior to the date of shipment.

8.3.2 Board solderability and all other quality within this specification shall be guaranteed for 12 months from date of manufacture (date code) for all surface finishes.

8.3.3 Immersion silver and OSP boards shall be stored per surface finish vendors’ recommendation

8.4 Shelf Life – Assembly

8.4.1 Boards with a date code older than 12 months must be evaluated prior to use.

9.0 APPENDICES:Appendix A - C of C Requirements for Intel PCBs – reference document onlyAppendix B - Supplier Change Control Checklist

Appendix A: C of C Example



__________________________________________________________________________________


REFERENCE COPY UNLESS COVER SHEET IS STAMPED CONTROLLEDOR CONTROLLED COPY IS CONTAINED IN FOOTER

REFERENCE COPY VALID ONLY ON DATED PRINTED ____________________________________________________________________________________________

Appendix B: Supplier Change Control Checklist

YES NO DOES YOUR CHANGE MEET ANY OF THE FOLLOWING CRITERIA? IF SO, NOTIFY INTEL!

KEY/CRITICAL PARAMETERSY N 1 - Does change affect (or potentially affect) component form, fit, or function?Y N 2 - Change is visually or functionally obvious to IntelY N 3 - Change could cause Intel concern (manufacturability, reliability or performance)Y N 4 - Change to part dimensions or design (including CPD changes)Y N 5 - Changes to CTF parameters

PRODUCT/SITE TRANSFERY N 6 - Move of a production site or the transfer of a piece part material to another production siteY N 7 - Begin use of, or change subcontractors

RAW MATERIALSY N 8 - Change of raw material contentY N 9 - Change to a different material

SHIPPING MATERIALSY N 10 - Change to packing or shipping materialsY N 11 - Change to labels

GENERICY N 12 - Has there been a problem as a result of such a change before?

INSPECTION/MONITORSY N 13 - Change in sampling plan to loosen criteria for lot acceptanceY N 14 – Reduction/elimination in sampling frequency or sample size for key process parameters

MEASUREMENTY N 15 - New measurement method or equipment for TDR, XRF, or CMM

REWORKY N 16 - Implementation of a new rework stepY N 17 - Change to qualified rework procedure

PROCESS FLOWY N 18 - Addition/deletion of a process step in the process flow

PROCESS METHODY N 19 - Change in production line equipmentY N 20 - Relocation of a production lineY N 21 - Change in process chemistry or technology (i.e., plating chemistry, surface

preconditioning)Y N 22 - Change to critical aspect of preventative maintenance procedure




REVISION HISTORY

REV DATE DESCRIPTION0 7/2002 New (converted to ATMO format) PCB Procurement Specification1 5/2003 Incorporated TEI #1 and TEI#2.

Revised section 5.2.16.3.1 to add thickness requirements for MacDermid immersion silver Revised section 5.2.16.3.2 to add MacDermid immersion silver as an approved process Revised section 5.2.18.11.2 to add Goo PSR 550 as an approved photoimageable solder mask Revised section 7.2.2 to specify a target VIP-P hole fill of 40% Added section 7.3.5.6 to specify that VBP vias shall not be via capped on secondary side Revised section 7.8.1.3.1 to clarify requirements if an on-board coupon is provided by the drawing and that the

panel refers to “manufacturers working panel” Revised section 7.8.1.3.4 to clearly specify that 100% impedance testing of panels is required when drawing

specifies tolerances of <15% Revised distribution list to remove Sook Chien Chan and Add SC Woon and Lee Yoke Revised approvers list to remove Carlos Mejia Revised section 5.1.8.2.3 to specify typical and maximum via cap fill percentages Revised sections 5.2.16.1.1 & 5.2.16.2 to specify that solder thickness are for SMT and BGA pads only and not in

the hole wall Revised section 5.2.2 to change line width tolerance to +/-1 mil for 5 mil nominal or less lines Revised sections 7.8.1.2 & 7.8.1.3 to require coupon testing for <+/-20% differential impedance Revised section 8.1.11 to add packaging requirement to ImAg boards to ensure shelf life Revised section 8.3.2 to add language to ensure suppliers guarantee 1 year shelf life for Im Ag

2 10/2003 Revised section 5.1.8.2.5 terminology from “plug” to “cap” Revised section 5.2, Table I terminology from “feature thickness, IL/OL” to “copper thickness, inner layer/outer

layer” Revised section 5.2.6 to specify 1 oz as the default, nominal, internal copper weight Revised section 5.2.7 to specify ½ oz copper as the default, nominal, external copper weight prior to plating Revised section 5.2.13.4 Table III to specify outside corner radius with a preferred condition of rounded at 0.020 –

0.065” rad. Revised section 5.2.18.6 minimum solder mask thickness from 0.0004 inches to 0.0001 inches Added section 5.2.18.11.6 to specify approved black solder masks Revised section 5.3.2.1 UL requirements from “94V-0” to “V-0” Added sections 7.1.4 & 7.1.4.1 to allow duplicate drill holes to be deleted Revised section 7.5.4.1 to specify UL marking as “V-0” Revised Appendix A with new C of C form

3 5/2004 Added section 1.3 to specify that A84501 replaces 454979 procurement specification and that this revision of 84501 replaces all earlier ones.

Revised section 5.2.19.1 to specify legend characters of <0.040” are not required to be legible Revised section 5.2.19.2 to clarify legend registration requirements of +/-0.010” Revised section 5.3.2.1 to specify UL certification of 130C maximum operating temperature Revised section 7.8.1.3.3 to add company logo to TDR coupon marking. Revised marking method from etch to

permanent. Revised approval list by changing Frank Sanders to Van Gatlin, changing John Simmons to Tracy Tang, and

deleting Jayne Mershon4 2/2005 Added sections 4.3, 4.6, 4.19, 4.20, 4.25, 4.32 for various microvia definitions. These additions resulted in

renumbering of the section 4 (definition section). Added sections 5.1.9 and 5.2..21 which cover microvia requirements Revised sections 5.2.5 & 5.2.12.1 – 5.2.12.3 to replace geometric tolerances with linear dimensions Revised section 5.2.16.3.4 to reference section 7 for ImAg handling requirements Added section 5.2.18.11.6 to add Tamura DSR2200 TT19BR as an approved black solder mask Added section 5.2.18.11.7 to specify Onstatic R500 BL and TAMURA DSR2200 TL06BL blue solder mask Added section 5.2.19.5 to specify discoloration of legend after assembly is allowed Revised sections 5.3.2.2. & 7.5.4.2 to disallow etch marking in plane areas Obsoleted sections 7.2 & 7.3 which covered VIP and VBP




Revised section 7.4 to specify 50-100% pre-ImAg via plugging Added section 8.1.12 to limit the number of date codes in one shipment to 4 Revised section 7.7.1, Table IV to specify that rework of cured soldermask and PCBA open trace rework are not

allowed. Also that HASL reprocessing must be done prior to via capping Revised 7.7.2, Table V to incorporate lead –free assembly conditions Revised section 7.7.5.1 to specify 550F thermal stress Added section 7.8.4 to specify immersion silver handling requirements Re-labeled all figures to reflect section numbering Removed Leo Ko from the page 1 approval list at his request. WY Kong will be the sole AMAP approver.

5 2/2006 Added Intel RoHS Environmental Lead Free Requirements specification to Section 3.0 Added Intel Environmental Product Content specification to Section 3.0 Added “Gold Fingers”, “RTP”, and “Test Points” to definitions Section 4.0 Modified 5.1.2.6 to require a separate operation for both via cap and via plug Added 5.1.4.3 and 5.2.17.6 requiring Intel approval for stains on gold contacts > 20% of total pad area, with

example photos of rejectable cosmetic defects Added 5.1.5.2 prohibiting OL thieving within 1” of embedded microstrip impedance traces on adjacent layers Added 5.1.9 and 5.2.20 with requirements for Via Plugging on Immersion Silver boards Modified 5.2.2: added default tolerance for non-specified feature size as +/-20% for features of <25 mils, and +/-

5mil tolerance for features >25 mils Modified Table II in 5.2.2: addition of gold finger tolerance, moved tighter SMT tolerance (+0.5/-2.0 mils) cutoff

to pads of 12 mils or less, and changed “+/-20%” tolerances to “the smaller of +/-20% or +/-5mils” Modified 5.2.3 to use +/-20% tolerance for PTH pads and clearances of <25 mils, and +/-5mil tolerance for >25

mils Modified 5.2.5 and 5.2.12.1: changed drill and feature to datum tolerance back to radial coordinates (undid R4

changes) Modified Table III in 5.2.13.4: addition of gold finger to slot tolerance for edge connector cards Added additional detail drawing for gold finger edge connector slot-to-finger tolerance to 5.2.13.4 Added 5.2.12.1.4 with tolerance for non-plated slot to datum Modified 5.2.16.3.1 to include new immersion silver chemistries to approved list Modified 5.2.16.3.2 to include allowed thickness ranges for new chemistries and changes to existing Added 5.2.16.3.3-5 to include new immersion silver board requirements for soldermask undercut, galvanic

corrosion, and total Cu removal during application process Modified 5.2.16.3.7 to allow discoloration of immersion silver boards after the assembly process Added 5.2.18.8 stating that soldermask defined pads have the same size tolerance as metal defined pads Added 5.2.18.9 prohibiting soldermask undercut at or greater than 1mil Added 6.13 with Intel Environmental Compliance requirements Modified 6.5.1 to include BOLD, highlighting supplier change control requirements Removed Via Cap and Immersion Silver requirements from Section 7 (moved to Sections 5.1 and 5.2) Added 7.4.1.1 prohibiting the use of hand marking on PCBs Modified 8.1.10 to state that vacuum pack is preferred and will be required by 2007 for ImAg boards. Modified Table IV Rework to prohibit reprocessing of Immersion Silver boards without Intel approval Replaced Rakesh Patel with John Davignon on distribution list, removed Daryl Sato from list Replaced John Dungan with Morgan Viggers on approvals list Changed all reference of “CSMO” to “SMO” Modified Appendix A C of C:o Changed solderfloat test temperature to 550F, and now requires representative photo of PTH and via x-sectiono Changed pads to be measured, requested that nominal sizes of measured pads be listedo Copper thickness data to be gathered on smallest vias, not PTHso Removed VBP/VIP fill %o Requires representative photo of via plug on immersion silver boards and via fill % for boards > 0.040” thicko ImAg boards: measure SM undercut, Cu removal during ImAg, and Cu thickness at soldermask/Ag interfaceo State whether RoHS compliant

6 2/2007 Added 6.13.3 to put RoHS requirement as optional for quick turn PCB supplier. Added OSP surface finishing to 5.1.9 Modified 5.2.3 to reduce inner layer clearance pad (anti-pad) size tolerance.




Modified 5.2.20.1.1 to add new via plug visual inspection requirement. Modified 5.2.10 to change minimum dielectric thickness requirement. Modified 7.7.1.2 to change microstrip differential impedance tolerance for 100% measurement. Added 5.2.16.4 for Organic Solderability Preservative (OSP) surface finishing requirement. Added 8.1.11 for OSP PCB packing method. Modified 5.2.18.7 to clarify solder mask thickness measurement location. Modified TABLE IV : REWORK to add OSP PCB rework control

7 9/07 Transferred to SMO.8 4/08 Changed document title from ANSI 14.5M to ASME 14.5

Changed document numbers and titles on Intel Specifications no longer ATMO controlled. Deleted section 4.26 to replace definition of RTP with definition of DTP Deleted sections 4.40 and 4.41 referencing obsolete VIP and VPB processes. Added 5.2.13.5 to document preferred method of creating Mini-PCI gold finger slots. Modified 5.2.5 and 5.2.12 to replace RTP requirements with DTP requirements. Modified 5.2.16.3.1 and .2, removed Uyemura RGA-14 from approved immersion silver lists. Modified 5.2.17.5 to prohibit immersion silver residue on gold fingers Modified 5.2.18.9 to remove ‘soldermask defined pad’ from definition. Undercut applies to all s/m openings. Modified 6.10.2.2 to replace VIP and VBP with via percent fill. Added 7.7.5 to clarify requirements for compliancy coupons Modified 8.1.10 to allow packaging without innerleaf separation. Updated list of approvers on coversheet Changed document number to rev 8

9 4/09 Deleted distribution/notification list Changed approvals name list, added YC Chew to materials and deleted TD. Added 1.2 stating that PTP and Intel consign need follow this specification. Added “PTP” to definition section 4.0. Added 5.2.14.3 requiring Tg130-145° C material for <70mil boards, and minTg170 ° C for >=70mil boards. Deleted the first sentence of 5.2.16.1, which states “Unless otherwise specified, boards shall be fabricated

using the Solder mask Over Bare Copper (SMOBC) process with solder finish” Added 5.2.16.3 to include Entek Plus HT in parenthesis with Entek 106 a (X) HT. Deleted commonly used and outdated solder mask materials. Added 5.2.22.2 stating the criteria is based on typical 4-5mil micro-via Added “Halogen Free PCBs” requirement to 6.13 Added 8.1.3 requiring vacuum pack. Modified 8.3.2 requiring 12 month shelf life guarantee for board general quality. Added 8.3.3 requiring boards’ storage per surface finish vendors’ recommendation. Changed document number to rev 9

10 4/10 Changed approvals name list Updated 3.6&3.7reference documents, and removed outdated reference docs in 3.9&6.5 Added 4.38 VDCR definition and 7.1.3.1 VDCR requirement Modified 5.1.7 to make the requirement applicable for gold surface finish Modified Table II to align with IPC measuring at the “base” for all conductive features Expanded 5.2.13.1 to include <0.062” PCB finished thickness tolerance Added a comment to Table III to make the table refer to 0.062” and below boards Removed figure 5-3B Modified 5.2.14.2 material Tg selection criteria Removed 5.2.15,5.2.16,7.6.1.2.2 and 7.6.1.2.3 HASL requirements Removed 5.2.16.2.2 Alpha Level as it is not applicable. Modified 5.2.16.3.2 Glicoat spec to 0.15-0.35 microns Rewrited 5.1.3.1&5.2.17.4 to, scratches, pits and dents are acceptable provided that no nickel and copper expose Rewrited 6.7 Removed 6.8.1.2 and rewrited 6.8.1.3 Modified 6.9.1 from on monthly basis to upon Intel request Modified 6.10 to include reliability testing




Added 6.13.4 requiring no red phosphorous to be used as flame retardant for halogen free materials. Added 6.13.5 requiring uploading IPC-1752 through supplier portal within 3 business days Updated rework table IV Added table V to include typical lead-free thermal cycles Added to 7.7.1.3.2 requiring measure 50%-70% of impedance coupon trace Updated COC
