04/19/23 1

Prime Indicants: A Synthesis Method for

Indicating Combinational Logic Blocks

Will TomsSchool of Computer ScienceUniversity of Manchester

04/19/23 2

Process Variation

Process Variation at 45nm: Transistor Delay: 20-23% Interconnect Delay: 10%

Self-Timed circuits more robust to variations in

propagation delay

No external timing assumptions

Indication - status of internal signals can be determined

by the outputs of the gates

04/19/23 3

Indicating Combinational Logic

Validity must be encoded into the datapath

DI (unordered) encoding (dual-rail/m-of-n)

Each data word transmitted explicitly

Need to return to known state (Four-phase/RTZ)

Functions difficult to specify:

Functions completely specified

All minterms must be enumerated

Impractical for large datapath operations

04/19/23 4

Desynchronisation

Can construct large indicating datapaths from

synchronous circuits by expanding gates into dual-rail

equivalents

04/19/23 5

Desynchronisation

Desynchronised networks can be optimised by

reducing indication:

Relaxation (Jeong, Zhou):

Removing redundant indication (fanout of gates)

Relative-Timing (Chelcea):

Applying timing constraints to avoid indication

Validity (NCL-X):

Adding additional signals for indication

04/19/23 6

Desynchronisation

Properties of self-timed datapaths differ from

conventional datapaths:

Invertions are free (in 1-of-N codes)

N-input complex gates (approximately) same cost as

N-input simple gate

Mapping desynchronised networks to DI-codes

other than dual-rail (possibly 1-of-4) expensive

04/19/23 7

Block-Level Approach

Self-timed datapaths constructed from complex function-

blocks:

Small blocks consisting of up to 10 binary inputs and outputs

04/19/23 8

Block-Level Approach

Existing optimisations applied between function

blocks

Distribute indication between the outputs of

function blocks

Can use any encoding between function blocks

04/19/23 9

Block-Level Approach

How to synthesise arbitrary indicating function

blocks?

04/19/23 10

Indication

In four-phase indicating logic, transitions

between spacer and data-values form allowed-

transition sets (ATS):

Each ATS describes all the possible states of the

inputs (or outputs) within the transition

0000 0101 = {0000,0100,0001,0101}

04/19/23 11

Indication

The adjacent transitions of an ATS are the states

distance 1 from final state

Each adjacent transition has an associated variable ε that

transitions

0000 0101 = {0100(x4),0001(x2)}

Function f indicates the input transitions of an ATS if for

each adjacent transition f is dependent on variable ε

f(ε=0) ≠ f(ε=1)

04/19/23 12

Indication

In order for a function block to be indicating for each

adjacent transition in each ATS, at least one output

function must be dependent on variable ε

Checking Indication is expensive:

8 input/8 output-function block has 256 ATS each with 8

adjacent transitions = 16,384 (256*8*8) dependency checks to

verify an implementation

04/19/23 13

Indication Architecture

Need an architecture that is correct by

construction

Implement each output function as a sum-of-

products where each product is given by ε(a,b)

(the inputs that transition in ATS (a-b))

Each product implemented by a C-element to

cover return-to-zero transitions

04/19/23 14

Indication Architecture

Each term ε(a,b) is mutually-exclusive and so

function indicates all of its input transitions.

C

a0

Cb0

ci0

a0b1

ci1

f

C

04/19/23 15

Indication Architecture

Large

Slow

As function block has several outputs, the number of

outputs that indicate each transition is often >1

Can optimise architecture by reducing the number of

outputs that indicate each input transition

04/19/23 16

Prime Implicants

Implicant of a function, f, is a function p where:

p f

A Prime Implicant is an implicant not contained

in any other

Minimum cost Sum-of-Products implementation

must always consist of a sum of prime implicants

04/19/23 17

Prime Implicants

Prime Implicants generated from minterms by consensus:

f = x1x2 + x2x3

1

10

0

0 0

0 1

000

100

111

110

001

101

011

010

1

10

0

0 0

0 1

f = x1x2x3 + x1x2x3 + x1x2x3 _ _

04/19/23 18

Prime Implicants

Function constructed by minimum cost covering of

prime implicants

Unate Covering Problem (UCP)

€

x1x2x3x4

€

x1x2x3 x4

€

x1x2 x3 x4

€

x1x2x3x4

€

x1x2 x3 x4

€

x1x2 x3 x4

€

x2 x3 x4

€

x1x2

€

x1x4

€

x1x3

1 1

1 1 1

1 1 1

1 1 1

04/19/23 19

Optimisation of Indicating Logic

Removing literals from function terms reduces

indication

Optimising one function can prevent further

optimisations of other functions

Need to consider all functions together

May not be possible to construct indicating

solution from prime implicants

04/19/23 20

Optimisation of Indicating Logic

Two phase approach:

Construct minimum cost indicating cover for

each function

Determine un-indicated input transitions and

reduce existing function terms to cover them

04/19/23 21

Indicant

In indicating function terms have two roles:

Implicate AND Indicate

An indicant is an implicant that indicates the transitions on

its literals

The indicants of a function must be mutually-exclusive

A function block constructed from indicant covers of its

functions will indicate all internal transitions and some

input transitions

Minimum cost implementation of Function Block

04/19/23 22

Indicant Cover

Construct the lowest cost mutually-exclusive

cover for each function

Unate Covering Problem:

Determine prime implicants of each function

Enumerate all the expanded implicants

Determine non-overlapping cover

04/19/23 23

Unindicated Inputs

Can easily determine unindicated input transitions

Literals not present in the indicants of any function

Reduce Indicants by re-inserting the literals

Partitions Indicant into multiple indicants

All functions must remain unate

Need to ensure that new indicants:

Cover exactly the same minterms

Are mutually-exclusive

04/19/23 24

Unindicated Literals

Indicant a0 covers 6 minterms:

a0b0c0, a0b0c1, a0b0c2, a0b1c0, a0b1c0, a0b1c1, a0b1c2

Reducing by literal b0 results in two indicants

a0b0: {a0b0c0, a0b0c1, a0b0c2}

a0b1: {a0b1c0, a0b1c1, a0b1c2}

Reducing by literal c0 results in three indicants

a0c0: {a0b0c0, a0b1c0}, a0c1: {a0b0c1, a0b1c1}

a0c2: {a0b0c2, a0b1c2}

04/19/23 25

Unindicated Literals

Reducing the indicants by more than one literal

multiplies the number of indicants

Reducing Indicant a0 by b0 and c0 gives 6

indicants:

a0b0c0, a0b0c1, a0b0c2, a0b1c0, a0b1c0, a0b1c1, a0b1c2

04/19/23 26

Unindicated Literals

Use UCP to determine the lowest cost

reductions that will cover all of the unindicated

inputs

Cost of a reduction can change depending on

selection of other reductions

Eliminates several reduction strategies

But distributes the reductions between functions

04/19/23 27

Offset Optimisation

Initial function implementations use C-elements

Can distribute the indication of the RTZ

transitions throughout the indicants

Can use conventional UCP

A range of strategies introduced that target

generalised C-elements or AND-gates

04/19/23 28

Results

Use clustering algorithm to create suitable-sized

function blocks from ISCAS Benchmarks

Results show the effectiveness of optimisation

Literal Count

Not a direct comparison with desynchronisation

techniques

Techniques fit into desynchronisation framework

04/19/23 29

Results

Circuit Inputs OutputsNon

Opt Arc

Opt ArcDesynchronisati

onBest Total

% Decreas

eOn-set Off-set

drfulladder 6 4 96 60 37.5 40 20 -1of4fulladder 10 6 384 216 43.8 144 72 -3of6fulladder 14 8 44800 17806 60.3 15175 2631 -C6288_131 6 6 144 35 75.7 22 13 32C6288_871 6 6 144 39 72.9 22 9 64C6288_173 8 6 640 79 87.7 62 17 72C6288_52 12 14 5376 173 96.8 139 31 152C6288_43 12 12 3840 162 95.8 118 44 204

C6288_140 16 18 36864 247 99.3 202 45 264C6288_144 16 16 32768 275 99.1 213 62 272

99.1%

Approx Equal Literal Count

Significantly Reduced

04/19/23 30

Summary

Developed new technique to synthesis arbitrarily

encoded indicating function blocks

Large reduction in literal count over initial

specification

Can be employed within desynchronisation

framework

04/19/23 31

VERDAD

New project to look at incorporating verification

techniques in self-timed synthesis operations

Inconjunction with Newcastle University.

Funded by EPSRC

PhD Studentship available