procesador de 8 bits de clase

FACULTAD DE INGENIERÍA ELECTRÓNICA - UNMSM

TRABAJO

Implementación de la ruta de datos en VHDL del procesador de 8 bits.

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;

library LPM;use LPM.LPM_COMPONENTS.all;

entity PROCESADOR_8BITS isport( sel_A,sel_D: in std_logic_vector(1 downto 0);

selM,selI,clk: in std_logic; inmediato: in std_logic_vector(7 downto 0); cod: in std_logic_vector(2 downto 0); R: buffer std_logic_vector(7 downto 0));

end PROCESADOR_8BITS;

architecture solution of PROCESADOR_8BITS iscomponent ALU_8BITS

port ( A,B : in std_logic_vector(7 downto 0); OPER : in std_logic_vector(2 downto 0);

F : out std_logic_vector(7 downto 0));end component;

component banc_reg port( sel_A,sel_B,sel_D: in std_logic_vector(1 downto 0);

clk,w: in std_logic; dato: in std_logic_vector(7 downto 0);

A,B: out std_logic_vector(7 downto 0));end component;

component LPM_RAM_DQ generic (LPM_WIDTH: positive; LPM_TYPE: string := L_RAM_DQ; LPM_WIDTHAD: positive;

LPM_NUMWORDS: string := UNUSED; LPM_FILE: string := UNUSED; LPM_INDATA: string := "REGISTERED"; LPM_ADDRESS_CONTROL: string := "REGISTERED";

LPM_OUTDATA: string := "REGISTERED";LPM_HINT : string := UNUSED);

port (DATA: in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0); ADDRESS: in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);

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WE: in STD_LOGIC := '1'; INCLOCK: in STD_LOGIC := '0'; OUTCLOCK: in STD_LOGIC := '0'; Q: out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));

end component;

signal H,W: std_logic;signal U,E,T,S,L: std_logic_vector(7 downto 0);

beginU1: banc_reg port map (sel_A,inmediato(7 downto 6),sel_D,clk,H,S,U,E);U2: ALU_8BITS port map(U,L,cod,R);U3: LPM_RAM_DQ generic map (LPM_WIDTH => 8,

LPM_WIDTHAD => 8, LPM_FILE => "PROCESADOR_8BITS.MIF", LPM_INDATA => "UNREGISTERED",

LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA => "UNREGISTERED")

port map (DATA => U, ADDRESS => inmediato, WE => W1, Q => T);

L <= E when selI = '0' else inmediato;S <= R when selM = '0' else T;H <= selM nand selI;W1 <= not H;out_A <= U;out_B <= E;

end solution;

Instrucciones para la operación: 2x – 3y donde los valores de X e Y están ubicados en la dirección de memoria 20H y 21H:



INSTRUCCIÓN

CODIGO

SELI

SELM

SEL_D

SEL_A

INMEDIATO

LD R0,20H X X X 0 1 0 0 X X 0 0 1 0 0 0 0 0LD R1,21H X X X 0 1 0 1 X X 0 0 1 0 0 0 0 1

ADD R0,R0,R0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X XADD R2,R1,R1 0 0 0 0 0 1 0 0 1 0 1 0 X X X X XADD R1,R2,R1 0 0 0 0 0 0 1 1 0 0 1 0 X X X X XSUB R3,R0,R1 0 0 1 0 0 1 1 0 0 0 1 0 X X X X X

Los datos grabados en las posiciones 20H y 21H de la memoria son 2 y 1 respectivamente:



La simulación se muestra a continuación


procesador de 8 bits de clase

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