probabilistic verification tong wang tw2436 yihan zou yz2575 hang yin hy2368 miaoqiong wang mw2908...
DESCRIPTION
Assumptions RTT >> Tx: multiple messages on channel FC and BC are FIFO queues: packets arrive in order Sender/ Receiver can only process one packet at a time Sender always has packet to send Timeout occur Stopping conditions Initial state: ( 0 0 (0,1,2,3) ( ) )TRANSCRIPT
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Probabilistic Verification
Tong Wang tw2436Yihan Zou yz2575Hang Yin hy2368
Miaoqiong Wang mw2908
of Go-Back-N
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Assumption
Components of states
Flow chart of algorithm
Analysis
Agenda
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AssumptionsRTT >> Tx: multiple messages on channel
FC and BC are FIFO queues: packets arrive in order
Sender/ Receiver can only process one packet at a time
Sender always has packet to send
Timeout occur
Stopping conditions
Initial state: ( 0 0 (0,1,2,3) ( ) )
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SI
SW
a>=baseF
Tbase=a+1
Xmit M(base)……M(base+3)Reset timer
Base=0Xmit M(base)…M(base+3)
Initial
Rcv Ack(0)Wait for Ack
TimeoutXmit M(base)…M(base+3)
Start timer
Source
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SWSI
Initial
Xmit Ack(e)s=e?
Rcv M(s)
e=e+1M(s)->AppXmit Ack(e)
TF
Receiver
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Timeout
Backward channel is empty
Both forward and backward channel is empty
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Stopping points
3 lost packages on the channel
ACK0 is successfully received
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Global state (Tx, Rx, FC, BC)
Four stacks: stack(i) contains states going through i low probability transitions
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Initial(0 0 (0,1,2,3) ()) Get M0, Get M1, Get M2, Get M3 0
step 1 Pop (0 0 (0,1,2,3) ()) (0 1 (1,2,3) (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 0(0 0 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3 1
step 2 Pop (0 1 (1,2,3) (0)) ,(1 1 (1,2,3,4) ()) is accepted
(0 2 (2,3) (0,1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 0(0 1 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 1(0 1 (2,3) (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 1(0 0 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3 1
step 3 Pop (0 2 (2,3) (0,1)) ,(1 2 (2,3,4) (1)) is accepted
(0 3 (3)(0,1,2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, AcptM1, AcptM2 0(0 2 (2,3) (1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 1(0 2 (3) (0,1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 1(0 1 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 1(0 1 (2,3) (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 1(0 0 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3 1
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Stopping point analysis
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step 49 Pop (0 3 () (1,2)) ,(2 3 (4,5) (2)) is accepted
(0 4 () (2,3)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2, Acpt M3 2 (0 3 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 3 () (2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 2 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 2 () (1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 1 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 1 () (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 0 (3) ()) Get M0, Get M1, Get M2, Get M3 3 (0 0 () ()) Get M0, Get M1, Get M2, Get M3 3 (0 0 (0,1,2,3) ()) Get M0, Get M1, Get M2, Get M3 3 (0 4 () (1,2,3)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2, Acpt M3 3 (0 3 (3) (1,2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 3 () (0,1,2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 2 (2,3) (1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 2 (3) (0,1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 1 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 1 (2,3) (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 0 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3 3
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step 50 Pop (0 4 () (2,3)) ,(3 4 (4,5,6) (3)) is accepted
(0 4 () (3)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2, Acpt M3 3 (0 3 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 3 () (2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 2 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 2 () (1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 1 (3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 1 () (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 0 (3) ()) Get M0, Get M1, Get M2, Get M3 3 (0 0 () ()) Get M0, Get M1, Get M2, Get M3 3 (0 0 (0,1,2,3) ()) Get M0, Get M1, Get M2, Get M3 3 (0 4 () (1,2,3)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2, Acpt M3 3 (0 3 (3) (1,2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 3 () (0,1,2)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1, Acpt M2 3 (0 2 (2,3) (1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 2 (3) (0,1)) Get M0, Get M1, Get M2, Get M3, Acpt M0, Acpt M1 3 (0 1 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 1 (2,3) (0)) Get M0, Get M1, Get M2, Get M3, Acpt M0 3 (0 0 (1,2,3) ()) Get M0, Get M1, Get M2, Get M3 3
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Table1(157 steps)
Table2(50 steps)
VS
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Self Critique1. Additional assumptions about channel
RTT>> Tx, push 4 msg into channel, omit the possibility of Rx prompt reply (concurrency)
RTT < timeout interval, omit the possibility of pre-mature timeout (fixed already)
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Self Critique (cont’d)2. No mapping of msg # from Real Number to finite set of number {0,1,2,3}
Hard to justify stopping point, successful reception of ACK(100) does not guarantee the successful reception of ACK(101)
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Self Critique (cont’d)
3. Insufficient justification of stopping
We stop verification when first message is successfully received, and take it for granted that the following messages can be received (need to verify!)
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Self Critique (cont’d)Our valuables:
Stack processing technique
Under our assumptions, reasonable results are obtained
Succinct implementation of program
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Thank you!