principles of computer architecture miles murdocca and vincent heuring appendix a: digital logic
DESCRIPTION
Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic. Chapter Contents. A.11 Sequential Logic A.12 Design of Finite State Machines A.13 Mealy vs. Moore Machines A.14 Registers A.15 Counters. A.1 Introduction A.2 Combinational Logic - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/1.jpg)
A-1 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring
Appendix A: Digital Logic
![Page 2: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/2.jpg)
A-2 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Chapter Contents
A.1 Introduction
A.2 Combinational Logic
A.3 Truth Tables
A.4 Logic Gates
A.5 Properties of Boolean Algebra
A.6 The Sum-of-Products Form, and Logic Diagrams
A.7 The Product-of-Sums Form
A.8 Positive vs. Negative Logic
A.9 The Data Sheet
A.10 Digital Components
A.11 Sequential Logic
A.12 Design of Finite State Machines
A.13 Mealy vs. Moore Machines
A.14 Registers
A.15 Counters
![Page 3: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/3.jpg)
A-3 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Some Definitions
• Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder.
• Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit.
• Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller.
![Page 4: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/4.jpg)
A-4 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Combinational Logic Unit• Translates a set of inputs into a set of outputs according to one or
more mapping functions.
• Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 v. and 0 v. for example.
• The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i0 – in are presented to the CLU, which produces a set of outputs according to mapping functions f0 – fm
![Page 5: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/5.jpg)
A-5 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Truth Tables• Developed in 1854 by George Boole
• further developed by Claude Shannon (Bell Labs)
• Outputs are computed for all possible input combinations (how many input combinations are there?
Consider a room with two light switches. How must they work†?
†Don't show this to your electrician, or wire your house this way. This circuit definitely violates the electric code. The practical circuit never leaves the lines to the light "hot" when the light is turned off. Can you figure how?
![Page 6: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/6.jpg)
A-6 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Alternate Assignments of Outputs to Switch Settings
• Logically identical truth table to the original (see previous slide), if the switches are configured up-side down.
![Page 7: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/7.jpg)
A-7 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Truth Tables Showing All Possible Functions of Two Binary Variables
• The more frequently used functions have names: AND, XOR, OR, NOR, XOR, and NAND. (Always use upper case spelling.)
![Page 8: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/8.jpg)
A-8 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Logic Gates and Their Symbols
• Note the use of the “inversion bubble.”
• (Be careful about the “nose” of the gate when drawing AND vs. OR.)
Logic symbols for AND, OR, buffer, and NOT Boolean functions
![Page 9: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/9.jpg)
A-9 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Logic symbols for NAND, NOR, XOR, and XNOR Boolean functions
![Page 10: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/10.jpg)
A-10 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Variations of Basic Logic Gate Symbols
![Page 11: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/11.jpg)
A-11 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Inverter at the Transistor Level
Transistor Symbol
Power Terminals A Transistor Used
as an InverterInverter TransferFunction
![Page 12: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/12.jpg)
A-12 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Allowable Voltages in Transistor-Transistor-Logic (TTL)
![Page 13: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/13.jpg)
A-13 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Transistor-Level Circuits For2-Input a) NAND and b)NOR Gates
![Page 14: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/14.jpg)
A-14 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Tri-State Buffers• Outputs can be 0, 1, or “electrically disconnected.”
![Page 15: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/15.jpg)
A-15 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Basic Properties of Boolean Algebra
Postulates
Theorems
A, B, etc. are Literals; 0 and 1 are constants.
Principle of duality: The dual of a Boolean function is gotten by replacing AND with OR and OR with AND, constant 1s by 0s, and 0s by 1s
![Page 16: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/16.jpg)
A-16 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
DeMorgan’s Theorem
Discuss: Applying DeMorgan’s theorem by “pushing the bubbles,” and “bubble tricks.”
![Page 17: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/17.jpg)
A-17 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Sum-of-Products (SOP) Form
• Transform the function into a two-level AND-OR equation
• Implement the function with an arrangement of logic gates from the set {AND, OR, NOT}
• M is true when A=0, B=1, and C=1, or when A=1, B=0, and C=1, and so on for the remaining cases.
• Represent logic equations by using the sum-of-products (SOP) form
Fig. A.15—Truth Table for The Majority Function
![Page 18: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/18.jpg)
A-18 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The SOP Form of the Majority Gate
• The SOP form for the 3-input majority gate is:
• M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = (3, 5, 6, 7)
• Each of the 2n terms are called minterms, running from 0 to 2n - 1
• Note the relationship between minterm number and boolean value.
• Discuss: common-sense interpretation of equation.
![Page 19: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/19.jpg)
A-19 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A 2-Level AND-OR Circuit that Implements the Majority Function
Discuss: What is the Gate Count?
![Page 20: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/20.jpg)
A-20 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Notation Used at Circuit Intersections
![Page 21: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/21.jpg)
A-21 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A 2-Level OR-AND Circuit that Implements the Majority Function
![Page 22: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/22.jpg)
A-22 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Positive vs. Negative Logic•Positive logic: truth, or assertion is represented by logic 1, higher voltage; falsity, de- or unassertion, logic 0, is represented by lower voltage.•Negative logic: truth, or assertion is represented by logic 0 , lower voltage; falsity, de- or unassertion, logic 1, is represented by lower voltage
![Page 23: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/23.jpg)
A-23 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Positive and Negative Logic (Cont’d.)
![Page 24: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/24.jpg)
A-24 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Bubble Matching
• Active low signals are signified by a prime or overbar or /.
• Active high: enable
• Active low: enable’, enable, enable/
• Discuss microwave oven control:
• Active high: Heat = DoorClosed • Start
• Active low: ? (hint: begin with AND gate as before.)
![Page 25: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/25.jpg)
A-25 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Bubble Matching (Cont’d.)
![Page 26: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/26.jpg)
A-26 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Digital Components
• High level digital circuit designs are normally made using collections of logic gates referred to as components, rather than using individual logic gates. The majority function can be viewed as a component.
• Levels of integration (numbers of gates) in an integrated circuit (IC):
• Small scale integration (SSI): 10-100 gates.
• Medium scale integration (MSI): 100 to 1000 gates.
• Large scale integration (LSI): 1000-10,000 logic gates.
• Very large scale integration (VLSI): 10,000-upward.
• These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits.
• Let us consider several useful MSI components:
![Page 27: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/27.jpg)
A-27 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Data
Sheet
![Page 28: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/28.jpg)
A-28 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Multiplexer
![Page 29: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/29.jpg)
A-29 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Implementing the Majority Function with an 8-1 Mux
Principle: Use the mux select to pick out the selected minterms of the function.
![Page 30: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/30.jpg)
A-30 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
More Efficiency: Using a 4-1 Mux to Implement the Majority Function
Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX input is selected from {0, 1, C, C} to pick the desired behavior of the minterm pair.
![Page 31: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/31.jpg)
A-31 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Demultiplexer (DEMUX)
![Page 32: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/32.jpg)
A-32 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Demultiplexer is a Decoder with an Enable Input
Compare toFig A.29
![Page 33: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/33.jpg)
A-33 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A 2-4 Decoder
![Page 34: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/34.jpg)
A-34 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Using a Decoder to Implement the Majority Function
![Page 35: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/35.jpg)
A-35 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
The Priority Encoder• An encoder translates a set of inputs into a binary encoding,
• Can be thought of as the converse of a decoder.
• A priority encoder imposes an order on the inputs.
• Ai has a higher priority than Ai+1
![Page 36: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/36.jpg)
A-36 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Programmable Logic Arrays (PLAs)
• A PLA is a customizable AND matrix followed by a customizable OR matrix:
![Page 37: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/37.jpg)
A-37 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Using a PLA to Implement the Majority Function
![Page 38: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/38.jpg)
A-38 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Using PLAs to Implement an Adder
![Page 39: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/39.jpg)
A-39 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Multi-Bit Ripple-Carry Adder
PLA Realization of a Full Adder
![Page 40: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/40.jpg)
A-40 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Sequential Logic
• The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs.
• There is a need for circuits with memory, which behave differently depending upon their previous state.
• An example is a vending machine, which must remember how many and what kinds of coins have been inserted. The machine should behave according to not only the current coin inserted, but also upon how many and what kinds of coins have been inserted previously.
• These are referred to as finite state machines, because they can have at most a finite number of states.
![Page 41: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/41.jpg)
A-41 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Classical Model of a Finite State Machine
• An FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information.
![Page 42: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/42.jpg)
A-42 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
NOR Gate with Lumped Delay
• The delay between input and output (which is lumped at the output for the purpose of analysis) is at the basis of the functioning of an important memory element, the flip-flop.
![Page 43: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/43.jpg)
A-43 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
S-R Flip-Flop
• The S-R flip-flop is an active high (positive logic) device.
![Page 44: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/44.jpg)
A-44 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
NAND Implementation of S-R Flip-Flop
![Page 45: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/45.jpg)
A-45 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Hazard
• It is desirable to be able to “turn off” the flip-flop so it does not respond to such hazards.
![Page 46: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/46.jpg)
A-46 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
A Clock Waveform: The Clock Paces the System
• In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs settle at the correct value when the clock next goes high.
![Page 47: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/47.jpg)
A-47 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Scientific Prefixes
• For computer memory, 1K = 210 = 1024. For everything else, like clock speeds, 1K = 1000, and likewise for 1M, 1G, etc.
![Page 48: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/48.jpg)
A-48 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Clocked S-R Flip-Flop
• The clock signal, CLK, enables the S and R inputs to the flip-flop.
![Page 49: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/49.jpg)
A-49 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Clocked D Flip-Flop
• The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop (next slide) addresses this problem.
![Page 50: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/50.jpg)
A-50 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Master-Slave Flip-Flop
• The rising edge of the clock loads new data into the master, while the slave continues to hold previous data. The falling edge of the clock loads the new master data into the slave.
![Page 51: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/51.jpg)
A-51 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Clocked J-K Flip-Flop• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R flip-flop, because Q enables J while Q’ disables K, and vice-versa.
• However, there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset state, the flip-flop will “catch” the 1. This is referred to as “1’s catching.”
• The J-K Master-Slave flip-flop (next slide) addresses this problem.
![Page 52: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/52.jpg)
A-52 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Master-Slave J-K Flip-Flop
![Page 53: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/53.jpg)
A-53 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Clocked T Flip-Flop
• The presence of a constant 1 at J and K means that the flip-flop will change its state from 0 to 1 or 1 to 0 each time it is clocked by the T (Toggle) input.
![Page 54: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/54.jpg)
A-54 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Negative Edge-Triggered D Flip-Flop• When the clock is high, the two input latches output 0, so the Main latch remains in its previous state, regardless of changes in D.
• When the clock goes high-to-low, values in the two input latches will affect the state of the Main latch.
• While the clock is low, D cannot affect the Main latch.
![Page 55: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/55.jpg)
A-55 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example: Modulo-4 Counter
• Counter has a clock input (CLK) and a RESET input.
• Counter has two output lines, which take on values of 00, 01, 10, and 11 on subsequent clock cycles.
![Page 56: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/56.jpg)
A-56 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
State Transition
Diagram for Mod-4
Counter
![Page 57: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/57.jpg)
A-57 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
State Table for Mod-4 Counter
![Page 58: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/58.jpg)
A-58 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
State Assignment for Mod-4 Counter
![Page 59: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/59.jpg)
A-59 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Truth Table for Mod-4 Counter
![Page 60: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/60.jpg)
A-60 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Logic Design for Mod-4 Counter
![Page 61: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/61.jpg)
A-61 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example: A Sequence Detector
• Example: Design a machine that outputs a 1 when exactly two of the last three inputs are 1.
• e.g. input sequence of 011011100 produces an output sequence of 001111010.
• Assume input is a 1-bit serial line.
• Use D flip-flops and 8-to-1 Multiplexers.
• Start by constructing a state transition diagram (next slide).
![Page 62: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/62.jpg)
A-62 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Sequence Detector State Transition Diagram
• Design a machine that outputs a 1 when exactly two of the last three inputs are 1.
![Page 63: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/63.jpg)
A-63 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Sequence Detector State Table
![Page 64: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/64.jpg)
A-64 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Sequence Detector State Assignment
![Page 65: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/65.jpg)
A-65 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Sequence Detector Logic Diagram
![Page 66: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/66.jpg)
A-66 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example: A Vending MachineController
• Example: Design a finite state machine for a vending machine controller that accepts nickels (5 cents each), dimes (10 cents each), and quarters (25 cents each). When the value of the money inserted equals or exceeds twenty cents, the machine vends the item and returns change if any, and waits for next transaction.
• Implement with PLA and D flip-flops.
![Page 67: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/67.jpg)
A-67 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Vending Machine State TransitionDiagram
![Page 68: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/68.jpg)
A-68 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Vending Machine State Table and State Assignment
![Page 69: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/69.jpg)
A-69 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
PLA Vending Machine Controller
![Page 70: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/70.jpg)
A-70 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Moore Counter• Mealy Model: Outputs are functions of Inputs and Present State.
• Previous FSM designs were Mealy Machines, in which next state was computed from present state and inputs.
• Moore Model: Outputs are functions of Present State only.
![Page 71: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/71.jpg)
A-71 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Four-Bit Register• Makes use of tri-state buffers so that multiple registers can gang their outputs to common output lines.
![Page 72: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/72.jpg)
A-72 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Left-Right Shift
Register with
Parallel Read and
Write
![Page 73: Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic](https://reader035.vdocuments.us/reader035/viewer/2022062801/56814457550346895db0f256/html5/thumbnails/73.jpg)
A-73 Appendix A - Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Modulo-8 Counter• Note the use of the T flip-flops, implemented as J-K’s. They are used to toggle the input of the next flip-flop when its output is 1.