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Primace 4.0 User Guide

Capital Microelectronics Co., Ltd.

Capital Micro ii

The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Capital Microelectronics, Co., Ltd. reserves the right to discontinue or make changes, without prior notice, to any products herein to improve reliability, function, or design. Capital Microelectronics, Co., Ltd. advises its customers to obtain the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current.

Copyright © 2010-2012 Capital Microelectronics, Co., Ltd. All rights reserved. No part of this document may be copied, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the written permission of Capital Microelectronics, Co., Ltd. All trademarks are the property of their respective companies.

1 Capital Micro

Table of Contents

Primace 4.0 Overview ........................................................................................................ 4 Introduction .................................................................................................................... 4

Start Primace ............................................................................................................. 4 Customizing Environment .............................................................................................. 4

EDA Tools Page......................................................................................................... 5 External Editors .......................................................................................................... 5 Text Editor Page ........................................................................................................ 5 I/O Editor Page........................................................................................................... 5 Netlist Viewer Page .................................................................................................... 5

Supported Devices......................................................................................................... 6 System Requirements, Licensing & Technical Support ................................................ 7

System Requirements ................................................................................................ 7 Installing ..................................................................................................................... 7 Uninstalling ................................................................................................................. 7 Getting Technical Support ......................................................................................... 8 Getting Online Help .................................................................................................... 8 Other Primace 4.0 Software Documentation ............................................................. 8

Design Flow ........................................................................................................................ 9 Introduction .................................................................................................................... 9 Graphical User Interface Design Flow ........................................................................... 9 Command-Line Executables........................................................................................ 12

Using Standard Command-Line Commands ........................................................... 13 Design Entry ..................................................................................................................... 14

Project .......................................................................................................................... 14 Creating a Project .................................................................................................... 14 Project Management ................................................................................................ 15

Creating a Design ........................................................................................................ 17 Using the Primace Text Editor ................................................................................. 17 Specifying Working Environment of Text Editor ...................................................... 18

Wizard Manager ........................................................................................................... 21 Opening Wizard Manager ........................................................................................ 21 Clock Switch ............................................................................................................. 22 Oscillator .................................................................................................................. 22 PLL ........................................................................................................................... 23 EMB.......................................................................................................................... 26 MAC ......................................................................................................................... 28 8051 ......................................................................................................................... 30 SRAM ....................................................................................................................... 32

Constraint Entry ........................................................................................................... 34 I/O Editor .................................................................................................................. 34 The Options Dialog Box ........................................................................................... 37

Synthesis .......................................................................................................................... 39 Introduction .................................................................................................................. 39 Using Primace Synthesis ............................................................................................. 39

Synthesis Options .................................................................................................... 39 Analyzing Synthesis Results ........................................................................................ 41

Primace User Guide

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Placement and Routing ................................................................................................... 42 Introduction .................................................................................................................. 42 Using Primace P/R ....................................................................................................... 42

Placement and Routing options ............................................................................... 43 Analyzing P/R Results ................................................................................................. 44 Optimizing the P/R ....................................................................................................... 44

Using manual placement in Chip Editor .................................................................. 44 Timing Analysis ............................................................................................................... 45

Introduction .................................................................................................................. 45 Static Timing Analysis (STA) ....................................................................................... 45 Run Primace Timing Analysis ...................................................................................... 52

Viewing Timing Report ............................................................................................. 52 Viewing Timing Delays with Netlist Viewer .............................................................. 53 Viewing Timing Delays with Chip Editor .................................................................. 54

Bitstream Generation and Download ............................................................................ 55 Introduction .................................................................................................................. 55 Generating bit stream file ............................................................................................. 55

Bitgen options .......................................................................................................... 55 Downloading ................................................................................................................ 56

Debugging and Optimization .......................................................................................... 59 Introduction .................................................................................................................. 59 Console window ........................................................................................................... 59 Design Report .............................................................................................................. 59 Netlist Viewer ............................................................................................................... 60

Viewing Netlist in Single/Multiple page mode .......................................................... 62 Viewing Property of Cells (Instance, net or port) ..................................................... 62 Using Goto to Reach a Specified Page ................................................................... 62 Searching Resources you need ............................................................................... 62 Filtering and Tracing Nets ........................................................................................ 63 Showing a Critical Path ............................................................................................ 65 Specifying Options of Netlist Viewer ........................................................................ 65

Chip Editor ................................................................................................................... 65 Opening Chip Editor ................................................................................................. 66 Displaying chip resources ........................................................................................ 66 Identifying Delays & Critical Paths ........................................................................... 68 Manual placement .................................................................................................... 68

Cross Probing .............................................................................................................. 69 Locate port ............................................................................................................... 70 Locate Net ................................................................................................................ 70 Locate Instance ........................................................................................................ 71

Signal monitor .............................................................................................................. 71 Flow .......................................................................................................................... 71 Configuring Monitored Signals ................................................................................. 72 Creating Signal Monitor Profile ................................................................................ 73

Using Keil Debugger .................................................................................................... 73 EDA Tool Support ............................................................................................................ 74

Introduction .................................................................................................................. 74 EDA Simulation Tools .................................................................................................. 74

Configure Modelsim Environment............................................................................ 74

Welcome to the Primace User's Guide

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Logic Simulation ....................................................................................................... 75 Appendix I: Design Example .......................................................................................... 76

Preparing for this Lesson ............................................................................................. 76 Create a Project ........................................................................................................... 76 Create design files with Text Editor ............................................................................. 77 Define System with Wizard Manager .......................................................................... 77 Make an Embedded System Design ........................................................................... 78 Specify initial design constraints .................................................................................. 78 Run Synthesis .............................................................................................................. 78 Perform a functional simulation with an EDA simulation tool. ..................................... 79 Assign I/Os in I/O Editor .............................................................................................. 79 Place/Route the design and Analyze result ................................................................. 80 Perform timing simulation ............................................................................................ 81 Analyze the timing ........................................................................................................ 81 Debugging and Optimizing .......................................................................................... 81 Create programming files and program the device ..................................................... 81 Keil Debug.................................................................................................................... 81

Documentation Conventions .......................................................................................... 83 Typographic Conventions ............................................................................................ 83

4 Capital Micro

User Guide Chapter 2 Chapter 1

Primace 4.0 Overview

Introduction Primace 4.0 provides powerful and flexible EDA tools to support the whole process of CAP

（Configurable Application Platform on chip）system design and the FPGA design.

Primace offers a variety of Intellectual Property (IP) cores. Those IP cores assist users to carry

out different applications in distinctive fields as well as accelerate the release of products.

Furthermore, Primace also supports third-party design tools with friendly and easy-to-use

Graphic User Interface (GUI).

Start Primace

Use one of the following ways to start Primace:

• Double click the Primace 4.0 icon on your desktop.

• Click Start > All Programs > Capital Micro > Primace 4.0 Beta2 > primace.

Customizing Environment Open the Options Dialog by clicking Tools > Options to customize the Primace Environment.

The Options Dialog shows as follows:


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EDA Tools Page

The EDA Tools Page is offered to help users to configure third-party EDA tools like Modelsim for

simulation or Prime Time for timing analysis. For further details, see EDA Tool Support.

External Editors

This page is offered to load external editors. Primace 4.0 not only supports external editors, but

also has the function to name external editors.

Text Editor Page

Text Editor is a tool used to view, create or modify text-based designs. You can pre-define its

working environment so that you can work with it in your favorite mode. Options of Primace

provide you with text editor to work faster and conveniently and save time on designing. For

future details, see

I/O Editor Page

Using the Primace Text Editor.

I/O Editor is a tool used to assign I/O signals (ports) to I/O pins on Capital Micro device. It

offers different choices for color defining of different pins. For more details, see I/O Editor.

Netlist Viewer Page


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Netlist Viewer provides different levels schematic view of your design and a hierarchy list, which

lists the instances, pins, and nets for the entire design netlist. It can help you check the errors

of your design. This page offers choices for netlist display. Port names, pin names, instance

names, and other choices are available. Please refer to Netlist Viewer for further details.

Supported Devices Devices in the following table are supported by Primace 4.0. Please refer to datasheet for further

details.

Product Device Name

CME3000

CME3C06-L144

CME3C06N-L144

CME3C06-T100

CME3C06N-T100

CME3C03-L144

CME3C03N-L144

CME3C03-T100

CME3C03N-T100

CME3P06-L144

CME3P06N-L144

CME3P06-T100

CME3P06N-T100

CME3P03-L144

CME3P03N-L144

CME3P03-T100

CME3P03N-T100


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CME3M06-L144

CME3M06N-L144

CME3M06-T100

CME3M06N-T100

CME3M03-L144

CME3M03N-L144

CME3M03-T100

CME3M03N-T100

System Requirements, Licensing & Technical Support System Requirements

The following table shows the basic system requirements for installing Primace 4.0. Check your

system to make sure that all the minimum requirements have been met before installation.

Operating System Service Pack Memory Disk Display

Windows XP

Professional SP2 1G 150M

1280 X 1024

pixels

Windows XP Home SP3 1G 150M 1280 X 1024

pixels

Windows 2000 SP4 KB884016 (Windows Installer

3.0) or higher 1G 150M

1280 X 1024

pixels

Windows Vista 1G 150M 1280 X 1024

pixels

Windows 7 1G 150M 1280 X 1024

pixels

Installing

Double-click Primace 4.0_setup.exe on Primace CD, and use the installation wizard to

complete installation.

Uninstalling


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Primace can be uninstalled with one of the following ways:

• Click Start > All Programs > Capital Micro > Primace 4.0> Uninstall Primace

• From Control Panel, open Add/Remove Programs, and then select Primace to

remove it.

Getting Technical Support

If you have trouble with running Primace or encounter problems during design process, you may

take the following steps to troubleshoot it yourself first:

1. Check whether the system running on Primace meets the System Requirements,

Licensing & Technical Support.

2. Check the configuration of your design compilation. Make sure all the settings are

allowed. For more information, see The Options Dialog Box.

If the problem still persists, you can report it to Capital Micro Support (support@capital-

micro.com) with the following information:

• Describe the precise steps leading to the problem.

• Send us the log file (agateflow.log), which is located in the outputs folder of your

project.

• Send us the design file you are working with if necessary. In order to solve the technical

issues that you have reported, we need to reproduce your working environment so that

we can recreate and analyze the problem.

Getting Online Help

Primace 4.0 includes a browser-based Help system that provides help documentation for

Primace 4.0 software. You can view Help by clicking Help->Help menu of Primace

Other Primace 4.0 Software Documentation

Primace 4.0 Tutorial, you can find it in Doc folder of Primace CD.

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User Guide Chapter 2

Design Flow

Introduction Primace 4.0 provides a complete design environment for CME CAP design. You can control the

whole design flow by graphical user interface or command-line interface.

Primace 4.0 Design Flow

Third-party Tool-Keil

Design Entry

Synthesis

Place & Route

Timing Analysis

Bit stream Generation

Debugging & Optimization Embedded System

Design

Debugger Driver Plugged-in

Third-party Tool Simulation

Includes FPGA design ,8051 MCU design

Download

Notes:

stands for Primace tools and flows;

stands for third-party tool.

Primace software allows you to use the graphical user interface and command-line interface of

the design flow. You can use either of them for the entire flow, or you can use different options

at different phases.

Graphical User Interface Design Flow The following figure shows Primace 4.0 Graphical User Interface.

Design Flow

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In Primace 4.0 software, we offer a modular Compiler which is composed of 5 steps:

■ Synthesis

■ Placement

■ Routing

■ Bitstream Generation

■ Static Timing Analysis

You can run the whole flow by clicking Flow > Run Project, or run each flow step by step from

Flow menu.

The following steps describe the basic design flow using the Primace 4.0 GUI

1. To create a new project and specify a target device, click Project > New Project.

For further details, refer to Creating a project.

2. Use the Text Editor to create source files, both VHDL and Verilog HDL is supported. Then add

the created source file into the project, or add exiting source files into the project.

For further details, refer to Creating a Design.

3. Use the Wizard Manager to generate and instantiate IP cores (such as 8051, EMB, MAC and

etc.).

For further details, refer to Wizard Manager.

4. Specify initial design constraints with the Settings dialog box, including Project settings and

EDA tools.

For further details, refer to The Options Dialog Box.

Design Flow

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5. Synthesize the design by clicking Flow-> Run Synthesis, analyze result with netlist viewer.

For further details, refer to Synthesis.

6. Perform a functional simulation with third-party simulation tool.

For further details, refer to EDA Simulation Tools.

7. Assign I/Os in the I/O Editor.

For further details, refer to I/O Editor.

8. Run Placement by clicking Flow-> Run Placement and Routing by clicking Flow-> Run

Routing, analyze the result from design reports and log files.

For further details, refer to Placement and Routing.

9. Analyze the timing by clicking Flow-> Run Timing Analysis.

For further details, refer to Timing Analysis.

10. (Optional) Use an EDA simulation tool to perform timing simulation for the design, and

debug the design with Netlist Viewer, Signal Monitor tool and Debugware too.

For further details, refer to EDA Simulation Tools and Debugging and Optimization.

11. (Optional) Adjust P/R optimization options in Options dialog box and do manual placement

in the Chip Editor to correct timing problems.

For further details, refer to P/R Options.

12. Create programmable bitstream files for the design by clicking Flow-> Run Bitgen, then

program the device by clicking Tools -> Downloader.

For the details, refer toBitstream Generation and Download.

13. Debug 8051 with Keil.

For further details, refer to Downloading.

Design Flow

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Command-Line Executables Primace 4.0 includes separate executables for each stage of the design flow. You can use these

executables with standard command-line commands. The following figure shows the available

command-line executables.

Command-Line Design Flow

Synthesis

Placement agp

Routing agrtr

Bitstream Generation abcgen-acfgen

Timing Analyzer agtc-cstimer

Programmer agdl

Verilog Design File (.v) VHDL design file (.vhd)

? (.amv) annotation file

Post-placement netlist (.apv) annotation file (.apa)

Post-routing netlist (.arv) annotation file (.ara)

Bitstream file (.acf) Timing report file (.trpt)

Table 1 Command-Line Executables

Executable Name

Title Function

ast Synthesis Synthesizes a design. Prepare the project and design files before running synthesis.

agv2aoc Constrain generator

Create the CME constraint file. Synthesis must be successfully run before running

agv2aoc.

agp Placement Places a design. Synthesis must be run successfully before running the Placement.

agrtr Routing Routs a design. Placement must be run successfully before running the Routing.

agtc

cstimer

Timing Analyzer Perform static timing analysis of the design using constraints entered in Synopsys

Design Constraint format.

abcgen

acfgen

Bitstream generator

Create a programming file for programming the target device. The Routing must be run successfully before running the Bitstream

generation.

agdl Programmer Program the target device.

Design Flow

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Using Standard Command-Line Commands

Using command-lines is another method to run flows. And this method can help you control

Primace to run a flow flexibly. You can either click Start > All Programs > Capital Micro >

Primace 4.0 > Command Line or click Tools > Command-Line Window to launch it.

For more details, refer to man pages in CD:/ Primace 4.0/ Primace 4.0/ man.

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Design Entry

Primace 4.0 project includes all of the design files, software source files, and other related files

necessary for the eventual implementation of a design in a programmable logic device. You can

use Text Editor, Wizard Manager, and third-party design entry tools to create design files that

include CME intellectual property (IP) functions.

The figure of Design Entry Flow is shown as below.

Text EditorCME IP design files generated by Wizards (.v, .vhd)

Verilog HDL ＆ VHDL　design files (.v, vhd)

Wizard Manager

Third-party Editors

Design files generated by third-party editors (.v, .vhd)

To Primace Synthesis tool

To third-party Syntheis tool

Project

Creating a Project

To create a project, click Project > New Project on the menu bar or on the toolbar.

In the New Project Dialog, you can choose the project directory, input the project name and top

module name. Also choose the HDL type of your project which both Verilog HDL and VHDL is

supported and select a device for your project.

Design Flow

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Notes: For the project directory, a path with Space like “C:\My Documents\workspace” is not

supported.

Project Management

Project Settings Specification

After a project is created, you can manage the project options with the Project Settings dialog

shown in following figure. You can use one of the following ways to open Project Settings dialog

box:

• Click on the toolbar.

• Click Project > Project Settings on the menu bar.

• Click Tools > Options on the menu bar.

On the General page of Options dialog box, top module of the current project, target device and

language and include file path are shown as well as changeable.

Note: We suggest users not put your files under outputs directory at the current step,

accidental deletion may happen when cleaning flow results.

Set Top Module

If you want to set a module as top module of a project, you can do it in two ways as follow:

• “Set As Top Module” menu

Synthesis

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In Project Explore Window, select the module you want and right click; you can see a

Set As Top Module dialog box menu，choose Set As Top Module.

• “Options” Dialog

Click Tools in Menu bar > Options> Project, you can input Top Module Name, case

sensitive.

Importing/Exporting Files

The importing and exporting functions are offered to you for importing files generated by third-

party tools or other projects and exporting files from current projects.

To import files,

1. Click Tools > Import Files on the menu bar to open Import Files dialog box. See

the dialog box below:

To export files,

1. Click Tools > Export Files on the menu bar to open Export Files dialog box.

Design Flow

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Creating a Design You can create designs in Primace 4.0 Text Editor. Primace 4.0 also supports designs created

from files generated by third-party EDA design entry. For more information on using EDA

synthesis tools to generate Files, see EDA Tool Support.

Using the Primace Text Editor

Text Editor is a text-based tool which is used to view, create, and edit designs in Verilog HDL or

VHDL. Also it can view output files generated by Primace.

Text Editor also allows you to create and edit a template for Verilog, VHDL, Make file, XML, sdc,

and C, export the template and insert it into the current file.

To create a design in Text Editor:

Method 1:

Select the project in Project Explorer and right-click, select Add New File. The file can be

automatically added into the project as source file. You can create design in Verilog HDL or

VHDL in Text Editor.

Synthesis

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Method 2:

1. Click File > New Text File on the menu bar, or to bring out the Text Editor.

2. Enter source code in Text Editor.

3. Click File > Save to save the file in Verilog HDL.

4. Click Flow > Check Syntax to be sure there is no syntax errors.

5. Add the design file to the project: select the project name in Project Explorer and

right-click, select Add Existing File.

To use existing design files

If design files generated by third-party tools need to be used as source file in the project, or you

want to use existing design files created before, you can choose one of the following methods:

Method 1: add these design files into the project by clicking Add Existing File.

1. Select the project name in Project Explorer and right-click, select Add Existing File.

2. In Open Files dialog box, browse and select the file you want to add, and then click

Open to add the existing file.

In fact, the file you add as an existing file will still be saved in its current path instead of copied

to the src path of the project. This makes easier to share files between different projects or

tools. If you want to move these files to the project src path, you can copy these files to the

project src path first, then add them into the project, or you can import files by clicking

Tools>Import Files menu.

Method 2: Import source file

For the details, please refer to Importing/Exporting Files.

Specifying Working Environment of Text Editor

When you create a design using text editor, you can customize your own working environment

of text editor. Click Tools > Options on the menu bar, and click Text Editor on the left list. See

the figure as follow.

Design Flow

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• Fonts and Colors

Font and color shown in text editor can be defined in this page. Font sample is visible in

whitespace while setting.

• Templates List

You can choose to comprehend or edit templates written in a certain languages here.

Certain default templates written in Verilog HDL are available to use.

Synthesis

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Design Flow

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Wizard Manager Wizard Manager offers a friendly graphic user interface to use complex high level embedded IP

cores. With Wizard Manager, you can create and modify an IP core design and instantiate it with

custom parameters and variations.

Reference: The related device datasheet offers you detailed messages about IP cores, so make

sure you have read it and acquired information about the properties of IP cores before

customizing.

Opening Wizard Manager

1. Click Tools > Wizard Manager on the menu bar, or directly click on the toolbar.

2. A Wizard Manager dialog box appears. You can select to create a new design or edit an

existing design shown as the following figure.

3. After your selection, click Next button to continue following steps. You can see the

second page of Wizard Manager.

Synthesis

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You can choose which IP core to create in this dialog. So far, Primace 4.0 supported Clock

Switch, GBufGate, Oscillator, PLL, Debugware, EMB, MAC and 8051.

Clock Switch

Clock Switch core is used to instantiate CFG_DYN_SWITCH of the CME3000 devices. After

choosing Clock Switch, page 1 is shown as follows:

Take the following steps to customize GCLKCtrl Switch core:

1. Specify a name in Module name box, and select a directory to save output files. The

default directory is the src folder in the current project, or you can browse to any folder to

save files. Then click Next.

2. Specify initial Gclk input port and Gclk dynamic Mux.

3. Click Finish to generate design file.

Oscillator

Design Flow

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Oscillator is used to instantiate the oscillator of the CME3000 devices. After choosing OSC, page

1 is shown as Figure 1.

Take the following steps to customize the oscillator:




Figure 1

2. Choose Oscillator type.

3. Click Finish to end the configuration.

PLL

Synthesis

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PLL core is used to instantiate the PLLs of the CME3000 devices. After choosing PLL, page 1 is

shown as Figure2.

Take the following steps to customize PLL core:




Figure 2

2. Page 2 shows the general settings.

- Specify clkin’s frequency ranges from 5~472.5 MHz and band width, default

frequency is set as 100 MHz.

- Create an “fbclkin” input (External Feedback Mode), default is no.

- Specify output ports. Bypass is optional. Create “locked” output

- Set power mode:

"always on” - power is always on “always off" - no power “FP” – use FPGA to control the power “MCU” – use MCU to control the power

Design Flow

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Figure 3

3. Page 3, set output clock parameters. Primace 4.0 supports input expected values of

frequency directly, and calculate the actual values with parameters configuration of output

frequency.

Synthesis

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4. Page 4, set the phase shift and delay of VCC and output ports.

Figure 4

EMB

EMB is used to instantiate the EMB5K of the CME3000 devices. After choosing EMB, page 1 is

shown as Figure 5.

Take the following steps to customize EMB core:




2. Select EMB type and then click Next.

- If EMB is customized as single port, only one port is supposed to be configured;

- If EMB is customized as simple dual port, set data width and memory depth of

read port. Click next, specify data width, memory depth and operation mode of

write port;

- If EMB is customized as true dual port, set data width, memory depth and

operation mode of both read and write port;

3. If EMB is customized as ROM, browse the .dat file location to choose a file to initialize the

EMB.

4. Click Finish to generate design file.

Design Flow

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Figure 5 Page 1 of EMB

Figure 6 customized as simple dual port schematic diagram

Synthesis

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Figure 7 configure true dual port schematic diagram

MAC

MAC is used to instantiate the MACs of the CME3000 devices. After choosing MAC, page 1 is

shown as Figure 8.

Take the following steps to customize MAC core:




Figure 8

Design Flow

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2. Specify input type, there are 2 options, signed and unsigned. Set both X and Y input width

and mode, there are two options, bypass and register. Z input width and mode is

configurable only if adder or osload are checked.

Figure 9 Choose data width page

Figure 10 adder is checked

Synthesis

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Figure 11 sload is checked

Figure 12 sload and accumulator are checked

8051

8051 is used to instantiate the 8051 MCU of the CME3000 devices. After choosing 8051, page 1

is shown as Figure 13.

Take the following steps to customize 8051 core:




Design Flow

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Figure 13 8051 instantiation page1

2. Choose ports you want to use. If external memory ports are selected, Figure 15 will show

for you to specify synchronous mode.


Synthesis

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SRAM

SRAM is used to instantiate the embedded single port SRAM of the CME3000 M series devices.

After choosing SRAM, page 1 is shown as Figure 15.

Take the following steps to customize SRAM core:




Design Flow

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Figure 17 SRAM instantiation page1

2. Choose Data Width you want to select. There are two types: 8 bit or 16 bit for SRAM data

bus. The addr bus width will be 16 when the Data Width is 16 while the addr bus width

will be 17 when the Data Width is 8. The ‘CEN’ is SRAM select signal and the ‘WEN’ is write

enable signal, the both ports are active low. The data on the datai bus will be written to

SRAM on the posedge ‘clk’ when the ‘CEN’ and ‘WEN’ are both low. The datao will output

the SRAM memory content on the posedge ‘clk’ when the ‘CEN’ is low and ‘WEN’ is high.

Figure 18 SRAM instantiation page2

Synthesis

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Constraint Entry During you run flows for the design, you can use the I/O Editor and the option dialog box to

specify design constraints, such as device options, logic flow options, physical flow options, IO

assignments and timing constraints.

The figure of Constraint Entry Flow is shown as below.

Setting Dialog Box

IO Editor

Primace Project File(.apj)

Synopsis Design Constraint file(.sdc)

Constraint file(.aoc)

To Primace flows

I/O Editor

I/O Editor is a tool used to assign I/O signals (ports) to I/O pins on Capital Micro devices. You

can assign all ports to those available pins and modify I/O attributes respectively.

Primace 4.0 provides graphical view and table view to do I/O assignment. The graphical view

shows you a rough image of chip and its pin arrangement. You can drag unassigned ports to

pins with your mouse. The table view shows you port names, location (which pin this port

assigned on), and other I/O attributes. You can specify a location for a port and modify relative

I/O constraint attributes to meet your requirements. In table view, you can directly input pin

number in corresponding location column to distribute unassigned ports.

Opening I/O Editor

Click Tools > I/O Editor on the menu bar, or directly click on the toolbar.

Assigning I/O

There are two methods to assign I/O: Graphical Mode and Table Mode.

Graphical Mode

Take the following steps to assign a port to a pin:

1. Open the I/O Editor by clicking Tools > IO Editor on the menu bar.

Design Flow

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2. In graphical mode, select a port in Unassigned Ports panel, hold your mouse and

drag it to the pin location you want.

There are 8 buttons in the toolbar to modify IO Editor, listed in follow table:

Icon Function

Zoom In

Zoom Out

Auto Fill I/O Locations

Bottom/Top View

Bird’s-eye View

Drag to Zoom In

Hand Tool

Fit to Window

Legends

Synthesis

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All the pins which can be assigned are marked in white background, while assigned pins

are marked in red. Other colors shown in the legend indicate they are system-assigned

and also available for users to utilize.

Notes:

You can also simply press F3 to use the function of “Find next”. Left-click the mouse, roll the scrolling

wheel of the mouse, and at the same time press Ctrl, you can change the height and length of your

view.

3. The pin turns red, showing the assignment is successful. And you can find the port in

Assigned Signals panel.

4. Click the Save button.

After assigning a port, you can click on the port in Assigned Ports panel to locate it, and if doing

so, the relevant pin location in the graphical view window will be highlighted.

Table Mode

You can also use this table view to do I/O assignment. The table lists all the I/O attributes and

you can modify them according to your need. At the same time, you can customize the columns

which show I/O attributes to hide some useless columns or show useful ones.

Un-assigning I/O

To Un-assign I/O, use one of the following ways:

• Select the assigned pin(s) in the table view and press Delete key.

• Drag the selected port in Assigned Signals panel to the Unassigned Signals panel, and

drop it there.

• Select a pin in red in the Assigned Ports panel, press delete key.

Reassigning I/O

To reassign I/O, follow the two steps below:

• Un-assigning I/O, more details please refer to Un-assigning I/O.

• Assigning I/O, more details please refer to Assigning I/O.

Configuring I/O Properties

IO properties can help reserve I/O for monitored signal：

Design Flow

Capital Micro 37

1. Choose a spare I/O you want to reserve;

2. Double-click the I/O you aim to reserve or right-click it and click Property; then Pin

Property dialog box pops up;

3. Check out Reserved IO checkbox and click OK.

The Options Dialog Box

You can use the Options dialog box to specify general project settings and synthesis, P/R,

bitstream, timing analysis and EDA tool settings for a project. Click Tools > Options or directly

click the on the toolbar to open the Options dialog box.

Specify project settings

In the General page of Options dialog box, you can view or change top module of the current

project, target device and include file path. See the dialog box below.

Specify Synthesis settings

Synthesis

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In the Logic Flow page, you can specify different synthesis options. For further details, refer to

Synthesis Options.

Specify P/R settings

In the Physical Flow page, you can specify different P/R options. For further details, refer to

Setting P/R Options.

Specify Bitstream settings

In the Physical Flow page, you can specify Bitstream options. For further details, refer to BitGen

Options.

Specify Timing Constraints

In the Timing Constraint page, you can specify different timing constraints. For further details,

refer to Static Timing Analysis.

Design Flow

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Synthesis

Introduction After you create a project and design files, you need to synthesize your design. Synthesis

translates a use RTL to a post-mapping netlist.

Figure of Synthesis Flow.

Synthesis ast

Verilog design files (.v) VHDL design files ( vhd) Post-map netlist (.amv)

Primitive libraries

to Placement

Netlist viewer

Design EntryConstraint

Report file (.rpt)

Using Primace Synthesis CME synthesis supports both Verilog HDL and VHDL. You can specify which language and

standard to use in Project page of Options window. CME synthesis uses Verilog HDL as default.

You can run CME Synthesis separately by clicking Flow > Run Synthesis or you can run the

whole design flow which includes Synthesis by clicking Flow > Run Project.

Synthesis Options

The Logic Flow page in the Settings dialog box allows you to specify netlist optimization options.

Synthesis

Capital Micro 40

The following are details about synthesis options:

Enable RAM Extraction

CME Synthesis will auto infer memory which match particular pattern in user RTL to EMB5K on

CME Chips if checked.

Enable MAC Extraction

CME Synthesis will auto infer Multiplier and Macs which match particular pattern in user RTL to

MAC on CME Chips if checked.

Enable Advanced Timing Optimization

CME Synthesis will use advanced timing optimization strategies to get a better timing

performance if checked.

By clicking Advance button in the Logic Flow page, you can open the Synthesis Advance Setting

dialog box.

Design Flow

Capital Micro 41

The following are details about advance synthesis options:

RAM Extraction

Define the minimum address width of memory which auto infer to EMB5K cells.

MAC Extraction

Define the minimum operator width of Multiplier and Mac which auto infer to MAC cells.

Enable Carry Chain Optimization

CME Synthesis will use Carry Chain Optimization strategies if checked.

Enable Collapse Constant Adder

CME Synthesis will collapse the constant adder in user RTL if checked.

Enable Collapse Constant Comparator

CME Synthesis will collapse the constant comparator in user RTL if checked.

The minimal collapse adder width

Define the minimum operator width of Adder which is collapsed.

Analyzing Synthesis Results Primace provides the following three methods to analyzing synthesis results: Message Window,

Synthesis Report and Netlist viewer.

For further details, refer to Debugging and Optimization.

Synthesis

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Placement and Routing

Introduction As the first step in physical design process, the task of placement is to calculate the positions of

the cells. Then the routing process assign signals to routing resources in order to successfully

route all signals while achieving a given overall performance.

Primace Placement takes a post-mapping netlist (.amv), a constraint file (.aoc) and libraries as

input, to determine the legal location of each element in the mapped netlist. It takes different

constraints (IO distribution, logic cell structures, clock/non-clock interconnects, resource

capacity and special macro blocks) in CME FPGAs into account. The output is a post-placement

netlist file (.apv), a netlist annotation file (.apx) and an annotated AOC file if using manual

placement.

Primace Routing tool takes a post-placement netlist (.apv) and a netlist annotation file (.apx) as

input, to connect all signal paths using the available programmable interconnects on-chip. The

output is a post-routing netlist annotation file (.ara) and an annotated aoc file if using manual

placement.

The figure, Place and Route Design Flow is shown as below.

Placement agp

Post-map netlist (.amv)

Post-placement netlist (.apv)

libraries

to Bitstream generation, Timing Analysis,Netlist Viewer

Report file (.rpt)

Routing agrtr

from Synthesis

from Design Entry

Post-routing netlist (.arv)

Placement Drc Routing Drc

Report file (.rpt)

to Netlist Viewer

libraries

If you have made IO assignments or manual placement in your design, the P/R attempts to

match those resource assignments with the resources on the device, tries to meet any other

constraints you have set, and then attempts to optimize the remaining logic in the design. If you

have not set any constraints on the design, the P/R automatically optimizes it. If it cannot find a

resolution, the P/R terminates compilation and issues an error message.

Using Primace P/R Before running Placement, you must run synthesis successfully. You can run CME Placement and

Routing separately by clicking Flow > Run Placement and Flows > Run Routing or you can

run the whole design flow which includes Synthesis by clicking Flow > Run Project.

Design Flow

Capital Micro 43

If you make changes to the design or design settings as needed, you need to run P/R again. For

information about running a whole flow, refer to chapter 2 on page 9 “Graphical User Interface

Design Flow”.

You can also use Command lines to run P/R. For details, please refer to Placement and Routing

man pages.

Placement and Routing options

The Physical Flow page in the Settings dialog box allows you to specify netlist optimization

options.

The following are details about P/R options:

Optimize Post Placement

When this option is checked, placer would repack LUTs and REGs automatically to optimize

placement.

Effort

There are three effort levels available: low, standard, and high. Default effort level is standard.

Higher effort level takes more time to complete placement, but in general would produce better

result in terms of both routability and timing. On the average, one higher level of effort would

take about twice longer time to complete the flow compared with a lower level.

Mode

Synthesis

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There are two options—area and timing—to let you choose which method you want to use for

placer. Area aims at guaranteeing the success of placer as much as possible. The function of

Timing is to achieve better timing performance by getting a compromise with routability.

Random Seed

Define the random seed number Primace Placement using. User can modify this value to get a

different P/R result.

Analyzing P/R Results Primace provides the following three methods to analyzing P/R results: Message Window, P/R

Report and Netlist viewer.

If necessary, you can use Chip Editor to view P/R results and make adjustments.

For further details, refer to Debugging and Optimization.

Optimizing the P/R Once you have run the P/R and have analyzed the results, you can try several options to

optimize the result:

■ Using manual placement in Chip Editor

■ Setting options that control place and route

Using manual placement in Chip Editor

Manual placement is used to optimize P/R after running the whole flow. With manual placement,

you can directly drag the resource assignment to the aim LUT or REG. After that, run placement

again to check the result. For more detail, refer to Debugging and Optimization.

45 Capital Micro


Timing Analysis

Introduction Static Timing Analysis allows you to analyze the timing characteristics of your design. You can

use the information generated by the timing analyzer to analyze, debug, and validate the timing

performance of your design.

Static Timing Analysis (STA) Primace has 2 tools to do static timing analysis, Cswitch Timing Analysis and Prime Time.

Cswitch is CME self-owned tool, once specified, you can directly use it. Prime Time is a third-

party tool that users are supposed to install it before doing analysis

Before running Timing Analysis, you are supposed to specify a Capital Micro Timing Analysis tool

and timing constraints.

To configure Capital Micro Timing Analysis,

1. Click Tools > Options on the menu bar to open Options dialog box.

2. On the EDA Tools page, choose Capital Micro Timing Analysis tool box.

To configure Timing Constraint,

1. Click Tools > Options on the menu bar.

2. Choose Timing Constraint on the left menu bar.

Timing Analysis

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3. Set parameters in Delay Type and Delay Requirements.

Delay Type includes max, min and typical. And Primace 4.0 sets typical as a default value.

tsu: Input pin setup time

th: Input pin hold time

tco: clock to output delay

tpd: pin-to-pin delay

In order to add a clock, click Clock in the dropdown list of Timing Constraint.

You need to click on and then you see the following image in the clock box:

Timing Analysis

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Click on 100 MHz to change the frequency value. Then click on the blank spot after 100 MHz,

a flashing cursor will turn up.

You can either type the name of clock port or click to choose the clock ports you want

from the dialogue box above:

Note: If the same clock is assigned two frequency values in the clock setting box, the system will

always choose the latter value listed in the box.

Apply on box in the Clock Settings. Two types of ports are available for a clock node.

1) External ports. Directly type the names of those ports;

2) PLL output ports. Type in the following format: hierarchical instance name. output pin.

4. Add clk.

5. Click OK. Clock constraint is shown in the following figure.

Timing Analysis

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To edit Sdc Commands

1. Click Sdc Commands choice in the dropdown list of Timing Constraint,

2. Click . Choose either set_false_path, set_multicycle_path, or create_clock

to use UI template. Inputting other sdc is Ok, but no UI template is to be provided.

Timing Analysis

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False paths mean that the paths which pass from, to, through nodes do not need analysis.

To add a false path, click . A Set False Path dialogue box appears.

Click to choose the nodes you want. A Find Nodes dialogue box turns out.

Click , available ports will be listed in Port Category. Choose nodes.

Timing Analysis

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Command aims at fetch the sdc command of that node. And then choose the type of that

node in the Category. Use Filter to enter keyword which describes the nodes you want to

find. When the editing is done, click OK.

To add a multi cycle path, click . A Set Multicycle Path dialogue box appears.

Timing Analysis

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Choose nodes which you want to use by clicking button. A Finding Nodes dialogue

box turns out.

Command aims at fetch the sdc command of that node. And then choose the type of that

node in the Category. Use Filter to enter keyword which describes the nodes you want to

find. When the editing is done, click OK.

And then set up Delay Type, Analysis Type, Reference Clock, and Value on the Set

Multicycle Path dialogue box.

3. To import an Sdc command file, click to do it. The gray part contains the sdc

commands which will be definitely used in user’s design.

Primace also allows using a third-party timing analysis tool Prime Time to do static timing

analysis. Before running Timing Analysis, you need to configure Prime Time and timing

constraints.

To configure Prime Time,

1. Click Tools > Options on the menu bar to open Options dialog box.

2. On the EDA Tools page, choose Prime Time in Timing Analysis Tool box.

3. In the Server Settings box, type server name and user name.

Timing Analysis

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4. Click OK.

To configure Timing Constraint,

1. Click Tools > Options on the menu bar.

2. In the Timing Constraint Page of the Options dialog box, set the parameters to meet your

need.

tsu: setup time

th: hold time

tco: output delay

tpd: pin-to-pin delay

3. Click OK.

Run Primace Timing Analysis After configurations, you can click Flow > Run Timing Analysis on the menu bar to start this

timing analysis step. The Console window will print information provided by Prime Time and a

file named TimingReport.trpt will be generated in outputs folder in the project directory,

containing the analysis' result.

Viewing Timing Report

The result timing report shows as follows:

Timing Analysis

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The timing report contains: Summary Page, Clock Page, and Path Pages including

tsu/th/tco/tpd/clock setup time/clock hold time. Each path page includes a Path list show in

following figure.

Locate path from timing report to view path information in Chip Editor or Nextlist Viewer。

Viewing Timing Delays with Netlist Viewer

After running timing analysis, you can use the Netlist Viewer to view the nodes that make up a

timing path, including information about total delay and individual node delay. For further

details, refer to Debugging and Optimization.

Timing Analysis

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Viewing Timing Delays with Chip Editor

After running static timing analysis, you can locate critical path from timing report viewer to

Chip Editor. Chip Editor displays the critical path from source node to destination node with

partitioned delays marked. For further details, refer to Debugging and Optimization.

55 Capital Micro


Bitstream Generation and Download

Introduction Bitstream generator generates bitstream files for device programming. Download tool

downloads bitstream files to FPGA configuration memory or SPI flash memory.

Bitstream Generation abcgen

Post-routing netlist (.arv) P/R annotation files (.apa, .ara)

ABC file (.abc)

to Capital Micro chip

Bitstream Generation acfgen

from Routing

from Design Entry

Configuration file (.acf)

Memory mapConstraint file (.aoc)

Download agdl

from MCU design tool

MCU design file (.hex)

Figure 19 Programming Design Flow

Generating bit stream file Before running Placement, you must run P/R successfully. You can run CME Bitgen separately by

clicking Flow > Run Bitgen or you can run the whole design flow which includes Bitgen by

clicking Flow > Run Project.

Bitgen options

The Physical Flow page in the Options dialog box allows you to specify bitgen options.

Bitstream generation and download

Capital Micro 56

The following are details about options on Bitstream page:

Unused IO’s default state

Specify the state for unused I/Os. Default state is Hi-Z.

Encryption Key

Specify download key to protect the bitstream configuration file. If Astro devices and OTP used,

it should be same as Astro Programmer OTP key.

JTAG operation protection

Specify read protection mechanism. If it is marked, users can not read FPGA and only can erase

SPI flash by JTAG.

Downloading After you have successfully compiled a project and generated Capital Micro configuration file

(.acf), you can download the configuration file to device. You need to install USB driver before

you can use it to download. For more information about installing USB driver, see JTAG ICE Use

Guide.

Choose one acf file, which is one of the acf files you just selected, to configure the device.

To download a configuration file to device,

1. Use USB to connect your development board with PC.

Bitstream Generation and Downloading

Capital Micro 57

2. Select Tools > Downloader on the menu bar, the download panel appears like the

figure below. You will see the configuration file's directory, size, and modified date.

If there are target devices detected, turn to step 3 derectly.

If not, click Setting button on the top right.

Suppose you want to use jtag cable directly, just click the check box on the top of

setting panel. Then choose the cable. If no cable available in the drop down list, check

cable connection and clike Detect button.

Something like “Open JTAG cable successful” will show in Console Window .

Click OK button in Connection Setting dialog.

Click Detect Devices in the download panel, the devices connected will show.

Bitstream generation and download

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3. Specify the target device and select the file you want to download and click Program

button on the bottom right corner of download panel to start loading and configure

automatically. During configuration, Program button changes into stop button. Click

stop to stop downloading. And information in the Console window shows the process

of programming.

4. Download process 100% in progress view and “Downloading successful” in Console

Window indicate that program succeeds.

Note:

If an error dialog box pops up or error information shows in Console Window to show program failed ,

we need to check to make sure the USB connects correctly and the setting is right.

59 Capital Micro


Debugging and Optimization

Introduction Primace offers console window, design report, Netlist Viewer, Chip Editor and Cross-probing

feature that enable you to analyze result of EDA flows and identifying timing critical paths, and

provide ways of manual optimization. It also offers Signal monitor feature which allows you to

route user-specified signals to output pins without affecting the existing fitting in a design, so

that you can debug signals without having to recompile the design. Capital Micro offers AGDI

plug-in for Keil µVision software to debug the embedded system design.

Console window Primace provides a message window to monitor the running state of design flow. The 5 sub-

windows of console window include Output, Information, Warning and Error. While flow is

running, all running message are printed to Output window, and warning message to Warning

window, Error message to Error window.

Every tab of the console window can be open or hidden by clicking View > Console on the

menu bar. It is a field to show you the log information of each flow. The log information includes

error log, warnings, progress-related information, and the environments of implementing a

design. You can learn more about your design flow by reading information displayed in the

Console window.

The window contains the following tabs:

Output: display all the output messages of a flow.

Information: general information.

Warning: show warnings about constraints and settings. The flow will not be blocked because

of warnings.

Error: show error messages, such as design errors, setting errors, constraints errors etc.

Design Report Primace generate a step design report while finish a design flow step like synthesis, placement,

routing and timing analyzing. After the whole design flow is done, Primace generate a whole


Capital Micro 60

flow report constructs of one or more above. These Reports contain many sections that can help

you analyze the implementation of your design. A typical design report shows as follows:

Netlist Viewer Netlist Viewer provides different levels schematic view of your design and a hierarchy list, which

lists the instances, pins, and nets for the entire design netlist. It can help you check the errors

of your design.

It consists of three types of viewers: technology mapper viewer, post-placement viewer, and

post-routing viewer. The technology mapper viewer is used to display the schematic of the

synthesized netlist. The post-placement viewer is used to display the schematic of the placed

netlist and the post-routing viewer is used to display the schematic of the routed netlist.


Capital Micro 61

You can run Netlist Viewer by clicking Tools > Netlist Viewer and click on one of the three

viewers.

Netlist viewer has two parts: a hierarchical list and a schematic view window. The hierarchical

list displays the project hierarchy in a tree format, while the schematic view window displays

each element of your designs. These elements include input and output ports, nets, and blocks.

You can click the element through expending and collapsing the hierarchical tree to navigate the

element in schematic view.


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Viewing Netlist in Single/Multiple page mode

A netlist can be showed in only one page or in multiple pages in schematic view window.

Sometimes, you may have a large design, and to view a large netlist in a single page is not as

convenient as you view a small netlist. However, netlist can be partitioned into multiple pages.

And you can switch from the single page mode to multiple page mode by right-clicking

anywhere of the schematic view window, and on the shortcut menu, choose Show Mode >

Multipage Schematics. In the multipage mode, each page is divided according to the number

of instances. You can set how many instances will be shown per page in Options page, or you

can use the default number (30 instances per page). When you change the number of instances

per page, the change applies only when you reopen the netlist viewer.

Viewing Property of Cells (Instance, net or port)

In order to view the property of an instance, right-click an instance and click Property on the

dropdown list. The values and pin attributes of this instance will be displayed. In order to view

the property of a net, right-click a net and click Property on the dropdown list. The connected

ports and their types will be displayed. In order to view the property of a port, right-click a port

and click Property on the dropdown list. The direction of the port and its connected net will be

displayed.

Using Goto to Reach a Specified Page

To go to a previous page or following page, right-click anywhere of the schematic view window,

and click Goto Previous Page/Goto Next Page on the shortcut menu. Another way is to click

or on the toolbar.

To go to a particular page, right-click anywhere of the schematic view window, and click Goto

Specified Page on the shortcut menu. In the Goto dialog box, choose a page number you want

to go or enter it directly.

Searching Resources you need

To find what you need in the netlist viewer, do the followings:

1. Right-click anywhere of the schematic view window, and on the shortcut menu, click Find.

2. In the Find dialog box, enter what you want to find.

3. Select the following checkboxes if needed:

Select Match case checkbox if you want Primace to distinguish between uppercase and

lowercase characters.

Select Match whole word checkbox if you want the result matches the whole word

precisely.

Select to use the regular expression to find resources.


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4. Select what kind of resources you want to find, instances, ports, or nets. If you select all

these fields, Primace will find the matched results among ports first, then find among nets,

and last among instances.

5. Click Find Next and the schematic view window will locate the resource. Use F3 to find next

matched result.

Filtering and Tracing Nets

Tracing nets is a new function in Primace 4.0. To trace nets in more than one page, do as

following steps:

1. Select Tools in toolbar> Netlist Viewer, choose the viewer you want.

2. Choose one net, right-click it and choose from page 1, or double-click it, you can trace the

net until the last page.

Filter allows you to filter out the source and destination of nodes, nets and instances in more

than one netlist. Do the followings to filter a net:

1. Press “ctrl” button and select nets, nodes or instances which you want to view.

2. Right-click anywhere of the schematic view, and on the shortcut menu, click Filter Selected

Nodes.


Capital Micro 64

3. The filtered view of the objects you select will be shown.

4. If you want to check a port without a value as source or destination, double-click the port,

and you will find it.

If you want to go back to the netlist, you can use the Backward button on the toolbar.


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Showing a Critical Path

This function displays the logic-level critical path in the technology mapper viewer. Follow the

instructions above to use this function:

1. Right-click anywhere of the schematic view window, and on the shortcut menu, click Show

critical path (logic level).

2. Choose the critical path you want to see, and click it.

3. Once you are in the page displaying a critical path, you can right-click your mouse and

Show Path in Whole Netlist option will be visible. Click it and you can see the location of

this critical path in the whole netlist.

Specifying Options of Netlist Viewer

To open the netlist viewer options page, click Tools > Options on the menu bar, and On the

Options dialog box, click Netlist Viewer. On the General Settings page, you can do the following

specifications:

Notes:

You need to reopen the netlist viewer to apply this setting.

Chip Editor Chip Editor is provided to view chip resources and timing critical paths, and to do manual

placement to achieve a better performance. After routing, you can view the placement and


Capital Micro 66

routing results of a design. If you are not satisfied with the results, you can use Chip Editor to

adjust some cells’ locations manually. After the adjustments, you need to re-run Placer and

Router flows. You can locate timing critical path from timing report viewer to Chip Editor,

analyze it and improve timing result by manual placement.

Result of editing constraints and manual placement will be recorded in .aoc file.

Opening Chip Editor

Click Tools > Chip Editor on the menu bar, or directly click on the toolbar.

Displaying chip resources

Table of used cells

Chip editor lists all used cells in a table like the following figure. You can locate a cell in chip

editor by clicking it in the table.

Graphic placement and routing result

After running placement, open Chip editor, you can see placement result. To see routing result,

run routing flow, then open Chip editor, click the “Hide/Show Routes” button, you can see

routed nets.

If you want to find out the details of routing information of a cell, please click to check its

name, location, configuration and timing info. With the button , you can trace fun in and fun

out. These two options offer you the routing information of both input and output signals from

this cell.


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Click on a blue line, it will turn to red. Right-click on the red line, two other options, locate

source and locate target, appear. The locate source option offers the information about from

which cell this signal comes; the locate target option offers the information about to which cell

this signal goes.

Searching Cells and nets

To search resources in Chip Editor:

1. Open Chip Editor by clicking Tools > Chip Editor on the menu bar.

2. Click the Find button to bring out Search Nets and CoreCells dialog box. See

the dialog box below:

3. Enter keywords in Search box in the Search Nets tab or Search CoreCells tab. You can

click to go to the location in chip package view window. And you can also

view its source and target.

4. Click OK to dismiss the dialog box.


Capital Micro 68

You can also locate the resource you want by entering its coordinate in the bottom Coordinate

text box.

Identifying Delays & Critical Paths

After running static timing analysis, you can locate critical path from timing report viewer to

Chip Editor. Chip Editor displays the critical path from source node to destination node with

partitioned delays marked.

Manual placement

If timing result does not match your requirement, you can do manual placement to improve it.

Manual placement result is recorded into aoc file as constraints to be loaded when re-running

placement.

To do manual placements, follow these steps:

1. Click on the toolbar to open Chip Editor.

2. Select a used core cell. The used core cells are all in yellow background. See the

image below:

3. Drag the cell with your mouse, and move to the location you want. See the image

below:


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4. Click Save on the File menu to save your changes. You can see the constraints

corresponding to your manual placement in aoc file.

If you want to adjust the placement of a macro, which usually several cells other than one, you

can drag one of the cells inside the macro to move it around.

Now, you can click Run Placement and Run Routing on the Flow menu to implement a

placement and routing process. A dialog box will pop up to alert you whether to load a new .apa

file. Click Yes to accept it. You can see placement result as you specified and its routing path

updated accordingly then re-run timing analysis to see timing result.

Cross Probing


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Cross-probing features enable you to locate instance, pin and net among different

editors/viewers. You can use cross-probing features among editors and viewer to analyze your

design.

Notes:

1. Cannot locate from design file in Text Editor.

2. If the opened file is not generated by current project (with current top module setting), locating operation will be disabled.

3. Technology netlist mentioned below includes post-mapping, post-placement and post-router.

Locate port

Cross probing will support locating ports among all kinds of editor/viewer. Port name in design

won’t be changed during whole flow.

Since Chip Editor cannot show design port, when locate port to Chip Editor, corresponding I/O

cell in Chip Editor will be chosen

Locate Net

Net can only be located among three kinds of technology netlist viewer and chip editor, the net

name keeps the same during these flows, no change is needed for net name. If we try to locate

net “N1” from technology netlist viewer to chip editor, the same net name and node type will be

passed to chip editor.


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Locate Instance

Instance can be located between all editors/viewers except I/O Editor.

Only I/O cells in Chip Editor can be located to I/O Editor.

Signal monitor Signal monitor is designed for debugging after router is successfully run. It allows you to route

user-specified signals to output pins without affecting the existing fitting in a design, so that you

can debug signals without having to recompile the design. Incremental routing method is

applied in this flow. The I/O(s) reserved in I/O assignment are available for use in this flow.

Starting with a fully routed design, you can select and route signals for debugging through I/O pins that were

either previously reserved or are currently unused.

Flow

The following diagram describes the flow of signal monitor:

Design File

(Text Editor)

Chip Editor

IO Editor

Gate-level

Netlist Viewer

Technology Netlist Viewer


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Configuring Monitored Signals

Before running signal monitor flow, you need to configure signal monitor assignment tool.

To configure signal monitor assignment,

Click Tools > Signal Monitor Assignment on the toolbar; or click Tools > Netlist Viewer >

Post-Routing Viewer, right-click on it, choose Monitor Signal;

Choose a net which you want to monitor from Signal Monitor page;


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Click on the Run Signal Monitor Flow on the dropdown list of Flow menu.

Creating Signal Monitor Profile

You can create signal monitor profiles in Signal Monitor Manager. Once a profile is created, a

folder which has the same name with the profile will be created accordingly. You can switch

between different profiles. Follow the instruction of this section to create a signal monitor profile:

a. Click the dropdown list after the Signal Monitor on the toolbar;

b. Choose Signal Monitor Manager. A dialogue box will pop up;

c. Click Add button to type the name of a new profile and then click OK;

d. Select the newly-created profile in the dropdown list after the Signal Monitor on the

toolbar;

e. Configure signal monitor assignment described in the former section;

Using Keil Debugger Refer to JTAG ICE Use Guide.

74 Capital Micro


EDA Tool Support

Content: introduce supported third-party EDA tools and interface.

Introduction Primace 4.0 allows you to use the EDA tools you are familiar with for various stages of the

design flow, including synthesis, simulation, and formal verification. The figure shows EDA Tool

Design Flow, refer the figure below.

Source design files(.v, .vhd, )

Primace Synthesis Tool

Primace Placement

Primace Routing

Primace Timing

Analysis

Third-party Timing Analysis Tool

Third-party Simulation Tool

Primace Bitstream Generation

Primace Download

Verilog netlist (.amv )

Third-party Formal Verification Tool

Verilog netlist (.apv, .arv )

Third-party Tool-Keil

Embedded System Design

Debugger Driver Plugged-in

MCU design file(.hex)

EDA Simulation Tools After all flows complete in Primace, both timing and logic simulation can be performed with

third-party simulation tools to verify design results. This part introduces how to use ModelSim to

do timing simulation. Please note that simulation is only available for the FP part of the design.

Configure Modelsim Environment

1. Open the Options Dialog by clicking Tools > Options to customize the Primace Environment.

2. In the Environment Page, set the Modelsim path to the Modelsim directory in your

computer.

EDA Tool Support

Capital Micro 75

Logic Simulation

Logic simulation can be processed after synthesis flow. The simulation method is almost the

same as timing analysis except for the following difference.

Click Flow > EDA Simulation > RTL Simulation to run logic sim7ulation.

76 Capital Micro

Appendix I: Design Example This section will lead you to accomplish a complete design. This design performs the task of

counter and 8051 outputting waveform to control LED display. Here CME offers a complete

design example, please visit Capital Microelectronics website to download it. Related URL is

http://www.capital-micro.com/****** .

Preparing for this Lesson Before starting this lesson, you should install the following software and prepare for the source design:

CME Software: Primace 4.0 CD

Third-Party Tools: Keil µVision

Download Kits: CME Development Board, Download Cable, and FPGA driver

Create a Project To start working on a new design, you have to create a project. In this chapter, a project named

demo1 will be created.

You can also double-click the icon of Primace 4.0 on desktop or select Start > All Programs >

Capital Micro > Primace 4.0 Beta2 > primace from the start menu to launch it.

To create a project,

1. Click to bring out a New Project dialog.

2. Type E:\Workspace\ in the Project Directory box.

3. Choose for both the Project Name and Top Module name and type it in.

4. In the Select a device box, choose CME3C06N_L144C7 as the device.

http://www.capital-micro.com/******�

Design Example

Capital Micro 77

5. Click OK to accept the settings. See the dialog box below:

Create design files with Text Editor To create a design in Text Editor:

1. Click File > New Text File on the menu bar, or to bring out the Text Editor.

2. Enter source code in Text Editor.

3. Click File > Save to save the file in Verilog HDL.

4. Click Flow > Check Syntax to be sure there is no syntax errors.

5. In the Save As dialog box, enter a name for the design file, select the file format and

then save it.

Primace supports the following two formats when you want to save a new design file:

• Verilog HDL: Verilog Hardware Description Language

• VHDL: VHDL Hardware Description Language

If another source file written in VHDL is created after the first source file in Verilog HDL is

created, wizard manager will generate a .vhd file.

Define System with Wizard Manager To define system with system wizard, follow the instructions above:

1. On the Tools menu, click Wizard Manager to start configuration.

Design Example

Capital Micro 78

2. Choose Create a new design to continue the design.

3. Choose 8051 of System in IP Cores to configure it.

Make an Embedded System Design Make an embedded design in the third-party tool Keil µVision software. For further design

information, please refer to the related Keil documents. Place the .hex file which was created

after system defined in the scr sub-folder under the project folder and configure 8051

initialization file with System Wizard.

Specify initial design constraints For more details about I/O design constraints please refer to Constraint Entry.

Run Synthesis The synthesis flow contains mapping flow in Primace 4.0. Select Flow > Run Synthesis.

Design Example

Capital Micro 79

Perform a functional simulation with an EDA simulation tool. For further details, refer to EDA Simulation Tools.

Assign I/Os in I/O Editor I/O Assignment is an essential step before placement in Capital Micro design flow. Every Capital

Micro project must have assignments to control the placement of all user ports to ensure that

the design operates correctly on the board. For more information about the I/O assignment,

please refer to the chapter of I/O Editor in the user guide.

1. Select Tools>I/O Editor or open the gray_counter.aoc in the root directory of the project to open the I/O Editor interface.

2. Assign ports. Either drag the unassigned port name and drop it to the I/O pin in graphic panel like the following figure, Or you can assign the port to appropriate I/O pin location in the text list editing mode as the following figures.

3. Save your assignments.

Design Example

Capital Micro 80

Place/Route the design and Analyze result Select Flow > Run Placement to carry out placement, figures below would show you the detail:

The progress of this step is visible in process view:

Flow > Run Routing to carry out routing, the following figures will show more details:

The progress of this step is visible in progress view:

Design Example

Capital Micro 81

Perform timing simulation Use an EDA simulation tool to perform timing simulation for the design, and debug the design

with Netlist Viewer, Signal monitor tool.

Refer to EDA Simulation Tools and Debugging and Optimization.

Analyze the timing Analyze the timing of the design by Flow > Run Timing Analysis.

For further details, refer to Timing Analysis

Debugging and Optimizing (Optional) Adjust P/R optimization options in Options dialog box and do manual placement in

the Chip Editor to correct timing problems.

For further details, refer to Timing Closure.

Create programming files and program the device Create programming files for the design by Flow > Run Bitgen, then program the device by

Tools > Downloader. For the details, refer to Programming and Configuration.

Keil Debug After your whole design is finished, download 8051 file and debug it in Keil µVision software.

Make sure you install our AGDI plug-in first. During the debugging process choose Capital Micro

8051 Emulator like the following picture.

Design Example

Capital Micro 82

83 Capital Micro

Documentation Conventions

Typographic Conventions The following conventions are used in this user guide. It can help you understand the words

and arrangements easily:

Visual Cue Meaning

bold Title name, button name, command line, file name, and the click action are in

bold format. For example, Save button, Readme file, click Yes

Courier New

font

Directory, driver name, URLs, and command line are in Courier format. For

example, C:\capital_micro\primace 4.0

italics Variable, parameter and user guide name are in italics format. For example,

Primace (version number)

Initial

Capitals

Menu name, dialog box name, panel name, keyboard key and windows name

are in initial capitals format. For example, on the File menu, F9

Note Notify you this part is a special case compared with others.

1.,2.,3.... Number lists indicate the procedures in a sequence.

• It is for non-procedure items and needn't to indicate sequence.