presto: improvements of industrial real-time embedded systems design and development
DESCRIPTION
Presentation of the PRESTO ARTEMIS project at OMG Workshop on Real-time, Embedded and Enterprise-Scale Time-Critical SystemsTRANSCRIPT
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www.modelio.org
PRESTO: Improvements of Industrial Real-time
Embedded Systems Design and
Development
Imran Quadri, PhD.
OMG Workshop on Real-time, Embedded and Enterprise-Scale Time-Critical Systems,
18th April 2012, Paris-France
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Overview
Introduction
PRESTO
Overview
End User Case Studies
Challenges
Conclusion
Demo (THALES C&S Case study)
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www.modelio.com
Introduction
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Context : Real-Time Embedded Systems
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Current design challenges
• Real-Time Embedded Systems (RTES) are exponentially increasing in complexity
• The “Design Productivity Gap”
between Hardware and Software development o Increase in Time to Market and Overall Costs
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What to do ?
• Effective design methodologies needed o Elevation of design abstraction levels
• Hand tuned coding at Register Transfer Level (RTL) High Level Synthesis (HLS) . . . .
o Co-Design (Y- Chart)
o Component based approach (e.g. AADL)
o IP-Reuse (e.g. OPC; IP-XACT)
o Model Driven Engineering
• Increasing synergy
• Separation of concerns
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www.modelio.com
PRESTO (ImProvements of industrial Real Time Embedded SysTems develOpment process)
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PRESTO Overview: Objectives
• Improve upon current RTES practices
• System Level Exploration o To enable early functional and performance analysis, platform
optimization and validation
o Test traces exploitation (e.g. System functional/non functional requirements)
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PRESTO Overview: Consortium Information
• Coordinator: Teletel (Greece)
• Budget: 8.6 M€
• Total Effort: 852 pm
• Start date: April 2011
• Duration: 36 Months
• 5 countries o 13 partners (8 SMEs)
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PRESTO Overview: Consortium Information
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United Kingdom
Greece France
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PRESTO Overview: Consortium Information
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Finland
Italy
Greece
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PRESTO Overview: Design Methodology
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Modeling RTES for System Level Exploration
• System modeling (Hardware/Software and their allocation o Approach: Classical Y-chart
o Standards/Specifications:
• MARTE, EAST-ADL, SDL, SCA …
o Integrating aspects:
• Timing,
• Performance,
– WCET analysis
• Schedulability
• Model refinements o Trace integration and visualization at model level
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Trace Driven Analysis
• Common Test Trace format definition, generation and exploitation
• Types of traces: o Test cases/Specification traces,
o Raw/Execution traces
o Filtered traces/result scenarios
• Trace filtering o Relevant traces to reduce set of inputs/states for each trace
• Functional properties verification o End user initial system requirements, causal properties, etc.
• Non functional properties verification o Deadlines, periodic, sporadic behaviors, etc.
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Software Design Flow Improvement
• Temporal logic in test scenarios o Timing constraints: Rate, latency, jitter, synchronization, etc
• Code instrumentation o Automatic code generation
• Trace generation, comparison
• Functional properties verified by generated traces from test executions
• Non functional properties verified by means of performance analysis tools
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Hardware/Platform Design Flow Improvement
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• Initial evaluation results from high level models via trace results o Performance estimation of applictation execution platform
• Virtual platforms o Application software binaries onto platform model (Simulation)
o Compare different different performance simulation models
• Simulation/Execution platform implementation results comparison o Useful for fast prototyping tool performance predictions
o Refining initial platform models
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End user case studies (MILTECH)
• Automated Test Equipment (ATE) for on-board communications based on SpaceWire (SpW) o Protocol Validation & Testing System for satellite on-board
communications
o SpaceWire standard support
o Protocol Validation & Testing
• Test cases development & execution
• Protocol Emulators
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SpaceWire Card
SpW Network Interface board
ATE SpW Tester
ATE SpW FPGA
Protocol Logic
(SpW etc.)
HW Driver
Test Cases
PTP /
Space
Packet Test
Cases
RMAP Test
Cases
Control and Configuration
Environment
Test Execution Engine
Application Driver
Other blocks HW Blocks for modellingSW Blocks for modelling
DMA CorePCIe Core
Protocol Emulators
PTP/Space
Packet
Protocol
Libraries
Protocol Execution Engine
Workstation
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End user case studies (THALES C&S)
• TDMA radio protocol case study o Part of a “Time Division Multiple Access” Radio Protocol
o Supports only a single traffic corresponding to the transmission of short messages with fixed length
o More details in subsequent demo
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Cycle
Frame 0 Frame 1 Frame 2 Frame 3 Frame 4
S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S0 S1 S2 S3 S4
Services
(Time, status, interface,
incoming/outgoing data)
TDMA Item
Network
Controller
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End user case studies (continued)
• THALES Italy o Frequency Hopping Ultra Wide Band
(FH UWB) application for indoor position
• TELETEL o MANET device case study
• Several internal experiments for improving design practices o For e.g. VTT’s FFMPEG application
implementation on Open Virtual Platform (OVP), Panda Board
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Challenges in PRESTO
• Interexchange between: o Different standards, specifications or languages (MARTE, SCA,
SysML, AADL, EAST-ADL, fUML, SDL, SystemC …)
o Different tools (Modelio, MetaEdit+, Spectra CX, TimeSquare, ABSOLUT, MOSES, MSC Tracer…)
• Adapting different end user design flows to the PRESTO methodology
• Positive influence on RTES community
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www.modelio.com
Conclusion
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Conclusion
• PRESTO o From high level design abstraction levels to execution platform
implementation
• Improving existing RTES practices in several application domains
• Contribute to future revisions of OMG standards o MARTE, SysML…
• Demo
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www.modelio.com
Questions ?
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Thanks!
Imran Quadri
SOFTEAM | ModelioSoft
PRESTO Project Web Site:
http://www.presto-embedded.eu/
SOFTEAM R&D Web Site:
http://rd.softeam.com
ModelioSoft Web Sites:
http://www.modeliosoft.com
http://www.modelio.org
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M o d e l i n g s o l u t i o n s.