presentation by tom hummel oversoc: a framework for the exploration of rtos for rsoc platforms
TRANSCRIPT
Background
Complexity of SystemsParallelismMemory ManagementConcurrency
Design ExplorationTestingValidation Experimentation
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Motivation
Prior WorksDo not consider dynamic reconfigurationDo not provide OS-like resources and
programming model
Framework must provide exploration ofSpatiotemporal SchedulingReconfiguration and Resource ManagementTask Pre-emption and migrationInter-process communication
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Platform ExplorationHierarchal
Top down designEvaluation at each level
Performance MetricsUser DefinedSystemC Simulation Model
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System Description3 Elements
Operating SystemCommunication
Memories and resourcesProcessing
GPU’s and DRA’s (Reconfig Blocks)
AbstractionLayers are separated via API’sEvaluation and exploration at each levelSystemC based simulation
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Refinement
Process Element RefinementVirtual Nodes
Functional SimulationAnnotated Nodes
Functional with timing constraintsCycle Accurate Nodes
GPU and DRA simulationsRTL Nodes
Bit level accuracy
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RTOS IntegrationSystemC OS
Highly AbstractDesigned to be service and
time accurateTest various scheduling
algorithms and resource sharing methods
CommunicationsProxy like resource
accessDoes not distinguish
between HW/SWInstantaneous
Communication
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Reconfiguration
DRA PortioningRe-active ComponentsActive ComponentsTask Parameters
MultilevelAllocation problem
defined as 3 levels for verification
Provides determinism in case HW version of task cannot run, software can take over
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DOGME ToolDesign Exploration Tool
Platform DesignSystemC Code GenerationCompilation and SimulationAnalysis
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Processor Modeling
Instruction Set SimulatorAVR Instruction Set
Easy to model and many compilersSystemC Based
Cycle accurate explorationPredictable Execution
Code broken into blocks which encapsulate system call free code
Improves simulation performance
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Validation
ApplicationRobotic Vision (Object Recognition)Nios-II on Cyclone-II SoC PlatformuC/OS-II style services
Ability of FrameworkOptimal number of CPU’s determinedTask timing versus size of reconfigurable blocksOccupation rate of reconfigurable blocksSimulation time proportional to number of OS in
system
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Opinion
Long PaperCould be divided into 2-3 papers
Poor FlowDescription of DOGME platform is begun in middle of
paper, yet most of its features are elaborated in the experimental section
Vague DescriptionsExplanation of inter-OS communication not well describedCommunication Elements were not elaborated on
ISS Architecture vs. ExperimentationISS Simulator uses AVR IS, however simulation was
performed on a NIOS-II. This discrepancy was not addressed
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