GUIDED BY SUBMITTED BY

Mr.A.Manigandan ,M.E R.Sharmila Parvin

Asst.Prof REG NO 1008472

ECE ME Vlsi Design

DESIGN OF AN EFFIECIENT DESIGN OF AN EFFIECIENT ARCHITECTURE FOR SD4 ARCHITECTURE FOR SD4

POSITIVE INTEGER POSITIVE INTEGER TRIANGULAR ARRAY TRIANGULAR ARRAY

DIVISION CIRCUITDIVISION CIRCUIT

ABSTRACT 

To date, Integer division operations are either long and cycle-

time consuming in a DSP implementation, or require long-latency

and complex hardware implementations in VLSI.

The goal of this paper is to provide a new efficient architecture

solution for implementing the division operation in VLSI i.e A

novel architecture for a non-restoring divisor based on radix-4

signed digit representation.

The radix-4 notation was chosen to achieve fast computation

presenting a Triangular architecture that will lead to a saving in

area.

The proposed divisor architecture is able to achieve a delay of O(n).

INTRODUCTION Division operation makes the system complex and is a sequence of

subtraction and comparison. Integer division takes many clock cycles than floatin point

division.

Two contributions

novel compact architecture for a nonrestoring divisor based on the SD4 representation for the partial remainder;

•triangular hardware implementation of a divider

OPERATION IDIV FDIV(s) FDIV(D)

CYCLE 56-70 23 38

1 6 5

2 331

2

13

12

11

10

1

Q

qj qj qj D (N)331 2

13 Rj

12

11 Rj

10

R- Rj

Rj >D, qj =1,

EXAMPLE FOR INTEGER DIVISION

Division operation is defined by N=QD+R

“Bit-level systolic carry-save array division,”

In this paper a division hardware architecture is presented, which is a bit-level systolic carry-save array that allows bit-level pipelining,

This leads to very fast, efficient and regular divisionimplementations as needed in digital signal processingapplications.

The architecture presented is very well suited for integer division as well as for the division of normalized fixed point mantissas used in floating-point number system implementations

It achieves the delay of O(n2)

LITERATURE WORKS

“High-radix parallel VLSI dividerswithout using quotient digit selection tables,”

The presented divider designs are based on the unifiedhigh-radix division algorithm.

The quotient digit can be obtained by prescaling the operands and converting the representation of each partial remainder into partially non redundant representation.

The quotient digit got directly from the integer part of the partial remainder without using quotient digit selection tables.

PROPOSED ARCHITECTURE

hc adderAbsolute conversion absc

Combinational logic

N-numeratorD-denominatorH-horizantal outputC-vertical carryNi-1-previous nullSi-1-previous signQ-quotient

N

D

h

c

xi

Si-1Ni-1

QSi

Ni

abssi

DESIGN OF AN EFFIECIENT DESIGN OF AN EFFIECIENT ARCHITECTURE FOR SD4 POSITIVE ARCHITECTURE FOR SD4 POSITIVE

INTEGER TRIANGULAR ARRAY INTEGER TRIANGULAR ARRAY DIVISION CIRCUITDIVISION CIRCUIT

Non restoring division algorithm.

Blocks of the proposed architecture a hc circuit, a sum circuit,absc circuit

NON RESTORING DIVISION EXAMPLE

This original architecture for a( N=4, D=4) nonrestoring SD2 divisor (eight columns and four rows),based on Non restoring algorithm.

The harware complexity is proportional to n2 array divider.

Divisor, dividend, quotient, and remainder are characterizedby the same number n of bits, it is possible to consider the architecture of the division unit as a rectangular unit

The n2cells,each composed of absc,hc and sum circuits

we have n rows and 2n-1 columns defined using only,absc,hc and sum circuits and one column composed of sum and absc.

FEATURES OF THE PROPOSED ARCHITECTURE

ORIGINAL STRUCTURE OF A NONRESTORING SD2 DIVISOR

hc ciruithc ciruit

The hc circuit accepts as inputs 2 signals: abss ,–d

1.abss:it have one of the following values: (-1,0,+1), from the output of the upper level

2.–d signal: which can be -1or 0. It also produces an vertical output h and a

horizontal carry c

c

hc

Absolute value and sign detecting circuitAbsolute value and sign detecting circuit..

absc

Sd2 (xi)

ni-1

si-1si

Sd2 abss(i)

nisi-1

ni-1

xIIi xI

i

ni

si

abssII

abssI

FunctionFunction Horizontal input: null i-1 = 0 (if the sign was not previously determined;

otherwise 1) sign i-1 = 1 (if the sign was previously determined and it was

negative; otherwise 0). Vertical input: xi.

Horizontal output:

null i = 0 (if the sign was not previously determined and xi= 0 ; otherwise 1) .

sign i = sign i-1 (if the sign was previously determined)

sign i =1 (if the sign was not previously determined and ; xi = -1 );si =0 otherwise.

Vertical output:

abssi = xi (if sign i = 0)

abssi = -xi ;otherwise.

SIMPIFICATIONS IN THE ARCHITECTURE

The Optimization is seen in the elimination of the triangle T3.

This reduction has been obtained by removing the sum and the hc circuits, with the sign and absc components still present in the divisor.

This hypothetical triangle T3 still contains the absc circuits.These circuits can be simplified considering the fact that the dividend bits remain unaffected.

Our objective is to remove, or to simplify as much as possible leftmost part of the architecture under the assumption that all the carry signals from the right side to the left are equal to 0.

    

PROPOSED TRIANGULAR STRUCTURE PROPOSED TRIANGULAR STRUCTURE OF A OF A NON RESTORIN GSD4DIVISORNON RESTORIN GSD4DIVISOR..

        

In orderto delete the left circuit we must do the following.

• Remove the signals going from the right circuit to the left one.• Compute the value of all the input signals of the circuitsin the right part of the divisor

The Proposed SD2 Sum CellThe Proposed SD2 Sum Cellfirst cell The first cell in the leftmost column computes sum pj,ni-1=+dj-1+aj,n-1which assume +2,+1,0 or-1 This cell provides as output the signal tn-1=1 pj,ni-1 =-1 if and

the signal rn-1 =1if pj,ni-1=+2

The generic cell n-k The generic cell n-k, however, computes the sum , pj,ni-k=-dj-k+aj,n-k which can assume +10-

1,or -2as values rn-k=1if pj,ni-k =0 and t n-k=1 if pj,ni-1 =-1

..

FINAL ARCHITECTURE.

TOOLS REQUIRED

Software : Verilog , Vhdl, H-Spice. Simulator : Xilinx ISE.

SIMULATION

CONCLUSION

The radix-4 notation was chosen to achieve fast computation

presenting a triangular architecture that will lead to a saving in area.

The computation of the absolute value of each partial remainder is

performed concurrently with the sign detection of the partial

remainder

The overall structure can save 40% in number of gates

This divisor architecture is able to achieve a delay of O(n).

REFERENCE

S. Kadowaki, “A hardware algorithm for integer division”.

H. Dawid and G. Fettweis, “Bit-level systolic carry-save array division” .

T. Aoki, K. Nakazawa, and T. Higuchi, “High-radix parallel VLSI dividers without using quotient digit selection tables,” in Proc. 30th IEEE.

D. L. Harris, S. F. Oberman, and M. A. Horowitz, “SRT division architectures and implementations”.