predesign nios ii i/o peripherals
TRANSCRIPT
14S4003 - Sistem Tertanam
Predesign NIOS II I/O PeripheralsSemester 1 2021/2022
10/19/2021 GFP 1
Basic NIOS II Software Development
NIOS II Processor Overview
NIOS II System Derivation and Low-Level Access
Predesign NIOS II I/O Peripherals
Predesign NIOS II I/O Drivers and HAL API
Interrupt and ISR
10/19/2021 GFP 2
Outlines
Overviews
PIO Core
JTAG UART Core
Internal Timer Core
Enhanced Flashing-LED NIOS II System
Software Development of Enhanced Flashing-LED System
Device Driver Routines
Task Routines
Software Construction and Testing
10/19/2021 GFP 3
Overviews : Case Study: Flashing-LED System Create Hardware NIOS II
System◦ Menggunakan ALTERA Qsys Tool
Terdiri dari :◦ NIOS II processor
◦ Memori on-chip, yang terdiridari blok memori pada chip FPGA; akan ditentukan memori4-Kbyte disusun dengan 32-bit words
◦ Dua parallel I/O interfaces
◦ JTAG UART interface untukkomunikasi dengan host komputer
10/19/2021 GFP 4
10/19/2021 GFP 5
DIRECT LOW-LEVEL I/O ACCESS Karakteristik unik ES adalah software perlu mengakses dan berinteraksi
dengan perangkat I/O tingkat rendah (low-level) secara langsung.
Prosesor Nios II menggunakan metode memory-mapped I/O untukmengakses port I/O
Register perangkat I/O dipetakan ke dalam ruang alamat memori utama.
Contoh: base address modul switch dan led adalah 0x0002000 dan0x0002010.
Prosesor dan program aplikasi dapat mengakses perangkat I/O denganmembaca dari atau menulis ke alamat ini.
10/19/2021 GFP 6
C pointer for I/O register
Contoh untuk membaca nilai dari modul switch dan
menulis pattern ke modul led dapat ditulis dengan
menggunakan pointer.
10/19/2021 GFP 7
C pointer for I/O register
To maintain modularity and enhance readability, we can
define a macro to encapsulate the type casting and
dereference operations.
10/19/2021 GFP 8
Robust Low-level I/O Access
Pada file io.h, altera menyediakan dua macro untuk akses I/O:
◦ IORD(base_address, offset): baca sebuah register I/O dengan
alamat dasar yang ditentukan dan offset.
◦ I0WR (base_address, data, data): tuliskan data ke dalam
register I/O dengan alamat dasar yang ditentukan dan offset.
10/19/2021 GFP 9
Overviews I/O peripherals are usually described by HDL codes and implemented
as soft cores → need to instantiate it when a Nios II system is constructed.
Altera provides a set of I/O cores for commonly used I/O functionalities.
When we use a predesigned I/O core, we must pay attention to the following: ◦ Function description.
◦ Configurability.
◦ Register map. Nios II processor utilizes the memory-mapped I/O scheme.
From the viewpoint of a processor and application software, an I/O core is represented by a collection of registers.
◦ Device driver. Device driver is a collection of software routines used to access an I/O core.
10/19/2021 GFP 10
PIO Core Parallel Input/Output
Provides a memory-mapped interface between a port of
the Avalon interconnect and a general-purpose I/O port
10/19/2021 GFP 11
Instantiation pages of the PIO core.
10/19/2021 GFP 12
PIO Modes
1. Input ports only: PIO port can capture input only.
2. Output ports only: PIO port can drive output only.
3. Both input and output ports: can capture input and drive output simultaneously
4. Bidirectional (tristate) ports: can either capture input or drive output, only one bidirectional bus
10/19/2021 GFP 13
Register map The processor controls
and communicates with a PIO core via a set of registers
Address offset 0: for I/O data, implement 2 register share same address
interrupt mask: 1 enables the interrupt request
10/19/2021 GFP 14
Register map of the PIO core
JTAG UART Core
UART: Universal Asynchronous Receiver and Transmitter.
2 serial line for data communication: receiving and transmitting
used to communicate the serial character stream between the
PC and the board
10/19/2021 GFP 15
Register map of the JTAG UARTcore
INTERNAL TIMER CORE Measuring the interval between events and generating
periodic pulses.
Key part: counter that counts down from a specific value to 0 (timeout period)
When the counter reaches 0, optional interrupt request is asserted
Counter driven by the system clock, each count = 1 clock period
Timer counter size: specifies the number of bits in the counter (32 or 64 bits), ex: 32 bit with 50-MHz clock can count up to 85.9s (2^32 x 20 ns)
10/19/2021 GFP 16
Instantiation page of the Timer Core
10/19/2021 GFP 17
Timer Register Map The status register ◦ to. The to (for "time out") bit is set to 1
when the counter reaches zero. It stays set until a processor writes 0 to this bit to clear it.
◦ run. This bit reads as 1 when the counter is running.
Control register◦ ito. This bit indicates whether interrupt is
enabled.
◦ cont. This bit specifies whether the timer operates in the continuous mode or count-once mode
◦ start. Writing 1 to this bit starts the counter running (counting down).
◦ stop. Writing 1 to this bit stops the counter.
The periodl and periodh registers store the lower 16 bits and upper 16 bits of the 32-bit timeout period value.
10/19/2021 GFP 18
The 32 bit timer core contains up
to six 16-bit registers
Register map of the timer core
Block diagram of an
enhanced flashing
- LED system.
10/19/2021 GFP 19
Add and configure PIO modules
For the eight discrete green LEDs, add a PIO module, configure it as an 8-bit
output port, and rename it ledg.
For the ten discrete red LEDs, add a PIO module, configure it as a 10-bit
output port, and rename it ledr.
For the four seven-segment LED displays, add a PIO module, configure it as a
32-bit output port, and rename it sseg. To accommodate the software
program development, allocate 8 bits (i.e., a byte) for each display. Since
there are only seven segments on a display, the MSB of the byte is not used.
For the ten slide switches, add a PIO module, configure it as a 10-bit input
port, and rename it switch.
For the four pushbutton switches, add a PIO module, configure it as a 4-bit
input port set up the edge capture capture the l-to-0 transitions
Two timer modules: one for system-level housekeeping function and one for
the user application
10/19/2021 GFP 20
The enhanced flashing-LED system Operates
The desired flashing time interval is specified by the ten slide switches. The value is loaded to the system when pushbutton switch 1 (labeled keyl on the DEI board) is pressed.
The flashing can be temporarily stopped. Pressing pushbutton switch 0 pauses and resumes the operation alternatively.
The four seven-segment LED displays show the current status of the system. The left-most display shows a 'P' pattern if the flashing is paused and the next three displays shown the value of the flashing interval in milliseconds.
The host console displays a message whenever a new interval value is set. This message is transmitted via the JTAG UART module.
The timer module keeps track of flashing interval and turns on and off the two discrete LEDs alternatively.
10/19/2021 GFP 21
The Skeleton of the Main Program
10/19/2021 GFP 22
Timer
Configured:
◦ During initialization, set the timer to count 1 ms continuously.
◦ During normal operation, keep track of the number of 1-ms ticks and toggle the LEDs as needed.
◦ The to (timeout) field of the status register is set to 1 when the counter reaches 0 and it remains 1 until the processor writes 0 to this field. This field can be treated as a "tick" that is asserted periodically.
◦ Define two macros to check and clear the to field
10/19/2021 GFP 23
Driver routine
The driver routine sets up the countdown period and
activates the counting
10/19/2021 GFP 24
The fllashsys_init_vl( ) function
It clears the btn module's edge capture register and sets
up the timer for 1 ms.
Note that the Nios II system runs at 50 MHz and thus
the 1-ms interval requires 50,000 clocks (i.e.,1 ms =
50000 * 20 ns).
10/19/2021 GFP 25
The led_flash_vl( ) function
toggles the two discrete LEDs according to the specified interval
If the pause field is not asserted, the routine toggles the LED
pattern and enters the while loop.
The loop body checks the 1-ms tick continuously and increments
the count, ntick, when the tick is asserted.
10/19/2021 GFP 26
EOF
10/19/2021 GFP 27