precise modeling of hot carrier gate current in short-channel mosfet's

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 9, SEPTEMBER 1993 1645

Precise Modeling of Hot Carrier Gate Current in Short-Channel MOSFET’s

Adel E. El-Hennawy, Senior Member, IEEE, and Owaish H. Mobarek

Abstract-Precise modeling of hot carrier gate current in short-channel MOSFET’s has recently been extremely useful for the evaluation of VLSI design and the prediction of device and circuit performance. The paper presents a powerful model which considers the fact that the values of the channel and carrier temperatures T and T, vary with position in the bulk and channel. It, consequently, reveals that the energy distribution of hot carriers deviates from the well-known Maxwellian distribution by a small but nonnegligible perturbation and eval- uates the dependence of this deviation of the device technology, geometry, and biasing conditions. The presented model helped to remove important discrepancies between the old hot-carrier models and measurements.

I. INTRODUCTION OT CARRIERS at the Si-SiO, interface of MOS- H FET’s play an important role in the modeling and

characterization of MOSFET devices and systems [ 11-[3]. Hot carrier generation is always associated with several unavoidable effects such as: a) increased surface trapping and recombination, b) degraded channel mobility, and c) noticeable threshold-voltage shift and instability. These effects become increasingly important as the trend towards progressively smaller MOSFET geometries is increased [3], [4]. Several models have developed to evaluate the hot carrier gate current and to characterize the associated phenomena [5], [6]. However, the dependence of the hot carrier distribution on the carrier distribution on the crystal carrier and crystal temperature has been ig- nored. This imposes disagreements between theory and experimental results. Measurements showed, in fact, that the channel and the carrier temperatures Tand T, are bias- and position-dependent. Moreover, T, undergoes a suffi- ciently strong variation, with position over the MOSFET channel length (A T, - 90 K), that the carrier distribution deviates from being the same over all the channel length [4], [5] , [7]. A simple two-dimensional (2-D) model of the crystal temperature Tin the MOSFET surface and bulk is developed in Section 11, from which the hot camer temperature distribution T, inside the channel is deduced. Precise modeling of the hot carrier injection and transport in the MOSFET oxide, is, consequently, achieved. This model is experimentally verified and seen to be more con-

Manuscript received July 17, 1992; revised February 17, 1993. The re-

The authors are with the Physics Department, Faculty of Sciences, King

IEEE Log Number 9210620.

view of this paper was arranged by Associate Editor Y. Nishi.

Abdul Aziz University, P. 0. Box 9028, 21413 Jeddah, Saudi Arabia.

sistent with the measurements than the other developed models. We have performed our experimental measurements on test specimens of H MOS I and H MOS I1 gen- erations which were fabricated by Thomson EFCIS, Grenoble, France. The MOSFET channel length L and width 2 range, respectively, from 0.5 to 10 pm and from 3 to 100 pm and the oxide thickness varies from 400 to 1200 A. Aluminum and polycrystalline-silicon gate MOSFET’s were examined. Simulation and experimental results are presented and discussed in Section 111. A better agreement between the theory and measurements is ob- served specially for devices with L varying from 0.7 up to 3 pm. However, for L greater than 3 pm the presented model gives the same results as those derived from the other models ignoring the dependence of the hot carrier distribution on the crystal and carrier temperatures. Fi- nally, conclusions are presented in Section IV.

11. MODEL This section comprises a 2-D analysis and evaluation

of the crystal temperature T(x, y) in the MOSFET substrate and surface, from which the hot-carrier temperature distribution T,(x, y) and its dependence on the device biasing and geometry is deduced. Precise evaluation of the hot-carrier distribution n ( ~ , T,) and its dependence on the same parameters is consequently investigated. This subsequently leads to a more accurate evaluation of the hot carrier injection efficiency, escape probability, mean energy, and finally to the precise modeling of the hot carrier gate current and its associated effects.

A. Crystal Temperature Distribution T ( x , y) When the channel of a MOSFET is switched by a strong

electric field E,, the mobile carriers are accelerated and gain energy. These carriers emit some of their energy into the crystal through camer-lattice collisions [4]-161. When the channel field is so strong that the energy gain is greater than that lost in collisions, carrier heating takes place. The energy exchange between the hot carriers and the lattice continues and tends to increase the lattice temperature T, especially if the lattice radiation capability is notice- ably small. This provokes stronger lattice vibrations (op- tical and acoustic phonons) and leads to greater interac- tion between hot carriers and these vibrations which decreases the hot carrier mobility p. Therefore, the rate at

0018-9383/93$03.00 0 1993 IEEE

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1646 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 9, SEPTEMBER 1993

which these carriers gain energy from the channel field

and that at which energy is transferred to the lattice are decreased. This process continues until balance is reached between the two rates and the crystal and carrier temperatures T and T, attain their steady-state values.

The MOSFET power is dissipated within the channel region. As shown in Fig. 1 , this region is sandwiched between the oxide layer (from above) and the silicon substrate (downwards). Since the thermal conductivity of Si is a thousand times greater than that of S O 2 , it is expected that most of the thermal power diffuses downwards into the substrate, and a temperature gradient, with its maximum at the channel and minimum at the bottom of the substrate, is established. Also the dissipation of power inside the channel is longitudinally position-dependent owing to the nonlinear distribution of the channel potential. The channel temperature is, therefore, expected to vary with the distance x and to acquire its maximum value beside the drain.

The evaluation of the crystal temperature T(x, y ) in the MOSFET surface proceeds as follows: T(x, y ) is related to the volume power density Pv(x, y ) by the continuity equation [8]

where CY is the thermal diffusivity, pv is the specific mass, and C, is the thermal capacity. Since the channel depth do is very small compared to the thickness of the substrate, ( 1 ) could be developed to

Referring to Fig. 1 , the following boundary conditions can be deduced:

(3)

The solution of (2 ) with the boundary conditions (3) reveals the 2-D steady-state distribution of the crystal temperature T(x, y ) in the MOSFET surface [ 4 ] , [ 5 ] , [9], [ 101

Fig. 1 . A section in MOSFET device with the expected variation of the substrate temperature T i n the x and y directions.

H > y > H - do. (4b) The dependence of Ton x comes from the dependence of Pv on x

where ZDs, VDs, VDss, and A1 are the same channel current, the drain-to-source voltage, the drain-saturation voltage, and the pinch-off region length, respectively

7

Figs. 1 and 2 show the expected variation of T in the x and y directions. We see that T increases, in the y direction, when approaching the Si-Si02 interface. It also increases in the x direction when approaching the drain.

B. Carrier Temperature Distribution T, (x , y ) In the steady state, the hot carrier mobility decreases

due to random collisions of carriers with lattice vibrations. Consequently, it tends to decrease the rate at which carriers gain energy from the channel fields and makes it equal to that at which carriers emit energy into the crystal. In this case, T, and T become constant and related to each other by r41, r51, r121

T, = T [ i + (z>’], 2 > n > 1. (6)

EL-HENNAWY AND MOBAREK: MODELING OF HOT CARRIER GATE CURRENT IN MOSFET'S I647

tY

T(X.Y)

Fig. 2. The expected variation of the substrate temperature T in the x and y directions.

With E, as the critical value of E, at which appreciable carrier heating begins (E, - 1.5 V/pm for electrons and - 2V /pm for holes). E, is position-dependent [ 113. It is given by

Substituting from (7) into (6) yields

Te(x, Y ) = T(x, Y )

(8) Equation (8) shows that T, increases with x , while it re- mains nearly constant over the whole channel depth.

C. Carrier Energy Distribution When the channel fields are so small that thermal equi-

librium conditions are established at crystal temperature T equal to room temperature, the density of the free carriers, over the whole channel length L, varies with the carrier energy E and temperature T according to the well- known Maxwell-Boltzmann distribution [5]-[7]

n(E, T,) = ~ , e - ( e - e ~ ) / k T f . (9) When this distribution is adopted in the model used to evaluate the hot carrier gate current Zg, noticeable deviations from the simulation results measurements were ob- served. These deviations are seen to increase with the increase of biasing voltages VDs and VGs and/or the decrease of the channel length L. A new distribution which is bias- and device-geometry dependent should, therefore, be considered. However, as carrier heating takes place due to the operation of strong channel fields, T increases over room temperature and Te is no longer constant over the channel length. The free carrier distribution deviates therefore from the Maxwell-Boltzmann distribution. A perturbation term 6n(E, T,) should be added to that given

AT,' a2n(e, T,) + - ( aT,' ) + - 2

. (lob)

combining (loa) and (lob) yields

n(E, T,) = N, 1 + - - [ ( E iT:)

. - ef)/kT,

The third term in the large parentheses is negligibly small with respect to the second one, then

Since T, is position- and bias-dependent [see (S)], then n ( E , T,) and 6n ( E , T,) will also be functions of position x , y and biasing voltages VGS and VDS (n ( E + T,) and 6n ( E ,

T,) increase as VGS, VDS are increased and/or L is shortened). Simulation and measurements show that the use of this distribution in the present modeling removes the above mentioned inconsistency between the theory and measurements.

D. Hot Carrier Gate-Current Model The hot carrier gate current Ig results from the injection

of hot carriers into the oxide and the transport of these carriers towards the gate electrode [ 5 ] , [6]. Fig. 3 shows a cross section in a MOS structure with the mechanism of creation of I g . Referring to Figs. 1 and 3, the formulation of Ig proceeds as follows:

(12)

with part pox being the oxide mobile charge density. It is given, in terms of the channel mobile charge density pch, the injection efficiency Pinj, and the escape probability pes,, by [SI

Pox = PinjPescPch (13)

and vox is the hot carrier velocity inside the oxide. It is given in terms of the oxide carrier mobility pox and oxide field EO,, by 141, 151

vox = ~OXEOX (144


potential barrier peak is shifted by a distance X, into the oxide due to the interface forces. This decreases Pinj by a factor of exp ( - & / l o x ) , with lox being the mean free path of hot carrier inside the oxide. Equation (15) develops, therefore, as

4' ] exp [-(E + $ + ")1, 10,

Aq5 1 0 ( 174

Aq5 e 0 Fig. 3. The energy band structure MOSFET indicating the phenomena of

hot camer injection. and

with I

Pox = Pox0 42 and

pe, = [l - E] (14b) where E, is the mean energy of hot carriers. It is given by

[121, r131

$ F ~ ( E , Te)E + F ~ ( E , Te) Em +

Substituting from (1 1) into (19) yields

V, = Vg[l - ,/*I. (14d) L _I Substituting from (13)-(20) into (12) yields

(2 1 a) The probability of injection is defined as [4], [6]

Substituting from (1 1) yields

x exp [-(2 + 6 + " ) I cix 1, lox

and cg is the energy gap width (1.1 eV). E,,, is the critical value of the oxide field ( - 1.1 x lo8

V/m) over which pox begins to decrease as Eo, further increased.

Equation (15) is only valid for hot carriers existing at the Si-Si02 interface. For those carriers existing deeper in the channel, only exp ( - y / l , ) carriers of their total number, existing at a distance y from the Si-Si02 inter-

mean free path of hot carriers in silicon [5]. The worst case concerns carriers existing at the bottom of the chan- ne1 ( y = do, with do being the channel depth). Also the

V2 w = "[ do (vDs ] s" L - ~ ~ PoxpEox( 1 - E)

kT, + Aq5

face, will successfully arrive at the interface; 1, being the x exp [ -(% + 5 1, + h)]cix lox (22b)

with VDs, VDSS as the drain-source and drain-source saturation voltages, respectively, VGs the gate-source volt-

EL-HENNAWY AND MOBAREK: MODELING OF HOT CARRIER GATE CURRENT IN MOSFET’S 1649

age, VT the threshold voltage, and CO the oxide capaci- tance per unit area. The suffixes n and p are used to distinguish between electron and hole parameters.

111. MEASUREMENTS AND SIMULATION This section comprises the presentation of the test de-

vice specifications and explains the experimental setup with the necessary precautions to be considered. The experimental and simulation results are also presented and discussed.

A. Sample Preparation The measurements are performed on short-channel

MOSFET’s supplied by Thomson Microelectronics, Grenoble (see Fig. 1). They are n-channel of channel length L and width 2 ranging, respectively, from 0.5 to 10 pm and 3 to 100 pm. The oxide was processed by wet oxidation at !00”C and has a thickness ho ranging from 400 to 1200 A. The surface orientation is ( 100) and the doping profile has a surface level of about 1.05 X 1 0 1 6 / ~ ~ 3 .

B. Experimental Setup The hot carrier gate current Zg was measured as a func-

tion of the biasing voltages V,, and VGs for different device geometries Z, L , and ho. Fig. 4 shows a circuit dia- gram of the experimental setup, in which the HP p140 B microprocessor-based picoampere-meter ( A mea- suring capability) and voltage source (two programmable output voltages) is used. Some principal precautions are considered to minimize the device and setup leakage currents and make it possible to achieve the Zg measurement with the desired precision. A guard ring surrounding the gate window and all gate interconnections on the chip, seal and printed circuit levels, is employed and biased at the same gate voltage. Triaxial connectors are also used. Additional precautions against photo-induced leakage currents are considered.

C. Computer-Aided Acquisition of Device Parameters Thousands of test devices were automatically examined

to determine the values of their parameters (nomin$ value and Standard deviation). These values (1, = 40 A , h = 10 A , VTo = 0.5 V, po = 600 cm2/V.s) are fed to the simulation program.

D. Computer Aided Analysis A powerful and reliable simulation program which is

based on the modeling of Section I1 has been established and implemented in 486 fast personal computer in con- junction with a high-resolution and flexible-graphics technique. This software is capable of characterizing and ana- lyzing, individually and globally, all parameters related to the theory of carrier heating phenomena and their effects on the MOSFET operation and their dependence on the device geometry, technology, and biasing. Simulation

$Gl:d.P$ ,[k;sm+vm

PA

“GS

Fig. 4. The experimental setup used to measure 18.

results are compared to measurements and discussed in detail.

E. Experimental and Simulation Results Fig, 5(a) and (b) shows the variation of the channel

temperature T and the carrier temperature T, with the drain-to-source and gate-to-source voltages VDs and VcS for different values of the device geometric ratio Z / L . Here the average values of T and T, occurring mid distance between the source and drain (x = L / 2 ) are considered. Smaller values are expected to be obtained at x < L / 2 while greater values are obtained at x > L / 2 . We observe that T and T, increase as V,, and/or VGs are increased. This is because the channel current Z,, and, consequently, the volume power density dissipated in the channel Pv increase with increasing V,, and/or VGs. It is also seen that T and T, increase with the decrease of the MOSFET channel length L. This is related to greater carrier heating occurring in shorter channels and the larger power density associated with it.

Fig. 5(c) and (d) shows a 2-D distribution of T and T, over the substrate thickness ( y direction) and along the channel length (x direction) for different device geometries. We observe that T and T, increase, over the whole channel length, with the decrease of the channel length L.

Fig. 6(a) and (b) presents the simulation results con- cerning the variation of the injection probability Pinj with position x and its dependence on the device biasing ( VDs, VGs) and channel length L. We see that Pi, increases ex- ponentially with x and acquires greater values with shorter channel lengths. The sensitivity of P , to VDs variations is seen to be smaller the longer is the channel length L. When the MOSFET is switched into saturation or near saturation (V,, 1 VGs) the rate of change of Pi, with x is increased near the drain and strongly decreased near the source. This is referred to the channel potential V, which is modified during saturation so as to correspond to en- hanced potential near the drain and reduced one else- where.

Fig. 7(a) and (b) investigates the simulation results of the dependence of the hot carrier gate current density Zg,ZL on the position x for different biasing conditions (V,,, VGs) and channel lengths L. We notice that the current density increases with x and becomes greater with shorter channel lengths. The sensitivity of the current density to variations of VD, and VGs increases as L is reduced. This is referred to the enhancement of Pinj occurring when L is shortened.

Figs. 8(a)-(c) and 9 show the simulation and experi-

I


5-

m-

3000 -

2000 -

1000 -

(-

O b

V,,=lOV v,s=lov v ~ s = 8 v vDS=8v V ~ = 8 v

(C) (d) Fig. 5 . (a) Variation of the channel temperature T with VDs for different values of VGs. (b) Variation of the electron temperature T, with VDs for different values of VGs. (c) Dependence of the x , y , distribution of Ton the channel length L. (d) Dependence of the x , y, distribution of T, on the channel length L.

(a) (b) Fig. 6. (a) Dependence of the injection probability distribution on the device geometry and biasing (VDs parameter). (b) D e

pendence of the injection probability distribution on the device geometry and biasing (VGs parameter).

mental results of the hot carrier gate current Ig as a func- tion of the device biasing geometry. We see that Ig re- mains null as long as VD, is smaller than a certain critical value VD* = LE,, below which no carrier heating occurs. As VDs exceeds VDsj, appreciable carrier takes place and Ig is created and begins to increase proportionally with VDs and becomes greater the greater is the value of VGs

and/or the shorter is the channel length L. This is caused by the increase of the oxide field E,, (as VGs is increased) and leads, therefore, to decreased oxide trapping. This latter makes the rate of increase of Ig with VGs to be larger at larger values of VGs. On the other hand, the channel field E, is increased (as the channel length is reduced) and consequently it enhances channel camer heating. As V,,

EL-HENNAWY AND MOBAREK: MODELING OF HOT CARRIER GATE CURRENT IN MOSFET'S 1651

-5 10 -

o " " " " ' 1 xipm1

0.2 0.4 0.6 a8

(a) (b) Fig. 7. (a) Dependence of the gate current density distribution on the device geometly and biasing (VDs parameter). (b) Depen-

dence of the gate current density distribution on the device geometry and biasing (VGs parameter).

LOR= 20

0 5 10 15

Fig. 8. Variation of the gate current density with VDs for different values of VGs(L = 4 pm). (b) Variation of the gate current density with VDs for different values of VGs(L = 2 pm). (c) Variation of the gate current density with VD, for different values VGs(L = 1.4 pm).

- v,, - 10 y , VGS - 06 v

n s = 75v. v,= 1ov

0 5 V . V,- 1 3 V V,, = 1 O V Ds = 05V.

0 1 2 3 L 5 L(um)

Fig. 9. Variation of the gate current with the channel length L for different values of VGs and VDs.

continues to increase (V,, - VGs - V,), I, begins to saturate and to decrease thereafter as V,, is increased further. This is attributed to the creation of the pinchoff region where the normal oxide field E,, reverses its polarity and stops, therefore, hot electron injection and favors in- stead the injection of hot holes. We observe that the values of V,, at which the I eaks occur is greater the greater the value of VGs, which insures that this Z, behavior is related to the channel pinchoff. We observe an excellent agreement between the measurements and modeling. However, a small inconsistency appears with channel lengths smaller than 1.4 pm. This is related to uncertainty in the pinchoff-region length A1 which appears here to be greater than the value given by the model. This problem does not appear with longer channel MOSFET's (L > 1.4 pm). A more exact modeling of A 1 necessitates precise modeling of the channel depth do which, up till now, has not been given sufficient attention. This field is very important for the submicrometer MOSFET devices and applications. In Fig. 9, I, is seen to increase as the value of L decreases. I, begins to saturate at L = 1.4 pm and to

g ?


decrease thereafter as the value of L is decreased further.

and to the hot hole injection occurring over the pinchoff region which becomes comparable in area to that of the gate.

[81 H. S. Carslaw and G. C. Gaeger, Conduction of Heat in Solids. OX- ford, UK: Oxford Univ. Press, 1959.

channel temperature in MOSFET from HCI measurements,” in ESSDERC 81, Europhysics Conf. Abstr., Toulouse, France, 1981.

[IO] A. El-Hennawy, “Cancellation of gain error of MOSFET IC Op. Amp,” Sri. Bull. FEIASU, vol. 26, no. 3, pp. 246-269, Sept. 1991.

I I 11 J. L. Moll, Physiques de Semiconducteurs. New York: McGraw-

This is to the reduction Of the gate surface area [9] A. El-Hennawy, J. Borel, and D. Barbier, ‘‘Determination of the

. . . - Hill, 1964.

[12] P. Hohenberg and W. Kohn, “Inhomogeneous electron gas,” Phys. Rev., vol. 136, 1964.

[13] 0. H. Mobarek, “On the gradient expansions of the kinetic and exchange density functionals,” IL Nuovo Cimenro, vol. 102 B, no. 4, 1988.

IV. CONCLUSIONS The paper comprises a 2-D modeling and simulation of

the and carrier temperatures ~~~d T,, which make possible a precise evaluation and prediction of the hot carrier energy distribution n ( ~ , T,) and probability of injection Pi,. As a result, the hot carrier gate current Ig is ac- curately modeled and experimentally verified. The dependence of Ig and all related variables on the MOSFET geometry and biasing conditions is also revealed. The experimental results are in good agreement with the model. This work could be extended to study and evaluate the reliability and parameter stability of MOSFET’s and re- veal any short-term or long-term degradation due to stressing.

ACKNOWLEDGMENT

Adel E. El-Hennawy (M’90-SM’91) was bom in Domiat, Egypt, on June 24, 1948. He received the B.Sc. and M.Sc. degrees in electronics and com- munications engineering from Ain Shams Univer- sity, Faculty of Engineering, Cairo, Egypt, in 1971 and 1975, respectively. He received the DEA, Ph.D. and Doctor of state degrees in microelectronics from the National Institute of the Polytechnique de Grenoble INPGIENSERG, Grenoble, France, in 1977, 1981, and 1983, respectively.

He was with the French Nuclear Enerev Center of Grenoble CENGl

lation program and the achievement of some analysis. Department of Electronics and Computer Engineering, Faculty of Engi- neering, Ain Shams University, Cairo, Egypt. He joined the Yarmouk Uni- versity, Hijjawy College of Technology, Irbid, Jordan, in September 1988. He became the Assistant to Dean of the College in Februarv 1989. Since REFERENCES September 1989, he has been with King Abdulizis University, Faculty of science, ~ ~ d d ~ h , saudi Arabia, [ I ] A. El-Hennawy, “Design and simulation of non-volatile CMOS EE-

PROM compatible with scaling down trends,” Int. J. Electron., vol. 72, no. I , pp. 73-87, 1992.

[2] A. El-Hennawy and F. AI-Ghamdi, “Study and characterization of MOS IC magnetodetector,” Proc. Inst. Elec. Eng., pt. G , vol. 139, no. 1, pp. 119-125, Feb. 1992.

[3] W. Shahab and A. El-Hennawy, “New technique for offset compen- sation and noise reduction of MOSFET VLSI op amp,” Int. J . Elec- tron., vol. 68, pp. 547-566, 1990.

[4] A. El-Hennawy, M. H. El-Said, J. Borel, and G. Kamarinos, “Mod- eling of MOSFETs at strong narrow pulses for VLSI applications,” Solid-Srate Electron., vol. 30, no. 5, pp. 519-526, 1987.

[5] A. El-Hennawy, J. Borel, B. Baylac, and N. Ballay, “Measurement and modeling of hot camer gate current in MOSFET VLSI,” in ESSDERC 82, Europhysics Conf. Absr., (Munich, Germany, 1982).

[6] T. H. Ning, “Emission of hot camers into MOSFET oxide,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, 1979.

[7] W. Kohn and L. J. Sham, “Self-consistent equations including exchange and correlation effects,” Phys. Rev. A, vol. 140, p. 1133, 1965. tant Professor in 1985.

-

Owaish H. Mobarek was bom in AI-Humaed, A1 Bahah District, Saudi Arabia, on July 1, 1952. In 1972, he enrolled at Riyadh University, Riyadh, Saudi Arabia, and received the B.Sc. degree in physics and general mathematics in 1976. In Au- gust 1977, he enrolled at Indiana University, and after completion of some English and physics courses, in the Fall of 1979, he transferred to Tu- lane University, New Orleans, LA, to do graduate work. He received the Master’s degree in physics in 1982 and the Ph.D. degree in December 1984.

From June 1976 to August 1977 he was a graduate assistant in the Col- lege of Medicine at King Abdul Aziz University in Jeddah, Saudi Arabia. He retumed to the University and joined the Physics Department as Assis-

precise modeling of hot carrier gate current in short-channel mosfet's

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