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Pre and post-silicon techniques to deal with large-scale process variations Jaeyong Chung, Ph.D. Department of Electronic Engineering Incheon National University

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Page 1: Pre and post-silicon techniques to deal with large … · Pre and post-silicon techniques to deal with large-scale process variations ... Statistical Static Timing Analysis

Pre and post-silicon techniques to deal with large-scale process variations

Jaeyong Chung, Ph.D.

Department of Electronic EngineeringIncheon National University

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Outline

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Introduction to Variability Pre-silicon Techniques

Basics of traditional static timingOCV AOCV/LOCV SSTA POCV/SOCV

Post-silicon Techniques Compressed Sensing Compressed Silicon Sensing (CSS) Virtual ProbeOur Proposed Framework Application of CSS

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Timing Uncertainty

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Add Timing Margins For Delay Uncertainty– Process Variation– Voltage Variation– Temperature Variation– Aging Effects

Associated Costs– Area, Power, Design Efforts/Time

CLOCK

Actual Circuit Delay

AgingProcessTemperature Voltage

Timing Margin

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Classification of variability

4

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Sources of variation FEOL (Front end of line) variation BEOL (Back end of line) variation

5

Lithography-induced variation/Proximity effects

Random Dopant Fluctuation

Erosion and dishing in CMP process

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CD (Lgate) Variation Critical dimension (a.k.a, Lgate, Leff,…)

– The effective channel length of transistors– Affects delay and leakage substantially– Varies across-wafer and within-chip systemically

A reduction of 1nm of the standard deviation of CD → $7.5/chip for a high end product

6

http://www.eecs.berkeley.edu/~bora/Conferences/2009/SPIE09-Qian.pdf

a) wafer-to-waferb) Across-waferc) Die-to-died) Across-diee) Pattern dependentf) Local random noise

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CD (Lgate) Variation Across-wafer CD variation

– Post Exposure Bake (PEB) is the greatest variation culprit– In areas where the bake plate is relatively cool, CD is larger than average

7

http://bcam.berkeley.edu/ARCHIVE/theses/Friedberg_PhD.pdf

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CD (Lgate) Variation Within-chip CD variation

– Lens aberration induces spatially correlated variation– Different layout leads to different spatial patterns due to optical proximity effect

8

http://www.bioee.ee.columbia.edu/courses/upload/Bibliography/orshansky2004.pdf

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Voltage, temperature, weather, …

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[IBM]

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Spatial Correlation

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Traditional Static Timing

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Setup check

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Traditional Static Timing

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Hold check

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Traditional Static Timing

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CLOCK

D Q D Q

Launch Path

Capture Path

Use worst/best corners for setup/hold checks

LD

CD

Setup Check

cL ckc loTD D< +

(Launch clock path + data path)

p1

p2

Process Space

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Traditional Static Timing

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CLOCK

D Q D Q

Launch Path

1

1

Capture Path

GBA (Graph-Based Analysis) takes linear time in circuit size PBA (Path-Based Analysis) takes exponential time in circuit size

LD

CD

Setup Check

cL ckc loTD D< +

1

1

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Traditional Static Timing

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GBA finds an upper bound of the worst path delay in linear time through the graphGBA is pessimistic than PBA

a

b c

D Q

The upper bound of the worst path delay

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On-Chip Variation (OCV)

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CLOCK

D Q D Q

Launch Path

[0.95,1.05]

[0.95,1.05]

Capture Path

LD

CD

Setup Check

cL ckc loTD D< +

[0.95,1.05]

[0.95,1.05]

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On-Chip Variation (OCV)

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CLOCK

D Q D Q

Launch Path

[0.95,1.05]

[0.95,1.05]

Capture Path

Common Path Reconvergence Pessimism Removal (CRPR) (a.k.a, CPPR)

LD

CD

Setup Check

cL ckc loTD D< +

[0.95,1.05]

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Statistical Cancellation

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(OCV)

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Statistical Cancellation

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Advanced OCV (AOCV) (aka LOCV)

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[Synopsys Whitepaper]Stage-based AOCV

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Advanced OCV (AOCV) (aka LOCV)

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[Synopsys Whitepaper]

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Advanced OCV (AOCV) (aka LOCV)

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CLOCK

D Q D Q

Launch Path

[0.95,1.05]

5%

Capture Path

Cells gets different derate depending on the logic depth and the cell type (Design-specific OCV, CLK DA) it also depends on the loads and slews

LD

CD

Setup Check

cL ckc loTD D< +

[0.95,1.05]3%

[0.95,1.05]

[0.97,1.03]

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RSS credit in setup/hold check

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cL ckc loTD D< +

Setup CheckMethod 1 (OCV)

RSS credit

Method 1 (OCV)Method 1 (OCV)

If perfectly correlated, variation will be canceled

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Advanced OCV (AOCV) (aka LOCV)

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cL ckc loTD D< +

Distance-based AOCV[Synopsys Whitepaper]

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Advanced OCV (AOCV) (aka LOCV)

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5%

[0.95,1.05]

0.02

0.05

0.03

3%

+

=

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Advanced OCV (AOCV) (aka LOCV)

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Derating Table for each cell type [Synopsys Whitepaper]

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Advanced OCV (AOCV) (aka LOCV)

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AOCV requires a lot of library characterization efforts Derating values for each cell type, each depth, each location, each

slew, each loadWorst-case derating is selected across each load and each slew

A source of pessimism AOCV tables doesn’t have much information

Can be predicted by the simple analytic model

Path credit is mapped into the credit of segment delays Paths do not consist of a single type of gates Not graph-based analysis (GBA) friendly

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Statistical Static Timing Analysis (SSTA)

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Statistical Static Timing Analysis (SSTA)

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All timing quantities computed and propagated in a parameterized form ATs, RATs, slacks, slews, delays, etc

Need to characterize sensitivities for each cell type, each delay, each slew

Canonical Form

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Statistical Static Timing Analysis (SSTA)

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Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

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Statistical Static Timing Analysis (SSTA)

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Use 7 variables in the Canonical Form

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Statistical Static Timing Analysis (SSTA)

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SSTA benefits Chip-to-chip variation

No corners Safe RSS credit

Within-chip variation RSS credit down a path RSS credit in setup/hold

check

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Statistical Static Timing Analysis (SSTA)

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Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

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Statistical Static Timing Analysis (SSTA)

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Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

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Statistical Static Timing Analysis (SSTA)

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Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

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Statistical Static Timing Analysis (SSTA)

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Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

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Statistical Static Timing Analysis (SSTA)

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Apples-to-apples comparison of statistical flow to: 2 corner foundry-like timing with derating ‘n’ corner industry-standard flow Exhaustive corner timing

Statistical Timing: Where’s the tofu? ICCAD 2009, IBM

- 380ps total- 200ps from RSS credit in chip-to-chip variation- 80ps from RSS credit in on-chip variation

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Parametric OCV (POCV) (aka SOCV)

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Use SSTA for within-chip variation only Eliminate a lot of characterization burden from SSTA, giving up the

benefits in chip-to-chip variation Use a few variables only in the canonical form

Statistical OCV (SOCV) is a similar technique In theory, POCV/SOCV is clearly a better engineering than AOCV

Better accuracy and less characterization effort

“A parametric approach for handling local variation effects in timing analysis”, DAC 2009, Mutlu. A (Extreme DA)

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Remaining Pessimism in SSTA/POCV

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CLOCK

D Q

[Chung and Abraham, ICCAD 2009] (Best Paper Award Nomination) [Chung and Abraham, TCAD 2012]

D Q

Launch Path

Capture Path

Refactoring - CRPR for Combinational Networks

CD

cL ckc loTD D< +

Setup Check

a

b

c

d e

max( , )max( , )

L cd

cd

D D a b a c d eD a b c d e= + + + + +

= + + + +

Using DistributivityOf + over max

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Compressed Sensing

RGB2YCbCr Color

Converter

8X8 Block2D

DiscreteCosine

Transform

QuantizationHuffmanEncoding

JPEG Encoder IP

Acquisition(Sampling)

f f

Sparse

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Compressed Sensing

Tremendous impact on signal processing, machine learning, statistics,.. The original groundbreaking paper [Donoho 2004] has been cited 8769

times (200+ papers in the last 3 years.) Linear measurements

Non-uniform sampling

or

Classical answer: Underdetermined → cannot solve

We have k equations and 2m unknowns, If k>2m, we may have a unique solution

New answer: Information on 2m unknowns are encoded into k measurements, andwe can recover it perfectly and efficiently(In practice, around 4m are needed)

Decoding or Recovery

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Compressed Sensing

Images and sounds have continuation Samples adjacent in time or space are highly correlated (high energy at

low frequencies) Conventional measurements are not efficient

CS recovers/predicts unobserved quantities from a few observations

t0

After acquisition at t0

Lower entropy, less information

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Compressed Silicon Sensing

In IC manufacturing, measurements are expensive IC cost = die cost + test cost + package cost

Could be applicable to pre-silicon as well (where some simulations are expensive or interpolation is used)

Automatic Test Equipment (ATE)Wafer

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Virtual Probe

Framework for wafer characterizationMany wafer test results are spatially correlated across wafer

Spatially correlated data(282 measurements)

Random 50 measurements Predicted from 50 samples1.8% Error

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Our CSS Framework

Test-items are also correlated strongly VP recover results of each test-item independentlyOur approach does it simultaneously

(0.4% Error)(12% Error)

Synthetic wafer

NormalizedFlushed delay

NormalizedLog(IDDQ)

VP’s Prediction Our Prediction

50 samples/item

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Our CSS Framework

Can decompose it into correlated variation and random variation

50 samples/item

Synthetic wafer

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Applications of CSS

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Conclusions

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Robustness is the key to success in nanometer technologiesMargins are the easiest way to obtain robustnessMargins eat up competitiveness Needs sophisticated engineering for margining (OCV, AOCV,

POCV,…) Post-silicon engineering (silicon debug, characterization, etc) is very

important under large-scale process variations Compressed Silicon Sensing

CS is a revolutionary theory Let’s take advantage of it at IC design and manufacturing!

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Q/A

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Thank you!