pravn.docx

8/14/2019 PRAVN.docx

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INDUSTRIAL TRAINING REPORT

E&C Department ,NMAMIT Page 1

Chapter 1

INTRODUCTION

COMPANY PROFILE: BCS INNOVATIONS

Philosophy:

As an Organization, our goal is to contribute to society through broad -ranging

activities in the areas of Software development and Technical Projects.

Individually, we aim to combine good citizenship with the courage to innovate

BCS Innovations is located in Bangalore, the Silicon Valley of India, where high

technology is a way of life. Since 26 thOctober 1996, BCS Innovations has successfully

performed projects under various platforms and has delivered high quality competitively

priced products and services to customers all over India.

For over 17 Years, our customers and students have inspired us to create,

manufacture and develop advanced technologies to meet the ever growing

requirements, through stringent quality expectation, hostile operating conditions and

timely targets demanded by our customers and students.

Aim:

Recent rapid development in science and technology requires co- operation

between University and industry. In response to this demand we aim to bridge and

strengthen the collaboration between them.


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Activities:

BCS Innovations bring together member organizations, Scientists and Engineers

and other leading experts to collaborate on solution to the challenges of technical

requirements. These solutions span every area of design, development, testing, and

implementation, including safety, health and environment.

The mission is to be accomplished by:

Education in core and inter disciplinary areas of technical sciences, technology and

engineering through R&D works.

Increasing public awareness of science and technology issues particularly among the

young.

Adjust flexible target oriented organizational structure to be able to rapidly respond to

new challenges and provides means for efficient technology transfer to the industry.

Our Associates Are:

BCS INNOVATIONSis one among Design Partners of Microchip[1]

Prateek Technologies, Bangalore, (2001) (www.prateektech.com)

Browseprice, Bangalore, (2013) (www.browseprice.com)

INFRASTRUCTURE:

Development Facilities

BCS Innovations with more than 8000 sq. ft. area has good facilities. The workplace is

well setup with all the latest equipments with good air, light and ventilation, thus

providing a healthy atmosphere.


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Training facilities

BCS Innovations has the modern facilities to enable a clean and transparent

interaction between the management and the staff. Good collection of technical books

are maintained in the library, supported with journals, manual and other technical

periodicals.

There are many knowledgeable and well experienced Technical Staff and

Administration Staff.

Research & Development:

The Research and Development unit continuously monitor and provide support to

the products, apart from providing innovative solutions to the customers. With the

technological advancement, the products are upgraded, thus keeping in par with the

industrial requirements.

SPECIALTIES:

BCS Innovations is a company that specializes in the development and service of

various electronic and software products. Our expertise spans a number of fields

including telecommunications, security, instrumentation and medical devices. Our

involvement in the product development process can be as little as reporting on the

feasibility of a design up to the complete project management of the product design and

manufacturing cycle. BCS can also provide specialized services such as the design and

construction of test jigs. We also provide back to base and field service of various

products. BCS INNOVATIONS is one among Design Partners of Microchip [1].

1. Design expertise

Software and Hardware

2. MCU/PIC Specialty

8bit;16bit;


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3. Analog specialty

Mixed signal; Linear; interface;

4. Market Segment Specialty

Automotive; Consumer; Home Appliances

Industrial; Medical; Telecom;

5. Application Specialty

Connectivity and networking: USB; RF; Infrared

Home and building automation: security systems and lighting control

Lighting: fluorescent

Motor control: stepper; brushed DC; AC induction;

Power supplies: analog and digital;

Utility metering: energy;

Other capabilities: audio and speech; battery management; sensors;

6. Manufacturing capabilities: outsource manufacturing;

BCS Innovations

# 86, Gokul Towers, 2nd

Floor,M.S. Ramaiah Main Road,

Gokula,Bangalore - 560054

Telephone: 080-41748280,

Mobile: 9845023627

Website: www.bcsinnovations.com

E-mail: [email protected]

[email protected]


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Chapter 2

TRAINING UNDERGONE

In BCS Innovations the training was done in four phases for about six weeks

starting from 19thAugust up to 28thSeptember.

The four phases were as follows

Advanced Digital Design

Verilog HDL

Introduction to XilinxISE FPGA Design Flow

Each phase was completed as on schedule. The introduction to advanced digital

design was carried on from 19thAugust to 24

thAugust. The very next week i.e. from 26

th

to 31stAugust training on Verilog HDL was conducted. Introduction to Xilinx ISE was

followed by the next two weeks i.e. from 2ndSeptember to 14thSeptember. The training

on FPGA Design Flow was given on fifth and sixth week of our Industrial training.

This was followed by mini project assigned to us during the last 2 weeks of our

Industrial Training.

Implementation of Booth 3 algorithm on FPGA

2.1 ADVANCED DIGITAL DESIGN

The key elements that the training focused include (1) Boolean logic, (2) logic gates

used by designers, (3) synchronous finite state machines, and (4) data path controller

designall from a perspective of designing digital systems. This focus led to elimination

of material more suited for a course in electronics. Additionally, the widespread

availability of web based ancillary material prompted us to limit our discussion of field


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programmable gate arrays (FPGAs) to an introduction of devices offered by only one

manufacturer, rather than two.

2.1.1 Sections covered

Digital Systems And Binary Numbers

Boolean Algebra And Logic Gates

Gate Level Minimization

Combinational Logic

Synchronous Sequential Logic

Registers And Counters

Memory And Programmable Logic

Design At Register Transfer Level

2.2.2 Summary of each Section

a)Digital Systems and Binary Numbers:

This section presented the various binary systems suitable for representing

information in digital systems. The binary number system was explained and binary

codes were illustrated.

b) Boolean algebra and Logic Gates:

This section presented the basic postulates of Boolean algebra and shows the

correlation between Boolean expressions and their corresponding logic diagrams. All

possible logic operations for two variables are investigated, and the most useful logic

gates used in the design of digital systems were identified.

c) Gate Level Minimization

This section covered the map method for simplifying Boolean expressions and

the map method is also used to simplify digital circuits constructed with AND OR,

NAND, or NOR gates. All other possible twolevel gate circuits are considered, and their

method of implementation was explained.


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d) Combinational Logic

This section outlined the formal procedures for the analysis and design of

combinational circuits. Some basic components used in the design of digital systems,

such as adders and code converters, are introduced as design examples. Frequently

used digital logic functions such as parallel adders and subtractors, decoders,

encoders, and multiplexers are explained, and their use in the design of combinational

circuits were illustrated

e) Synchronous Sequential Logic

This section outlined the formal procedures for analyzing and designing clocked

(synchronous) sequential circuits. The gate structure of several types of flip

flops waspresented together with a discussion on the difference between level and edge

triggering. Specific examples were used to show the derivation of the state table and

state diagram when analyzing a sequential circuit. A number of design examples were

presented with emphasis on sequential circuits that use Dtype flipflops

f) Registers and Counters

This section dealt with various sequential circuit components such as registers,

shift registers, and counters. These digital components are the basic building blocks

from which more complex digital systems are constructed

g) Memory and Programmable Logic

This section dealt with random access memory (RAM) and programmable logic

devices. Memory decoding and error correction schemes were discussed.

Combinational and sequential programmable devices such as ROMs, PLAs, PALs,

CPLDs, and FPGAs were presented.

h) Design at Register Transfer Level

This section dealt with the register transfer level (RTL) representation of digital systems.


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The algorithmic state machine (ASM) chart was introduced. A number of examples

demonstrated the use of the ASM chart and RTL representation.

2.2 VERILOG HDL

The digital designers use hardware description languages (HDLs) to design digital

systems. The most widely used HDLs are VHDL and Verilog. Verilog HDL is one of the

most common Hardware Description Languages (HDL) used by integrated circuit (IC)

designers.HDLs allows the design to be simulated earlier in the design cycle in order to

correct errors or experiment with different architectures. Designs described in HDL are

technology-independent, easy to design and debug, and are usually more readable thanschematics, particularly for large circuits.

Both of these hardware description languages allow the user to design digital

systems by writing a program that describes the behavior of the digital circuit. The

program can then be used to both simulate the operation of the circuit and synthesize

an actual implementation of the circuit in a CPLD, an FPGA, or an application specific

integrated circuit (ASIC). Another trend is to design digital circuits using block diagrams

or graphic symbols that represent higher-level design constructs. These block diagrams

can then be compiled to produce Verilog or VHDL code.

Verilog is based on the C programming language but it is not C. Verilog is a

hardware description language that is designed to model digital logic circuits. It simply

has the same syntax as the C programming language but the way it behaves is

different.

Verilog can be used to describe designs at four levels of abstraction:

Algorithmic level (much like c code with if, case and loop statements).

Register transfer level (RTL uses registers connected by Boolean equations).

Gate level (interconnected AND, NOR etc.).


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Switch level (the switches are MOS transistors inside gates).

The language also defines constructs that can be used to control the input and output of

simulation.

More recently Verilog is used as an input for synthesis programs which will

generate a gate-level description (a net list) for the circuit. Some Verilog constructs are

not synthesizable. Also the way the code is written will greatly affect the size and speed

of the synthesized circuit.

2.2.1 Sections covered

Hierarchical Modeling Concepts

Basic Concepts

Modules And Ports

Gate Level Modeling

Dataflow Modeling

Behavioral Modeling

Tasks And Functions


a)Hierarchical modeling concepts

This section presented good understanding on top-down and bottom-up design

methodologies for digital design, differences between modules and module instances in

Verilog and described the components required for the simulation of a digital design by

defining a stimulus block and design block.

b) Basic concepts

This section briefed us on lexical conventions for operators, comments,

whitespace, numbers string and identifiers. Defined the logic value set and data types,

such as nets, registers, vectors, numbers, simulation time, arrays, parameters,


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memories, strings and tasks for displaying, monitoring, stopping and finishing the

simulation.

c) Modules and ports

This section dealt with identifying the components of a Verilog module definition

and understanding on how to define the port list for a module and declare it in Verilog. It

also covered theport connection rules in a module instantiation.

d) Gate level Modeling

This section covered on identifying logic gate primitives, understanding

instantiation of gates, gate symbols, and truth tables and constructing a Verilog

description from the logic diagram of the circuit.

e) Dataflow Modeling

This section described the continuous assignment statement, restrictions on

assign statement and the implicit continuous assignment statement. It also covered

assignment delay, implicit assignment delay, and net declaration delay for continuous

assignment statements, expressions, operators and operands.

f) Behavioral modeling

This section covered the significance of structured procedures always and initial

in behavioral modeling. Understanding of blocking and non-blocking procedural

assignments, delay based timing control mechanisms, event based timing control

mechanism, conditional statements using if and else and multi ways branching using

case, casex and casez statements. Understanding of looping statements such as while,

for, repeat and forever, sequential and parallel blocks, naming of blocks and disabling of

named blocks.

g) Tasks and functions

This section briefed on differences between tasks and function, task declaration

and invocation, function declaration and invocation.


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2.3 Introduction to Xilinx ISE

Xilinx ISE(Integrated Software Environment) is a software tool produced

byXilinx for synthesis and analysis ofHDL designs, enabling the developer

tosynthesize ("compile") their designs, performtiming analysis,examineRTL diagrams,

simulate a design's reaction to different stimuli, and configure the target device with

theprogrammer.

The Web Edition is a free version of Xilinx ISE that can be downloaded at no

charge. It provides synthesis and programming for a limitednumberofXilinx devices. In

particular, devices with a large number of I/O pins and large gate matrices are disabled.

The low-cost Spartan family ofFPGAs is fully supported by this edition, as well as the

family ofCPLDs, meaning small developers and educational institutions have no

overheads from the cost of development software.

2.3.1Starting the ISE Design Suite

To start the ISE Design Suite, double-click the Project Navigator icon on your

desktop, or select Start > All Programs > Xilinx ISE Design Suite > Xilinx Design Suite

14 > ISE Design Tools > Project Navigator.

2.3.2 Creating a New Project

To create a new project using the New Project Wizard, do the following:

1. From Project Navigator, select File > New Project.

2. In the Location field, browse to c:\xilinx_tutorial or to the directory in which

You installed the project.

3. In the Name field, enter wtut_vhd or wtut_ver.

4. Verify that HDL is selected as the Top-Level Source Type, and click next.

The New Project Wizard appears.

The New Project WizardDevice Properties page appears.
http://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Programmer_(hardware)http://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Field-programmable_gate_arrayhttp://en.wikipedia.org/wiki/Complex_programmable_logic_devicehttp://en.wikipedia.org/wiki/Complex_programmable_logic_devicehttp://en.wikipedia.org/wiki/Field-programmable_gate_arrayhttp://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Programmer_(hardware)http://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Xilinx


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5. Select the following values in the New Project WizardDevice Properties

page:

Product Category: All

Family: Spartan3

Device: XC3S500E

Package: FG484

Speed: -4

Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISim (VHDL/Verilog)

Preferred Language: VHDL or Verilog depending on preference. This will

determine the default language for all processes that generate HDL files. Other

properties can be left at their default values.

5. Click next, then Finish to complete the project creation

2.3.3 Creating an HDL-Based Module

With the ISE Design Suite, you can easily create modules from HDL code using

the ISE Text Editor. The HDL code is then connected to your top-level HDL design

through instantiation and is compiled with the rest of the design. In this section, you

create a file using the New Source wizard, specifying the name and ports of the

component. The resulting HDL file is then modified in the ISE Text Editor.

To create the source file, do the following:

1. Select Project > New Source.

2. In the Select Source Type page, select VHDL Module or Verilog Module.


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3. In the File Name field, enter debounce.

4. Click Next.

5. In the Define Module page, enter two input ports named sig_in and clk and an

output port named sig_out for the debounce component as follows:

a. In the first three Port Name fields, enter sig_in, clk and sig_out.

b. Set the Direction field to input for sig_in and clk and to output for sig_out.

c. Leave the Bus designation boxes unchecked.


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6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.W

2.4 FPGA DESIGN FLOW

A fieldprogrammable gate array (FPGA) is a VLSI circuit that can be

programmed at the users location. A typical FPGA consists of an array of millions of

logic blocks, surrounded by programmable input and output blocks and connected

together via programmable interconnections. There is a wide variety of internal

configurations within this group of devices. The performance of each type of device

depends on the circuit contained in its logic blocks and the efficiency of its programmed

interconnections.


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A typical FPGA logic block consists of lookup tables, multiplexers, gates, and

flipflops. A lookup table is a truth table stored in an SRAM and provides the

combinational circuit functions for the logic block. These functions are realized from the

lookup table, in the same way that combinational circuit functions are implemented with

ROM [5].

2.4.1 Sections Covered

Xilinx FPGA

Basic Xilinx Architecture

Xilinx Spartan 3 FPGAs

FPGA Kit Interfacing And Configuration

FPGA Design Flow


a) Xilinx FPGA

Xilinx launched the worlds first commercial FPGA in 1985, with the vintage

XC2000 device family. 2 The XC3000 and XC4000 families soon followed, setting the

stage for todays Spartan, and Virtex device families.

Each evolution of devices brought improvements in density, performance, power

consumption, voltage levels, pin counts, and functionality. For example, the Spartan

family of devices initially offered a maximum of 40K system gates, but todays Spartan6

offers 150,000 logic cells plus 4.8Mb block RAM, Artex-7 offers 24,000 logic blocks,

Kintex-7 offers 480,000 logic blocks,Virtex-7 offers 2,000,000 logic blocks [2].

b) Basic Xilinx Architecture

The basic architecture of Spartan and earlier device families consists of an array

of configurable logic blocks (CLBs), a variety of local and global routing resources, and

inputoutput (I/O) blocks (IOBs), programmable I/O buffers, and an SRAMbased

configuration memory, as shown in Fig. 2.4.1


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Fig 2.4.1: Basic architecture of Xilinx Spartan

c) Xilinx Spartan-3 FPGAs

The Spartan-3E family builds on the success of the earlier\Spartan-3 family by

increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New

features improve system performance and reduce the cost of configuration. These

Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology,

deliver more functionality and bandwidth per dollar than was previously possible, setting

new standards in the programmable logic industry [4]. Summary of Spartan-3E FPGA

Attributes is given in table 2.4.1

The Spartan-3E family architecture consists of five fundamental programmable

functional elements.

Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that

implement logic plus storage elements used as flip-flops or latches. CLBs perform a

wide variety of logical functions as well as store data.


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Input/output Blocks (IOBs) control the flow of data between the I/O pins and the

internal logic of the device. Each IOB supports bidirectional data flow plus 3-state

operation. Supports a variety of signal standards including four high-performance

differential standards. Double Data-Rate (DDR) registers are included.

Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.

Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for

distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

Device System

Gates

Equivalent

Logic Cells

Max RAM

Bits

DCMs Max I/O

XC3S100E 100K 2,160 72K 2 108

XC3S250E 250K 5,508 216K 4 172

XC3S500E 500K 10,476 360K 4 232

XC3S1200E 1200K 19,512 504K 8 304

XC3S1600E 1600K 33,192 648K 8 376

Table 2.4.1: Summary of Spartan-3E FPGA Attributes

d) FPGA Kit Interfacing and Configuration

Configuration: Spartan-3E FPGAs are programmed by loading configuration data

into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively

control all functional elements and routing resources. The FPGAs configuration data is

stored externally in a PROM or some other non-volatile medium, either on or off the

board. After applying power, the configuration data is written to the FPGA.

LCD Initialization, Configuration and Display

The LCD (Liquid Crystal Display) is included with the Spartan-3E Starter Board

Kit sold by both Digilent. There are three main steps in using the display, the first being


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the initialization of the four bit interface itself, the second being the commands to set the

display options and the third being the writing of character data.

Process:

1. Implement hardware to control the LCD.

2. Verify the hardware in software (Xilinx ISE 14.6).

3. Program the S3-E Starter Kit Board.

Fig 2.4.2 FPGA design flow

Design EntryDesign Implementation

Design Verification

FPGA Configuration


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Chapter 3

MINI PROJECT

Efficient FPGA Implementation of Advanced Multiplier(Booth 3)

3.1 Booths Algorithm:

The purpose of this project is to present a method of implementing high speed

binary multiplication. A generator that creates a smaller number of partial products will

allow the partial product summation to be faster and use less hardware.

Fig 1: Booth 3 multiplier.

Fig 1 shows the logical architecture of Booth-3 multiplier. These circuits include a

Partial-Product-Generator (PPG) and adders.A recoding scheme introduced by Booth

reduces the number of partial products by about a factor of two. The Booth 3 decoder

and partial product selection logic is shown in fig 2.


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Fig 2: Booth 3 decoder and partial product selector logic.

Fig 3: Booth-3 dot diagram and Partial Product Selection table

A Booth 3 dot diagram is shown in Fig 3, and an example is shown in Fig 4. The

multiplier is partitioned into overlapping groups of 4 bits, and each group is decoded to

select a single partial product as per the selection table. Each partial product could be


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from the set {0, M, 2M, 3M, 4M}. All multiples with the exception of 3M are easily

obtained by simple shifting and complementing of the multiplicand.

Fig 4: 16-bit booth 3 example.

3.2 Simulation results:

The Booth-3 algorithm is coded using VHDL-Verilog and simulation is performed

using Xilinx ISE design suite version 14.6.The simulation result for the example shown

in fig 4 is as follows.


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3.3 Conclusion:

The simplest partial product generator produces N partial products, where N is

the length of the input operands. By the use of Booth-3 algorithm the number of partial

products gets reduced by about a factor of two. Since the amount of hardware and the

delay depends on the number of partial products to be added, this may reduce the

hardware cost and improve performance.


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E&C Department NMAMIT Page 23

REFERENCES

[1] microchip.newanglemedia.com/partner_matrix/

[2] M. Morris Mano and Michael D. Cilett, Digital Design, 5thedition

[3] Smair Palnitkar, Verilog HDL, A guide to Digital Design and Synthesis,

[4] xilinx.com/products/silicon-devices/fpga/spartan-3.html

[5] James O.Hamken, Tyson S. Hall, Michael D.Furman, Rapid prototyping of digital

Systems
http://microchip.newanglemedia.com/partner_matrix/http://www.xilinx.com/products/silicon-devices/fpga/spartan-3.htmlhttp://www.xilinx.com/products/silicon-devices/fpga/spartan-3.htmlhttp://microchip.newanglemedia.com/partner_matrix/

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