practical analog design techniques

7/31/2019 Practical Analog Design Techniques

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SECTION 1

SINGLE-SUPPLY AMPLIFIERS

Rail-to-Rail Input Stages

Rail-to-Rail Output Stages

Single-Supply Instrumentation Amplifiers


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SECTION 1

SINGLE-SUP P LY AMP LIF IER S

A d ol fo Ga r cia

Over th e last several years, single-supply operat ion ha s become a n increa singly

import an t requirem ent a s systems get sma ller, cheaper , and more port able.

Port able systems r ely on batt eries, and t otal circuit power consu mpt ion is an

import an t a nd often dominan t design issue, an d in some insta nces, more import an t

th an cost. This ma kes low-volta ge/low supply cur ren t opera tion critical; at th e sam e

time, however, accur acy and precision requiremen ts h ave forced IC man ufactur ers

to meet th e challenge of doing more wit h less in t heir am plifier designs.

SINGLE-SUPPLY AMPLIFIERS

Single Supply Offers:Lower PowerBattery Operated Portable EquipmentSimplifies Power Supply Requirements

But Watch Out for:Signal-swings limited, therefore more sensitiveto errors caused by offset voltage, bias current,finite open-loop gain, noise, etc.More likely to have noisy power supply becauseof sharing with digital circuitsDC coupled, multi-stage single-supply circuitscan get very tricky!

Rail-to-rail op amps needed to maximize signalswings

In a single-supp ly applicat ion, th e most immedia te effect on t he per form an ce of an

am plifier is the r educed input an d output signa l ran ge. As a result of these lower

inpu t a nd outpu t signa l excursions, amplifier circuits become more sen sitive to

inter na l an d extern al er ror sources. Precision am plifier offset voltages on t he order

of 0.1mV ar e less th an a 0.04 LSB err or source in a 12-bit, 10V full-scale system . In

a single-supply system, however, a "rail-to-rail" precision amplifier with an offset

volta ge of 1mV repr esent s a 0.8LSB err or in a 5V FS system , and 1.6LSB err or in a

2.5V FS syst em.

Fu rt her more, amplifier bias curren ts, now flowing in lar ger sour ce resista nces tokeep curr ent d ra in from t he bat ter y low, can genera te offset errors equa l to or

grea ter th an th e am plifiers own offset volta ge.

Gain accuracy in some low voltage single-supply devices is also reduced, so device

selection needs car eful considera tion. Many a mplifiers h aving open-loop gains in th e

millions typically opera te on dua l supplies: for example, t he OP07 family types.

However, ma ny single-supply/rail-to-ra il am plifiers for precision a pplicat ions


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typically ha ve open-loop gains between 25,000 an d 30,000 under light loadin g

(>10kohm). Selected devices, like t he OPX13 fam ily, do ha ve high open-loop ga ins

(i.e., >1V/V).

Man y tra de-offs ar e possible in t he design of a single-supply amplifier: speed versu s

power, n oise versus power, pr ecision versus speed a nd power, etc. Even if the n oise

floor r ema ins const an t (highly unlikely), the signa l-to-noise rat io will drop as t he

signa l am plitude decreases.

Besides th ese limitat ions, ma ny other design considerat ions t ha t a re otherwise

minor issues in du al-supply amplifiers become import an t. For exam ple, signal-to-

noise (SNR) perform an ce degra des a s a resu lt of reduced signal swing. "Ground

referen ce" is n o longer a simple choice, as one r eferen ce volta ge ma y work for some

devices, but n ot other s. System n oise increa ses as operat ing supply cur rent drops,

an d ban dwidth decreases. Achieving adequat e ban dwidth an d r equired precision

with a somewhat limited selection of amplifiers pr esent s significan t syst em design

challenges in single-supply, low-power applications.

Most circuit designers take "ground" reference for granted. Many analog circuits

scale their input an d out put r an ges about a ground r eference. In du al-supply

app licat ions, a r eferen ce th at splits th e supplies (0V) is very convenient , as th ere is

equa l supply head room in ea ch direction, an d 0V is genera lly th e volta ge on t he low

impedance groun d plane.

In single-supply/rail-to-rail circuits, however, the ground reference can be chosen

an ywhere with in the su pply ra nge of th e circuit, since ther e is no sta nda rd t o

follow. The choice of groun d refer ence depen ds on th e type of signa ls processed an d

th e am plifier char acteristics. For example, choosing the negative ra il as t he ground

reference may optimize th e dynam ic ra nge of an op amp whose out put is designed

to swing to 0V. On th e other h an d, the signal m ay require level shifting in order t obe compa tible with th e input of other d evices (such as ADCs) th at ar e not designed

to operat e at 0V input.

"RAIL-TO-RAIL" AMPLIFIERS

What exactly is rail-to-rail

Does the input common mode range (for guaranteedCMMR) include: 0V, +Vs, both, or neither?

Output Voltage Swing (how close to the rails can you getunder load?)

Where is ground?

Complementary bipolar processes make rail-to-rail inputsand outputs feasible (within some fundamental physicallimitations)

Implications for precision single-supply instrumentationamps


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Ea rly sin gle-supp ly zero-in, zero-out am plifiers were designed on bipolar processes

which optimized the performa nce of th e NPN t ra nsistors. The PNP t ra nsistors were

either lateral or substra te PNP s with much poorer performa nce than t he NPNs.

Fu lly complement ar y processes a re now required for th e new-breed of single-

supp ly/ra il-to-ra il opera tional a mplifiers. These n ew am plifier designs do not u se

lateral or substra te PNP tra nsistors within the signal path , but incorporate par allel

NPN and PNP input st ages to accommodate input signal swings from groun d to the

positive supply rail. Fur th erm ore, ra il-to-rail out put sta ges are designed with bipolar

NP N a nd PNP common-emitter , or N-cha nn el/P-cha nn el comm on-sour ce am plifiers

whose collector-emitter sat ur at ion voltage or dr ain-sour ce cha nn el on-resistan ce

determ ine outpu t signal swing with t he load curr ent.

The cha ra cteristics of a sin gle-supp ly amplifier in put sta ge (comm on-mode rejection,

inpu t offset volta ge and it s tem pera tu re coefficient, a nd n oise) are critical in

precision, low-voltage applications. Rail-to-rail input operational amplifiers must

resolve small signals, whether their inputs a re a t ground, or at the amplifiers

positive su pply. Amplifiers ha ving a minim um of 60dB comm on-mode r ejection overthe entire input common-mode voltage range from 0V to the positive supply (VPOS )

ar e good candidat es. It is n ot necessar y tha t amplifiers ma intain common-mode

rejection for signa ls beyond t he su pply volta ges: wha t is requ ired is th at th ey do not

self-destr uct for momenta ry overvolta ge conditions. F ur th ermore, a mplifiers t ha t

ha ve offset volta ges less tha n 1m V and offset volta ge drifts less tha n 2V/C are

also very good candidates for precision applications. Since inpu t signa l dyna mic

ra nge and SNR ar e equally if not more importan t th an output dynamic ra nge and

SNR, pr ecision single-supply/ra il-to-ra il opera tional a mplifiers sh ould ha ve noise

levels referr ed-to-inpu t (RTI) less th an 5Vp-p in t he 0.1Hz to 10Hz ban d.

Since the need for rail-to-rail amplifier output stages is driven by the need to

ma inta in wide dyna mic ra nge in low-supply voltage a pplicat ions, a single-supply/ra il-to-ra il am plifier should ha ve out put voltage swings which a re with in at least 100mV

of either supp ly ra il (under a n omina l load). The outpu t volta ge swing is very

dependent on out put sta ge topology and load cur rent , but the voltage swing of a

good output sta ge should ma inta in its r at ed swing for loads down t o 10kohm. The

smaller the VOL and th e larger the VOH , the better. System par ameters, such a s

zero-scale or full-scale output volta ge, should be det ermin ed by an am plifiers

VOL (for zer o-scale) an d VOH (for full-scale).

Since the m ajority of single-supply dat a a cquisition systems r equire a t least 12- to

14-bit perform an ce, am plifiers which exhibit an open-loop gain grea ter th an 30,000

for a ll load ing cond itions a re good choices in precision ap plicat ions .

S INGLE-S U P P L Y/R AIL-TO-RAI L OP AMP IN P U T S TAGES

With t he in creasin g emph asis on low-volta ge, low-power, a nd single-supp ly

opera tion, ther e is some dema nd for op am ps whose input comm on-mode ran ge

includes both supply rails. Such a feature is undoubtedly useful in some

applicat ions, but engineers should recognize th at ther e ar e relat ively few

applications wh ere it is a bsolutely essentia l. These should be car efully distingu ished


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from t he ma ny applicat ions wh ere comm on-mode ran ge close to the supplies or one

tha t includes one of the supplies is necessar y, but input ra il-ra il opera tion is not.

In m an y single-supply applicat ions, it is requir ed th at th e input go to only one of th e

supply r ails (usua lly ground ). Amplifiers wh ich will ha ndle zero-volt inpu ts ar e

relatively easily designed using either PNP transistors (see OP90 and the OPX93 in

Figur e 1.3) or N-cha nn el JF ETs (see AD820 fam ily in Figur e 1.4). P-cha nn el JF ETs

can be used wher e inputs must include the positive supply ra il (but not th e negative

ra il) as s hown in F igure 1.4 for th e OP282/OP482.

OP90 AND OPX93 INPUT STAGE ALLOWSINPUT TO GO TO THE NEGATIVE RAIL

Figure 1.3

In t he F ET-input st ages of Figur e 1.4, the possibility exists for ph ase r eversal as

inpu t signa ls appr oach a nd exceed th e am plifiers linea r inpu t comm on-mode

volta ge ran ges. As described in Section 7, inter na l amplifier sta ges satu ra te, forcing

subsequent sta ges int o cutoff. Depending on th e str uctur e of the input st age, phase

reversa l forces the outpu t volta ge to one of th e supply ra ils. For n-cha nn el JF ET-

input stages, the output voltage goes to the negative outpu t r ail during phase

reversal. For p-cha nnel J FE T-input sta ges, th e output is forced to the positive

output ra il. New F ET-inpu t a mplifiers, like t he AD820 fam ily of amplifiers,

incorporat e design impr ovements t ha t pr event out put voltage pha se reversal for

signa ls within th e ra ted supply voltage ran ge. Their input sta ge and second gain

sta ge even offer pr otection a gainst outpu t voltage pha se reversa l for input signa ls

200mV more positive th an th e positive supply voltage.


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AD820/AD822/AD824 INPUT INCLUDES NEGATIVE RAIL,OP-282/OP-482 INCLUDES POSITIVE RAIL

Figure 1.4

As shown in Figur e 1.5, tru e ra il-to-ra il input sta ges require two long-tailed pairs,

one of NPN bipolar tr an sistors (or N -cha nn el FETs), the other of PNP tr an sistors

(or p-chan nel FE Ts). These t wo pair s exhibit differentoffsets a nd bias curr ents, so

when the applied input common-mode voltage changes, the amplifier input offset

voltage an d input bias curren t does also. In fact, when both cur rent sour ces (I1 and

I2) remain a ctive thr oughout t he ent ire input common-mode ra nge, amplifier input

offset volta ge is th e average offset voltage of the NP N pa ir an d th e PNP pair. In

th ose designs wher e the curr ent sour ces ar e altern at ively switched off at some

point along th e inpu t common-mode volta ge, amplifier in put offset volta ge is

dominat ed by th e PNP pair offset voltage for signa ls near th e negat ive supply, and

by the N PN pair offset voltage for signa ls nea r t he positive supply.

Amplifier inpu t bias curr ent , a fun ction of tr an sistor curr ent gain, is also a function

of th e app lied input comm on-mode volta ge. The resu lt is rela tively poor comm on-

mode rejection (CMR), an d a changing common-mode inpu t impedan ce over t he

comm on-mode input volta ge ra nge, compa red t o familiar du al su pply precision

devices like th e OP07 or OP97. Th ese specificat ions should be considered car efully

when choosing a r ail-rail input op amp, especially for a non-invertin g configura tion.

In put offset volta ge, inpu t bias cur ren t, an d even CMR ma y be quite good over par t

of th e comm on-mode ran ge, but mu ch worse in t he r egion wh ere operat ion sh ifts

between the NP N an d PNP devices.


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RAIL-TO-RAIL INPUT STAGE TOPOLOGY

Figure 1.5

Man y rail-to-rail amplifier inpu t st age designs switch opera tion from one differentia l

pair to the oth er different ial pair somewher e along the input common-mode voltage

range. Devices like the OPX91 family and the OP279 have a common-mode

crossover t hr eshold at app roxima tely 1V below th e positive supply. In t hese devices,

the PNP differential input stage remains active; as a result, amplifier input offset

voltage, input bias current, CMR, input noise voltage/current are all determined by

th e char acteristics of th e PN P differen tial pa ir. At t he crossover th reshold, however,

am plifier inpu t offset volta ge becomes th e aver age offset volta ge of the NP N/PNPpair s an d can chan ge rapidly. Also, am plifier bias cur ren ts, dominat ed by th e PNP

different ial pair over most of the inpu t common-mode ra nge, cha nge polar ity an d

ma gnitude a t t he crossover thr eshold when t he NP N different ial pair becomes

active. As a r esult , sour ce impeda nce levels should be balan ced when usin g such

devices, as men tioned before, to minim ize inpu t bias cur ren t offsets an d distort ion.

An advant age to this type of ra il-to-ra il input s ta ge design is tha t inpu t sta ge

tra nsconductance can be m ade consta nt thr oughout the entire input common-mode

voltage r an ge, and t he a mplifier slews symmetr ically for a ll applied signals.

Opera tiona l am plifiers, like t he OP 284/OP484, utilize a ra il-to-rail input sta ge design

where both PNP and NP N tr ansistor pa irs are a ctive thr oughout the entire inputcomm on-mode volta ge ra nge, an d t her e is n o common-mode crossover th resh old.

Amplifier inpu t offset volta ge is th e avera ge offset volta ge of th e NPN an d th e PNP

stages. Amplifier input offset voltage exhibits a smooth transition throughout the

ent ire inpu t comm on-mode voltage r an ge becau se of careful laser-trimm ing of

resistors in t he input st age. In t he same man ner, thr ough careful input sta ge

curr ent balan cing and input tra nsistor design, amplifier input bias cur rents also

exhibit a smooth tr an sition t hr oughout t he ent ire common-mode input volta ge

ra nge. The exception occurs a t t he extr emes of th e input common-mode ran ge,


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where a mplifier offset volta ges and bias curren ts increa se sha rply due t o the slight

forwa rd-biasing of par asitic p-n junctions. This occurs for input voltages within

appr oximately 1V of eith er su pply rail.

When both different ial pairs a re a ctive thr oughout t he ent ire input common-mode

ra nge, amplifier tr an sient response is fast er th rough th e middle of th e common-

mode ra nge by as mu ch as a factor of 2 for bipolar inpu t st ages a nd by a factor of

th e squar e root of 2 for F ET input sta ges. Inpu t sta ge tran scondu cta nce determines

th e slew rat e an d th e un ity-gain crossover frequency of the a mplifier, hence

response time degra des slightly at t he extr emes of th e input common-mode ra nge

when either t he PN P sta ge (signa ls approaching VPOS ) or t he NP N sta ge (signals

appr oaching GND) are forced into cutoff. The t hr esholds a t which th e

transconductance changes occur approximately within 1V of either supply rail, and

the behavior is similar to tha t of the inpu t bias curr ents.

Applicat ions wh ich init ially appea r t o require tr ue r ail-ra il inpu ts sh ould be carefully

evaluated, an d th e am plifier chosen to ensure t ha t its input offset voltage, input bias

curren t, comm on-mode r ejection, and noise (voltage a nd cur ren t) ar e suita ble. Atr ue r ail-to-ra il inpu t a mplifier should not genera lly be used if an input ra nge which

includes only one ra il is sat isfactory.

S INGLE-S U P P L Y/R AIL-TO-RAI L OP AMP OU TP U T S TAGES

The ear liest IC op amp outpu t sta ges were NPN emitter followers with NPN cur rent

sources or resistive pull-downs, as shown in Figure 1.6. Naturally, the slew rates

were gr eat er for positive-going th an for n egat ive-going signals. While all modern op

am ps ha ve push-pull outpu t st ages of some sort, ma ny ar e still asymmetr ical, and

ha ve a grea ter slew rat e in one direction th an th e oth er. This asymmetr y, which

generally results from the u se of IC processes with better N PN t ha n P NP

tr an sistors, ma y also result in th e ability of the outpu t t o approach one supply more

closely th an th e oth er.

In m an y applicat ions, th e out put is required t o swing only to one rail, usua lly th e

negat ive rail (i.e., ground in single-supply system s). A pulldown r esistor to th e

negat ive ra il will allow the outpu t t o appr oach t ha t r ail (provided th e load impeda nce

is high enough, or is also groun ded to th at ra il), but only slowly. Using an FE T

current sour ce instead of a r esistor can speed t hings up, but this a dds complexity.


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OP AMP OUTPUT STAGES USINGCOMPLEMENTARY DEVICES ALLOW PUSH-PULL DRIVE

Figure 1.6

An IC process with rela tively well-mat ched (AC an d DC) PN P a nd NP N tr an sistors

allows both th e output voltage swing and slew rat e to be rea sona bly well matched.

However, an outpu t stage u sing BJTs can not swing completely to th e ra ils, but only

to within t he tr an sistor sa tur at ion voltage (VCESAT) of the r ails (see Figur e 1.7).

For sma ll amoun ts of load curr ent (less than 100A), the sa tur at ion volta ge may be

as low as 5 to 10mV, but for h igher load curr ents, th e sat ur at ion volta ge can

increase to several hundred mV (for example, 500mV at 50mA).

On th e oth er ha nd, an outpu t sta ge const ru cted of CMOS FETs can pr ovide tru e

rail-to-rail performance, but only under no-load conditions. If the output must

sour ce or sink curr ent, t he outpu t swing is redu ced by the voltage dropped across

th e FE Ts inter na l "on" resista nce (typically, 100ohm s).


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RAIL-TO-RAIL OUTPUT STAGE SWINGIS LIMITED BY Vcesat, Ron, AND LOAD CURRENT

Figure 1.7

In sum ma ry, th e following point s should be consider ed when selecting a mplifiers for

single-supply/ra il-to-ra il a pplicat ions:

First, input offset voltage and inpu t bias currents can be a fu nction of the applied

inpu t com m on-m ode voltage (for true rail-to-rail inpu t op am ps). Circuits usin g this

class of am plifiers sh ould be designed to minimize resu lting err ors. An inver ting

am plifier configura tion with a false ground r eference at th e non-invert ing input

prevent s th ese err ors by holding th e input common-mode voltage const an t. If the

inverting amplifier configuration cannot be used, then amplifiers like the

OP284/OP484 which do not exhibit an y common-mode crossover th res holds should

be used.

S econd , since inpu t bias currents are not always sm all and can exhibit different

pola ri t ies, source im ped ance lev els sh ou ld be carefu ll y m atch ed to m in im iz e

add itional inpu t bias current-indu ced offset voltages an d increased d istortion .

Again, consider using amplifiers that exhibit a smooth input bias current transition

th roughout t he a pplied input common-mode voltage.

T hird , rail-to-rail am plifier output stages exhibit load-dependent gain wh ich

affects am plifier open-loop gain , an d h ence closed-loop gain a ccura cy. Amplifiers

with open-loop gains grea ter tha n 30,000 for resistive loads less tha n 10kohm a regood choices in precision applications. For applications not requiring full rail-rail

swings, device fam ilies like th e OPX13 and OPX93 offer DC ga ins of 0.2V/V or

more.

Last ly , no m atter what claim s are m ade, ra il -to-rail ou tpu t volt age sw in gs are

fun ct ion s of th e a m pli fi ers ou tpu t stage d evices an d load cu rren t. The satu ra tion

volta ge (VCESAT), satu ra tion resistance (RSAT), an d load curr ent a ll affect the

am plifier outpu t volta ge swing.


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These consider at ions, as well as t hose regar ding ra il-to-ra il precision, ha ve

implicat ions in m an y circuits, nam ely instr um ent at ion a mplifiers, which will be

covered in th e next sections.

T H E T WO OP AMP INSTRUMENTATION AMPLIFIERT OPOLOGY

Ther e ar e several circuit topologies for instr um ent at ion a mplifier circuits su itable

for single-supply applications. The two op am p configura tion is often used in cost-

an d spa ce-sensitive applications, where t ight ma tching of input offset voltage, input

bias currents, and open-loop gain is important. Also, when compared to other

topologies, the t wo op amp inst ru men ta tion am plifier circuit offers t he lowest power

consu mpt ion an d low total drift for modera te-gain (G=10) applicat ions. Obviously, it

also has t he mer it of using a single dual op amp IC.

Figur e 1.8 shows th e topology of a t wo op amp inst ru men ta tion circuit wh ich u ses a

5th gain-setting r esistor, RG. This a dditiona l gain-sett ing resistor is optiona l, and

should be used in t hose applicat ions wh ere a fine gain t rim is r equired. Its effect will

be included in th is ana lysis.

Circuit r esistor values for t his topology can be deter mined from Equ at ions 1.1

th rough 1.3, where R1 = R4. To ma int ain low power consu mpt ion in sin gle-sup ply

app licat ions, values for R sh ould be no less tha n 10kohms:

R1 = R4 = R Eq. 1.1

R2 = R3 =R

0.9G 1

Eq. 1.2

RG =2R

0.06GEq. 1.3

where G equa ls the desired circuit gain. Note tha t in those applicat ions wher e fine

gain tr imming is not required, Eq. 1.2 redu ces to:

R2 = R3 =R

G1Eq. 1.4

A nodal a na lysis of the topology will illust ra te th e beha vior of th e circuits n odalvoltages an d th e am plifier output cur rent s a s functions of the a pplied common-

mode input voltage (VCM), the applied differential (signal) voltage (VIN), and th e

outpu t r eferen ce volta ge (VRE F). These expressions a re su mma rized in E quat ions

1.5 thr ough 1.8, Eq. 1.12, and in E q. 1.13 for positive, inpu t d ifferen tial volta ges. Due

to th e str uctur e of th e topology, expressions for voltages a nd cur rent s a re similar in

form and magnitude for negative, input differential voltages.


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Fr om th e figur e, expressions for t he four nodal volta ges A, B, C, an d VOU T as well

as t he output sta ge cur rent s of A1 (IOA1 ) and A2 (IOA2) ha ve been d eveloped. Note

th at th e direction of the amplifier out put cur rent s, IOA1 and IOA2 , is defined to be

in to th e amp lifiers out put sta ge. For exam ple, if th e nodal ana lysis shows tha t IOA1and IOA2 ar e positive entit ies, their direction is in to th e device; th us, th eir outpu t

stages are s inking cur rent . If th e ana lysis shows th at t hey are negative quan tities,

th eir direction is opposite to tha t sh own; therefore, th eir out put sta ges are sourcing

current .

Resistors RP1 and RP2 at the input s to the circuit a re optional input curr ent limiting

resistors used t o protect th e am plifier input stages a gainst input overvoltage.

Although an y reasonable value can be used, these r esistors sh ould be less than

1kohm to prevent t he u nwan ted effects of additiona l resistor noise an d bias

curr ent -gener at ed offset volta ges. For protection again st a specific level of

overvoltage, th e int erest ed r eader should consu lt t he s ection on overvoltage effects

on int egra ted circuits , found in Section 7 of this book.

THE TWO OP AMP INSTRUMENTATION AMPLIFIERTOPOLOGY IN SINGLE-SUPPLY APPLICATIONS

Figure 1.8

Using h alf-circuit concepts a nd t he pr inciple of superposition, th e input signal

volta ge, VIN- ,on t he n on-invert ing input of A1 is set to zero. Since th e input signal,

VIN+ , is app lied to the n on-invert ing ter mina l of A2, an expr ession for t he n odal

volta ge at t he inver ting t erm ina l of A1 is given by Eq. 1.5:

V A =V CM Eq. 1.5

An expression for t he out put volta ge of A1 (node B) shows th at it is depen dent on

all th ree exter na lly applied volta ges (VIN, VCM, and VRE F), and is illustr at ed in Eq.

1.6:

VB V IN +R2

RG+ VCM 1+

R2

R1 VREF=

( )R

R

2

1Eq. 1.6


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Since the input signal, VIN+ ,as well as th e applied inpu t comm on-mode voltage,

VCM, is applied to the n on-inverting t ermina l of A2, then th e expression for th e

volta ge at A2s inver tin g inpu t (node C) is given by:

VC VCM= + +V IN Eq. 1.7

For t he case wher e R1 = R4 and R2 = R3, combining the r esult s in Eq. 1.5, 1.6, an d

1.7 yields th e familiar expression for th e circuits outpu t voltage:

VOUT =( V IN +1+

R4

R3+

2R4

RG+ VREF)

Eq. 1.8

At th is point , it is worth noting th e beha vior of th e circuits nodal volta ges based on

th e applied extern al volta ges. From Eq. 1.5 and E q. 1.7, the comm on-mode

component of the curr ent t hr ough RG is equal to zero, whereas the full differential

input voltage appears across it. Fur ther more, Eq. 1.6 has shows th at A1 amplifies

th e a pplied comm on-mode inpu t volta ge by a factor of (1 + R2/R1). In low-gainapp licat ions, t he r at io of R2 to RG can be a s sma ll as 1:1 (for circuit gains gr eat er

th an or equa l to 2). Therefore, Equa tion 1.6 sets the u pper bound on the inpu t

comm on-mode voltage in low-gain app licat ions. If th e outp ut of A1 is a llowed t o

sat ur at e at high input common-mode voltages, then it will not have enough

hea dr oom to am plify the in put signal, as s hown in E q. 1.6. Therefore, in order for

A1 to amplify accur at ely inpu t signal voltages for an y circuit ga in > 1 (circuit gains

equal to 1 are n ot perm itted in th is topology) requires tha t a n u pper bound on the

tota l app lied input volta ge (common-mode plu s differen tial-mode volta ges) be

determ ined to prevent am plifier outpu t voltage sat ura tion. This upper boun d can be

determined by th e desired circuit gain, G, and the amplifier's minimum outpu t high

voltage:

VIN(TOTAL) < VOH(MIN)0.9G1

0.9G V

IN +

Eq. 1.9

In a similar fashion, a lower boun d on t he t ota l applied inpu t voltage is also

deter mined by circuit gain a nd t he a mplifiers ma ximum outp ut low voltage:

VIN(TOTAL) > VOL(MAX)0.9G 1

0.9G+ V

IN +

Eq. 1.10

For exam ple, if a r ail-to-ra il opera tional a mplifier exhibited a VOL(MAX) equal to

10mV and a VOH(MIN) equal t o 4.95V, an d if the a pplicat ion r equired a circuit gainof 10 to produce a 1V full-scale out put , then th e tota l input volta ge ra nge would be

boun ded by:

0.109 V < VIN(TOTAL) < 4.3 V


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14

Therefore, th e ra nge over which th e circuit will han dle input voltages without

am plifier out put voltage sat ur at ion is given by:

VOL(MAX)0.9G 1

0.9G

+ VIN +

< VIN(TOTAL) < VOH(MIN)0.9G1

0.9G

VIN +

Eq. 1.11

In low-gain instrumentation circuits, the usable input voltage range is limited and

asym met ric about th e supply mid-point voltage. To complete t he n odal ana lysis of

th e two op a mp instru ment at ion circuit, expressions for operat iona l am plifier output

sta ge cur rent s ar e shown in Equa tions 1.12 an d 1.13:

( )I OA1 =(V IN +2

RG+

1

R3+ VREF VCM

2

R1)

Eq. 1.12

( )I OA2 = (V IN + 2RG+ 1

R3+ VCM VREF 1

R4)

Eq. 1.13

Equa tion 1.12 illustr ates tha t A1s output stage mu st be a ble to sink current as a

function of the applied differential input voltage and the output reference voltage.

On th e oth er ha nd, A1s out put sta ge is required t o sour ce cur ren t over th e entire

input voltage ran ge.In th e s in gle-su pply case w here t h e cir cu it is requ ir ed to sen se

sm all differential sign als near groun d, E q. 1.6 and E q. 1.12 both illustrate th at A1s

output stage is required to sink current w hile trying to main tain a m ore negative

output v oltage tha n its own n egative supply . A1 is t hu s forced into saturation .

As shown in E q. 1.13, A2s outpu t s ta ge sour ces cur ren t for positive different ialinpu t volta ges with no different ial or comm on-mode volta ge constr ain ts pla ced upon

its output by Eq. 1.8.N ote, h owever, that as a fu nct ion of the a ppli ed com m on -m od e

voltage, A2 is required to sink current. Un fortun ately, in t he absence of an inpu t

signal, Eq. 1.13 shows th at A2s outpu t stage ma y be forced into satu ration, trying

to sink current w hile main tainin g its outpu t voltage at VOL .

To circumvent th e circuit topological a nd am plifier outpu t voltage limita tions, a

referen ce volta ge should be used t o bias t he out put of th e circuit (A2s outpu t) in the

m idd le of its outpu t voltage swin g, and not a t exactly one-half the s upply voltage:

VREF =

VOH(MIN) + VOL(MAX)

2 Eq. 1.14

The outpu t reference voltage a llows th e output sta ges of A1 a nd A2 to sink or

sour ce curren t with out an y outpu t volta ge constr aint s. So long as Eq. 1.11 is used to

define t o tota l inpu t volta ge ran ge, th en a mplifier beh avior for differen tia l- an d

common-mode operation is linear. To maximize output signal dynamic range and

outpu t SN R, the gain of the inst rum enta tion a mplifier circuit should be set

accord ing to Eq. 1.15:


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Circuit Ga in =VOH(MIN) VOL(MAX)

2 VIN(MAX)Eq. 1.15

Under th ese opera ting conditions, t he different ial out put voltage of th e

instru ment ation am plifier circuit is now measur ed relat ive to VRE F and not toGND. Thu s, negat ive full-scale input signals pr oduce outpu t voltages nea r A2s VOL,

an d positive full-scale signals pr oduce outpu t volta ges nea r A2s VOH . Therefore,

th e circuit 's input common-mode ra nge an d output dynamic ra nge ar e optimized in

terms of the desired circuit gain and amplifier output voltage characteristics.

For min imal impa ct of am plifier outpu t load curr ent s on VOH and VOL, circuit

resistor values should be greater than 10kohm in most single-supply applications.

Thu s, Equa tions 1.11, 1.14, an d 1.15 can all be used to design a ccur at e an d

repea ta ble two op amp inst ru ment at ion a mplifier circuits with s ingle-supply/ra il-to-

ra il opera tiona l am plifiers.

One fund am ental limitat ion of the two operational am plifier instrum entation

circuit is th at sin ce th e two am plifiers are operatin g at d ifferent closed-loop gains

(and th us at different band wid ths), there will be generally poor AC com m on-m ode

rejection with out the use of an A C CMR trim capacitor. For optima l AC CMR

perfor m ance, a tri m m in g capacitor sh ou ld be con n ected between th e invertin g

terminal of A1 to groun d.

A T WO OP AMP , F E T-I N P U T INSTRUMENTATION

AMPLIFIER

Figur e 1.9 illustr at es a two op am p instr um ent at ion a mplifier using the AD822, a

dua l JF ET-input, r ail-to-ra il out put opera tional am plifier. The out put offset voltage

is set by VRE F.


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A SINGLE-SUPPLY, PROGRAMMABLE, FET-INPUTINSTRUMENTATION AMPLIFIER

Figure 1.9

Dual operational amplifiers, like the AD822, make these types of instrumentation

am plifiers both cost- and p ower-efficient . In fact, when operat ing on a single, +3 V

supply, total circuit power consu mpt ion is less th an 3.5mW. The AD822s 2pA bias

curren ts m inimize offset er rors caused by unba lanced sour ce impedan ces.

Circuit per forma nce is enh an ced dra ma tically by the u se of a ma tched resistor

network. A thin-film r esistor a rr ay sets t he circuit gain to eith er 10 or 100 thr ough

a DP DT (double-pole, double-thr ow) switch. The a rr ays resist ors a re la ser-tr immed

for a ra tio match of 0.01%, and exhibit a maximum different ial tempera tu re

coefficient of 5ppm/C. Note t ha t in t his applicat ion circuit, th e fifth gain-setting

resistor is not used. The use of this gain trim resistor would introduce serious gain

an d linear ity err ors due t o the r esistance of th e double-pole, double-th row switches.

A perform an ce summa ry and t ra nsient r esponse of this instr umen ta tion am plifier is

shown in Figur e 1.10. Note th at th e small-signal ban dwidth of th e circuit is

independ ent of supply voltage, an d th at th e ra il-to-ra il out put pulse response is well-

behaved. For great er ban dwidth at t he expense of higher supply cur rent , the

functiona lly similar AD823 can also be used.


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PERFORMANCE SUMMARY OF AD822 IN-AMP

Figure 1.10

T H E T H REE OP AMP INSTRUMENTATION AMPLIFIER

T OPOLOGY

For th e highest precision a nd perform an ce, the three op amp instrumentation

am plifier t opology is optimum for bridge an d other offset t ra nsdu cer applications

where h igh a ccuracy and low nonlinearity a re r equired. This is at th e expense of

additiona l power consum ption over th e two op a mp instru ment at ion circuit (3

am plifiers versus 2 am plifiers). Fu rt herm ore, like the two op a mp configura tion, th e

inpu t a mplifiers can u se one du al op amp for t ight ma tching of input offset volta ge

matching, input bias current, and open-loop gain. Or, a single quad operational

am plifier can be used for th e whole circuit, including a referen ce volta ge buffer, ifrequired.

Single-supply/rail-to-ra il amplifiers can be used in t his t opology, like th at shown for

two op a mp designs, if the out put char acter istics of th e single-supply/rail-to-ra il

amplifiers are understood. As shown in Figure 1.11, a generalized, comprehensive

an alysis of th e str uctur e will illustr at e the beha vior of th e nodal volta ges and

amplifier output currents as functions of the applied common-mode input voltage

(VCM), the applied differential (signal) voltage (VIN), and t he output reference

volta ge (VRE F). As shown in Eq. 1.16 th rough 1.27, th e nodal ana lysis was car ried

out for positive-inpu t differen tia l volta ges; becau se of th e symmet ry in t he circuit,

th e expressions for the nodal voltages an d am plifier outpu t cur rent s carr ied out for

negat ive-inpu t differen tial voltages a re ident ical.


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THE UBIQUITOUS 3 OP AMP INSTRUMENTATIONAMPLIFIER IN SINGLE-SUPPLY APPLICATIONS

Figure 1.11

Using h alf-circuit concepts a nd t he pr inciple of superposition, t he signa l voltage

app lied to th e non-invert ing ter mina l of A1 is set t o zero. Since th e input signal is

applied to the n on-inverting t ermina l of A2, then an expression for the out put

volta ge of amp lifier A1 (node A) for positive, differen tia l inpu t sign als is given by E q.

1.16:

VA =(V IN +R1

RG+ VCM)

Eq. 1.16

Since th e voltage at the inverting input of A1 must equal th e voltage at its non-

invert ing term ina l, th en an expression for the volta ge at am plifier A1s invertin gter mina l (node B) is given by E q. 1.17:

VB = VCM Eq. 1.17

In a similar man ner, th e voltage at A2s inverting termina l must equal th e voltage

on A2s non-invert ing ter min al:

VC = V IN ++ VCM Eq. 1.18

The expr ession for th e out put volta ge of A2 (node D) shows th at it is depend ent

upon both the input signa l and the applied input common-mode voltage:

VD =(V IN +R2

RG+ VCM) 1 +

Eq. 1.19

At th is point, it is worth noting th e beha vior of th e nodal volta ges of the inpu t

am plifiers as fun ctions of th e applied differentia l input volta ge and t he inpu t

common-mode voltage. From Eqs. 1.17 and 1.18, the common-mode component of


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the curr ent t hrough the gain sett ing resistor, RG,is zero the input stages simply

buffer th e a pplied inpu t common-mode voltage. In oth er words, the input stage

com m on-m ode gain is unity .

On t he other ha nd, th e full different ial input volta ge appears across RG. In fact, Eq.

1.16 shows th at A1 mult iplies an d inverts th e input differen tia l volta ge by a factor of

( R1/RG), while Eq. 1.19 shows tha t A2 mult iplies th e input voltage by a factor of

(1+ R1/RG). For th e case where t he outpu t su btra ctor sta ge is configured for a gain

of 1, all th e different ial gain is set in th e input sta ge. Ther efore, th e ra tio of R1 to

RG (or R2 t o RG) could be as sma ll as 1:1 or as lar ge as 5000:1. Therefore, to avoid

input a mplifier outpu t voltage satu ra tion requires a n upper an d a lower bound be

placed on th e tota l input volta ge (defined t o be comm on-mode plus differen tia l-mode

voltages). These boun ds ar e set by the gain of the inst ru ment at ion a mplifier an d th e

outpu t h igh an d low volta ge limits of th e am plifier. The lower bound on th e total

applied input volta ge is given by Eq. 1.20:

VIN(TOTAL)

> VOL(MAX)

+G-1

2(V

IN +

) Eq. 1.20

An u pper bound on the t ota l input voltage can be determ ined in a similar fashion

an d is also dependen t on the circuit gain a nd th e amplifiers minimu m outpu t high

voltage:

VIN(TOTAL) < VOH(MIN) G+ 1

2(V

IN +

) Eq. 1.21

For exam ple, if a r ail-to-ra il opera tional a mplifier exhibited a VOL(MAX) equal to

10mV and a VOH(MIN) equal t o 4.95V, an d if the a pplicat ion r equired a circuit gain

of 10 for a 1V full-scale outpu t, th en t he t otal inpu t volta ge ra nge would be boun dedby:

0.46 V < VIN(TOTAL) < 4.4 V

Therefore, for t he t hr ee op am p instr umen ta tion circuit, th e total applied input

volta ge ran ge express ed in ter ms of circuit gain a nd a mplifier outpu t volta ge limits

is given by:

VOL(MAX) +G - 1

2(V

IN +) < VIN(TOTAL) < VOH(MIN)

G + 1

2(V

IN +

)

Eq. 1.22


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Since the non-inverting inpu t of the subt ra ctor a mplifier A3 determ ines th e voltage

on its inverting term inal, an expression for the voltages at Nodes E an d F is given

by Eq. 1.23:

VE = VF =( V IN +R6

R4 + R6

R2

RG+ VCM

R6

R4 + R6 + VREFR4

R4 + R6) +

1

Eq. 1.23

For t he case wher e R3, R4, R5, and R6 a re a ll equa l to R (typically th e case for

instr umen ta tion am plifier gains greater t ha n or equal to 1), then th ese nodal

volta ges will set up a t one-half the a pplied out put volta ge reference (VRE F) and a t

one-half the a pplied input comm on-mode volta ge (VCM). Fu rt herm ore, the

component due to th e amplified different ial input signa l is also att enu at ed by a

factor of two. Fin ally, Eq. 1.24 shows an expression for th e circuits outpu t voltage in

its fam iliar form for R4 = R3 a nd R6 = R5:

VOUT =(V IN +R5

R3

2R1

RG+ VREF)

+

1 Eq. 1.24

Fr om Eq. 1.24, the circuit outpu t volta ge is only a function of the a mplified input

different ial voltage an d th e output reference voltage. Provided th at R4 = R3 an d R6

= R5, the component of the outpu t volta ge due t o the a pplied input common-mode

voltage is completely suppressed. The only remaining error voltage is that due to

th e finite CMR of A3 and t he r at io ma tch of R3 to R5 an d R4 to R6. Also, in th e

absence of either an input signa l or an out put reference voltage, A3s output voltage

is equal t o zero; in a single-supply applicat ion wh ere r ail-to-ra il out put am plifiers a re

used, it is equa l to VOL.

To complete the analysis of this instrumentation circuit, expressions for operational

am plifier out put sta ge cur rent s ha ve been developed an d ar e shown in Eqs. 1.25

thr ough 1.27:

I OA1 =V IN + R1

RG1+

R3

R1+ 1+

R2

RG

R4

R4 + R6+

VREF -V CM

R3

R4

R4 + R6R3

Eq. 1.25

I OA2 = (V IN + 1 + R2RG1

R2+ 1

R4 1

R4R6

R4 + R6 1

R2+ VREF V CM

R4 + R6)

Eq. 1.26


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I OA3 =V IN + )

3 + R5

R1

RG+

R5

R3+

2 R1 R5

R3 RG+

VCM VREF

R3+ R5

(

REq. 1.27

Recall in the a na lysis of th e two-am plifier instr um ent at ion circuit th at am plifier

output stage currents were defined to be positive, if current flow is in to th e device,th e am plifier is s inking cur rent . Conversely, if the nodal ana lysis shows th at out put

curren ts ar e negative quan tities, then cur rent flow is out ofthe a mplifier, and th e

am plifier is sourcing current .

Equ ation 1.25 il lu st ra tes that A1s ou tpu t st age m ust be able t o sin k cu rren t as a

fu n ct ion of th e applied d iff eren tia l in pu t voltage an d th e ou tpu t referen ce voltage.

On th e other han d, A1s out pu t stage is required to source curren t throu ghout th e

applied com m on-m ode voltage.In th e s in gle-su pply case w h ere t h e cir cu it is

required to sense small d ifferential signals n ear ground , Eq. 1.16 and Eq. 1.25 both

illustrate that A 1s output stage is required to sink current wh ile trying to m aintain

a m ore negative outpu t voltage than its own n egative supply .A1 cann ot su st ain

this operating point, an d th us is forced into outp ut satu ration.

As shown in Eq. 1.26, A2s outpu t st age sour ces curr ent for p ositive input signal

volta ges with n o different ial nor comm on-mode volta ge const ra int s placed upon its

outpu t by Eq. 1.19. A3s out put sta ge is also required t o source cur ren t a roun d its

feedback resistor a s a fun ction of th e positive input different ial volta ge. Note,

however, that as a function of the applied common-mode voltage, it is required to

sink curr ent. Un fortun ately Eq. 1.24 showed th at in the absence of an inpu t signal,

A3s ou tpu t st age can be for ced in to satu ra tion , try in g to s in k cu rr en t wh il e

maintaining its output voltage at A3s VOL .

To circumvent circuit t opological a nd am plifier outpu t voltage limita tions, the resu ltsshown in Eq. 1.14 and E q. 1.15 for t he two op am p instr um ent at ion circuit a pply

equa lly well her e. The out put referen ce volta ge is chosen in t he m iddle of A1 an d

A2s outp ut volta ge swing:

VREF =VOH(MIN) + VOL(MAX)

2Eq. 1.14

Similar ly, outpu t signal dynamic ran ge and output SNR ar e maximized if the gain of

th e instr um ent at ion circuit is set according to Eq. 1.15:

Circuit Ga in =VOH(MIN) VOL(MAX)

2 VIN(MAX)

Eq. 1.15

Under th ese opera ting conditions, t he different ial out put voltage of th e

instru ment ation am plifier circuit is now measur ed relat ive to VRE F and not to

GND. Thu s, negat ive full-scale input signals yield out put voltages n ear A3s VOL,

an d positive full-scale signals pr oduce outpu t volta ges nea r A3s VOH . Thu s, circuit

input common-mode ran ge and outpu t dyna mic ra nge ar e optimized in t erms of the

desired circuit gain a nd a mplifier out put voltage char acterist ics.


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For minimal impa ct on VOH and VOL due to amp lifier out put load cur ren ts, circuit

resistor values should be greater than 10kohm in single-supply applications. Thus,

Equ at ions 1.22, 1.14, and 1.15 can a ll be used to design accur at e and r epeat able

th ree op amp inst ru men ta tion amplifier circuits with single-supply/ra il-to-ra il

operational amplifiers.

A COMPOSITE, S INGLE-S U P P L Y INSTRUMENTATION

AMPLIFIER [3]

As it h as been sh own t hr oughout t his chapter , opera tion of high perform an ce linea r

circuits from a single, low-volta ge supp ly (5V or less) is a comm on requ irem ent .

While ther e ar e ma ny pr ecision sin gle supply opera tional a mplifiers (some r ail-ra il),

such a s th e OP213, the OP291, an d th e OP284, and some good single-supp ly

instrumentation amplifiers, such as the AMP04 and the AD626 (both covered later),

th e highest per forma nce instru ment at ion amplifiers ar e still specified for dua l-

supply operation.

One way to achieve both high precision and single-supply operation takes

advan ta ge of the fact t ha t several popular t ra nsdu cers (e.g. strain gauges) provide

an outpu t signal centered ar oun d th e (approximate) mid-point of the su pply voltage

(or the reference voltage), where the inputs of the signal conditioning amplifier

need n ot oper at e nea r ground or th e positive supply volta ge.

Under th ese conditions, a dua l-supply instru ment at ion a mplifier referenced to the

supply mid-point followed by a ra il-to-rail opera tiona l am plifier gain st age pr ovides

very high DC precision. Figure 1.12 illustrates one such high-performance

instr um ent at ion a mplifier operat ing on a single, +5V supply. This circuit uses a n

AD620 low-cost pr ecision inst ru men ta tion amp lifier for t he inpu t st age, an d anAD822 J FE T-input dua l rail-to-ra il out put opera tional amplifier for the output sta ge.

A PRECISION SINGLE-SUPPLY INSTRUMENTATIONAMPLIFIER WITH RAIL-TO-RAIL OUTPUT

Figure 1.12


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In th is circuit, R1 a nd R2 form a voltage divider which splits th e sup ply voltage in

ha lf to +2.5V, with fine a djustm ent provided by a tr imming potent iomet er, P1. This

volta ge is applied to th e inpu t of an AD822 which bu ffers it an d pr ovides a low-

impeda nce source needed to drive t he AD620s outp ut referen ce port . The AD620s

REFE RENCE input h as a 10kohm input r esista nce and a n input signal curr ent of

up to 200A. The oth er h alf of the AD822 is connected a s a gain-of-3 invert er, so

th at it can outpu t 2.5V, ra il-to-rail, with only 0.83V requ ired of the AD620. This

outpu t voltage level of th e AD620 is well with in t he AD620s capa bility, th us

ensu rin g high linea rit y for the dua l-supp ly front end. N ote t h at th e f in al ou tpu t

voltage mu st be m easured w ith respect to th e +2.5V reference, and not to GN D.

The genera l gain expression for th is composite inst ru ment at ion a mplifier is th e

product of th e AD620 and t he invert ing amplifier gain s:

GAINk

RG

RF

RI= +

49 41

. Eq. 1.28

For t his exam ple, an overall gain of 10 is realized with RG = 21.5kohm (closest

sta ndar d value). The ta ble (Figure 1.13) summa rizes various RG/ga in va lu es .

In t his applicat ion, th e total input voltage applied to the inpu ts of th e AD620 can be

up to +3.5V with no loss in precision. For exam ple, at a n overall circuit ga in of 10,

th e comm on-mode inpu t voltage r an ge span s 2.25V to 3.25V, allowing room for th e

0.25V full-scale differen tial in put voltage r equired to drive th e outpu t 2.5V about

VRE F.

The invert ing configur at ion was chosen for th e output buffer t o facilitat e system

out put offset volta ge adjustm ent by summ ing curren ts into th e buffers feedback

sum ming n ode. These offset cur ren ts can be provided by an externa l DAC, or from

a resistor conn ected t o a reference voltage.

The AD822 rail-to-rail out put sta ge exhibits a very clean tr an sient r esponse (not

shown) and a sma ll-signal ban dwidth over 100kHz for ga in configur at ions u p to 300.

Figure 1.13 summ ar izes th e perform an ce of this composite inst ru ment at ion

am plifier. To redu ce the effects of unwa nt ed noise picku p, a capa citor is

recomm ended a cross A2s feedback resist an ce to limit t he circuit ba ndwidt h t o th e

frequen cies of int eres t. Also, to preven t t he effects of inpu t-sta ge rectification, an

optiona l 1kHz filter is recomm ended a t t he inpu ts of th e AD620.


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PERFORMANCE SUMMARY OF THE +5V SINGLE-SUPPLYAD620/AD822 COMPOSITE INSTRUMENTATION AMP

WITH RAIL-TO-RAIL OUTPUTS

Figure 1.13

L OW-SIDE AND H IGH-SIDE S IGNAL CONDITIONING

As previous d iscussions h ave sh own, single-supply a nd r ail-to-ra il opera tional

am plifiers in t wo and t hree op a mp inst rum enta tion amplifier circuits impose

cert ain limits on the u sable input common-mode an d output voltage ra nges of the

circuit. There are, however, many single-supply applications where low- and high-

side signal conditioning is r equired. F or th ese a pplicat ions, n ovel circuit design

techn iques allow sensing of very sma ll differen tial signa ls at GND or at VPOS . Two

such d evices, th e AMP04 an d AD626, ha ve been designed s pecifically for th ese

applications.

As illust ra ted in F igure 1.14, the AMP04, a single-supply instru ment at ion a mplifier,

uses a invert ing-mode out put ga in ar chitectur e, where a n extern al resistor, RG(conn ected bet ween th e AMP04s Pin s 1 an d 8), is used a s th e input resist or to A4,

an d an int ern al 100kohm t hin-film resistor, R1, serves as th e out put a mplifiers

feedback resistance. Unity-gain input buffers A1 and A2 both serve two functions:

th ey present a high impedance to the source, and pr ovide a DC level shift t o the

ap plied comm on-mode inpu t voltage of one VBE for a mplifiers A3 an d A4. As a

result, t heir outpu t st ages can operate very close th e negative supply without

saturating.

The input buffers a re designed with P NP t ra nsistors t hat allow the a pplied common-mode voltage range to extend to 0V. In fact, the usable input common-mode voltage

ra nge of th e AMP04 actu ally exten ds 0.25V below th e negat ive supply (although not

guara nteed, applied input voltages to any integra ted circuit should always remain

within its total supply voltage ran ge). On the other ha nd, since the inpu t buffers a re

PN P st ages, th e inpu t comm on-mode volta ge ran ge does not include th e AMP04s

positive supply voltage. When t he inp ut s ar e driven with in 1V of the positive ra il,


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th e PN P inpu t t ra nsistors ar e forced into cut off; an d, as a result, input offset

voltages and bias cur rent s increase, and CMR degrades.

SINGLE SUPPLY INSTRUMENTATION AMP HANDLESZERO-VOLTS INPUT AND ZERO-VOLTS OUTPUT (AMP04)

Figure 1.14

A pulsed-bridge tr an sducer-driver/amplifier illust ra tes t he u tility of this low-power,

single-supply instr um ent at ion a mplifier circuit a s shown in Figure 1.15. Comm only

ava ilable 350ohm str ain-gauge bridges a re difficult t o apply in low-voltage, low-

power systems for a nu mber of rea sons, including th e requirem ent s for h igh br idge

drive cur rent s a nd high sensitivity. For low-speed measu rement s, power limitations

can be overcome by opera ting th e bridge in a pulsed-power m ode, reading t heamplified output on a low-speed, low-duty-cycle basis.


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A LOW POWER, PULSED LOAD CELL BRIDGE AMPLIFIER

Figure 1.15

In t his circuit, an extern ally gener at ed 800s TTL/CMOS pulse is applied to the

SHU TDOWN input to th e REF 195, a +5V precision voltage referen ce. The RE F195s

shu tdown feat ur e is used t o switch between a norma l +5V DC out put if left open (or

at logic HIGH), and a low-power-down st an dby stat e (5A maximum cur rent dra in)

with t he sh ut down pin held low. The switched 5V outpu t from th e REF 195 drives

th e bridge and su pplies power to th e AMP04. The AMP04 is program med for a gain

of 20 by the 4.99kohm r esistor, which should be a s ta ble film type (TCR = 50ppm/C

or bett er) in close ph ysical pr oximity to th e am plifier. Dyna mic perform an ce of the

circuit is excellent , becau se t he AMP04s outp ut sett les to within 0.5mV of its finalvalue in about 230s (not shown).

This approach allows fast measu remen t speed with a minimum st an dby power.

Gener ally speaking, with a ll active circuitry essen tially being switched by the

measu remen t pulse, the avera ge cur rent dra in of th is circuit is determined by its

dut y cycle. On-state curr ent dra in is about 15mA from th e 6V batt ery dur ing the

measur ement interval (90mW peak power). Therefore, an 800s mea suremen t

str obe once per second will dissipate a n a vera ge of 72W, to which is a dded t he

30W stan dby power of th e REF 195. In an y event, overa ll opera tion is enha nced by

th e REF195s low-dropout regu lat ion char acter istics. The REF 195 can operat e with

supply voltages a s low as +5.4 V and st ill ma inta in +5V out put opera tion.

If low-frequ ency filterin g is desired, a n optiona l capa citor can be conn ected between

pins 6 a nd 8 of the AMP04. However, a mu ch longer str obe pulse must be used so

th at th e filter can set tle to the circuits requ ired accura cy. For example, if a 0.1F

capacitor is used for noise filtering, then the R-C time const an t form ed with th e

AMP04s int ern al 100kohm r esistor is 10ms. Ther efore, for a 10-bit sett ling

criterion, 6.9 time const an ts, or 70ms, sh ould be a llowed. Obviously, th is will place

great er dema nds u pon system power, so tr ade-offs ma y be necessary in th e amoun t

of filtering used.


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Of cour se, the am plified bridge outpu t a ppear s only during th e measu remen t

inter val, and is valid after 220s un less filter ing is used. Dur ing this time, a sa mpled-

inpu t ADC (ana log-to-digita l convert er) rea ds VOU T, elimina ting th e need for a

dedicat ed sa mple-and-hold circuit t o reta in t he outpu t volta ge. If 10-bit

measu remen ts a re su fficient, th e 5V bridge drive can also be assumed t o be

const an t (for 10-bit accura cy), becau se th e REF 195 exhibits a 1mV (0.02 %)

out put volta ge tolera nce. For more accurat e measur ement s, a rat iometr ic rea ding

of th e bridge stat us can be obtain ed by rea ding th e bridge drive (VRE F) as well as

VOU T.

On t he other ha nd, single-supply instru ment at ion amplifiers, like t he AD626, shown

in Figure 1.16, exhibit an input stage ar chitecture t ha t a llows the sensing of small

differen tial inpu t signa ls, not only at its positive supply, but beyond it a s well. The

AD626 is a differen tial a mplifier consistin g of a pr ecision ba lanced at ten ua tor, a very

low-drift pr eam plifier (A1), an d an outpu t bu ffer a mplifier (A2). It h as been

designed so that sma ll different ial signa ls can be accur at ely amplified and filtered in

th e presen ce of lar ge comm on-mode voltages, without t he u se of an y oth er exter na lactive or pa ssive componen ts.

AD626 SCHEMATIC ILLUSTRATES INPUT PROTECTIONAND SCALING RESISTORS AND ALLOWS

INPUT COMMON MODE VOLTAGE UP TO 6 x (Vs - 1V)

Figure 1.16

The simplified equivalent circuit in F igure 1.16 illust ra tes t he ma in element s of th e

AD626. The signa l inpu ts a t P ins 1 an d 8 are first a pplied to the dua l resistive

at ten ua tors R1 th rough R4, whose pur pose is to redu ce th e peak comm on-modevoltage a t t he inpu ts of A1. This allows th e applied differen tial volta ge to be

accura tely am plified in th e pres ence of lar ge common-mode volta ges six times

greater tha n t hat which can be tolerat ed by th e actual input t o A1. As a r esult, input

common-mode rejection extends to 6(Vs 1V). The overa ll common-mode err or isminimized by precise laser tr imming of R3 an d R4, th us giving t he AD626 a

common-mode rejection ratio (CMRR) of at least 10,000:1 (80dB).


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To minimize th e effect of spur ious RF signals at th e input s due t o rectification at t he

input s to A1, small filter capa citors C1 a nd C2, inter na l to the AD626, limit th e input

bandwidth to 1MHz.

The out put of A1 is conn ected to th e inpu t of A2 via a 100kohm r esistor (R12) to

allow th e low-pass filterin g to the signals of inter est. To use th is feat ur e, a capacitor

is connected between Pin 4 a nd t he circuits comm on. Equ at ion 1.29 can be used t o

deter mine t he va lue of th e capacitor, ba sed on th e corn er frequen cy of this low-pass

filter:

( )CLP =1

2 100 k fLP Eq. 1.29

where f LP = th e desired corner frequen cy of th e low-pass filter , in Hz.

The 200kohm input impedance of the AD626 requires th at th e sour ce resista nce

driving this a mplifier should be less tha n 1kohm t o minimize gain err or. Also, any

mismat ch between th e total source resista nce of eith er inpu t will affect ga inaccur acy and common-mode r ejection. F or example, when opera ting a t a gain of 10,

an 80ohm mismat ch in th e sour ce resista nce between t he inpu ts will degrade circuit

CMR to 68dB.

Out put am plifier, A2, opera tes a t a ga in of 2 or 20, thu s sett ing the overa ll,

precalibra ted ga in of th e AD626 (with n o extern al componen ts) at 10 or 100. The

gain is set by the feedback n etwork ar oun d a mplifier A2.

The output of A2 uses an inter na l 10kohm resistor to Vs to pull down its out pu t.

In single-supply app lications where Vs equa ls GND, A2s outpu t can dr ive a

10kohm ground-referenced load to at least +4.7V. The minimum nominal zero

outpu t voltage of the AD626 is 30mV.

If pin 7 is left u nconn ected, the gain of the AD626 is 10. By connecting pin 7 to GND,

th e AD626s gain can be set to 100. To adjust th e gain of the AD626 for gains

between 10 and 100, a variable resistance network can be used between pin 7 and

GND. This var iable resista nce network includes a fixed resistor with a rh eostat -

conn ected potent iometer in series. The inter ested r eader should consult th e AD626

dat a sh eet for complete det ails for a djustin g the gain of th e AD626. For t hese

app licat ions, a 20% adjustment ra nge in the gain is r equired. This is due to the on-

chip resistors absolute tolerance of 20% (these resistors, however, are ratio-

ma tched t o with in 0.1%).

An example of th e AD626 high-side sensin g capa bilities, Figure 1.17 illust ra tes a

typical curr ent sensor interface amplifier. The signal cur rent is sensed across the

current shunt , Rs. For reasons ment ioned ear lier, the value of the current shun t

should be less tha n 1ohm a nd sh ould be selected so tha t t he a verage different ial

volta ge across this r esistor is typically 100mV. To gener at e a full-scale outpu t

voltage of +4V, the AD626 is configured in a gain of 40. To accommodate the

tolera nce in the curr ent sh un t, the varia ble gain-setting resistor net work sh own in


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the circuit h as a n a djustment ran ge of20%. Note t ha t su fficient h eadr oom exists

in t he gain tr im to allow at least a 10% overra nge (+4.4V).

AD626 HIGH-SIDE CURRENT MONITOR INTERFACE

Figure 1.17

INSTRUMENTATION AMPLIFIER IN P U T-STAGE

R ECTIFICATION

A well-kn own ph enomen on in an alog int egra ted circuits is RF r ectificat ion,

particularly in instrumentation amplifiers and operational amplifiers. While

am plifying very sma ll signa ls, these devices can r ectify unwa nt ed high-frequ ency,

out-of-band signa ls. The resu lts ar e DC errors at the out put in addition t o the

want ed sensor signal. Unwa nted out -of-band signa ls enter sensitive circuitsth rough t he circuit 's condu ctors which provide a direct pa th for interference to

couple int o a circuit. Th ese condu ctors pick u p n oise th rough capa citive, inductive,

or radiation coupling. Regardless of the type of interference, the unwanted signal is

a voltage which a ppears in ser ies with the inpu ts.

All instru ment ation and operational amplifier input sta ges are either emitter -

coupled (BJ T) or sour ce-coupled (FE T) differen tia l pair s with r esistive or cur ren t-

sour ce loading. Depending on t he quiescent curren t level in t he devices an d th e

frequency of the int erference, these differen tial pa irs can beha ve as high-frequen cy

detectors. As it h as been shown in [1], this det ection pr ocess produces spectra l

components a t t he ha rm onics of the int erference as well at DC. It is the DC

component tha t sh ifts intern al bias levels of the inpu t st ages causing errors, whichcan lead to system inaccuracies. For a complete treatment of this issue, including

an alytical a nd em pirical r esults, the interested reader should consu lt Reference [1].

Since it is required to prevent un want ed signa ls and n oise from enter ing the input

sta ges, inpu t filter ing techniques a re u sed for t hese t ypes of devices. As illust ra ted

in Reference [1], th is technique u ses an equivalent a pproach suggested for

operat iona l amp lifiers. As shown in F igure 1.18, low-pass filters a re u sed in ser ies


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with th e differen tial inputs t o prevent u nwan ted noise from rea ching the inpu ts.

Her e, capa citors, CX1, CX2, and CX3, conn ected a cross th e input s of th e

instr um enta tion a mplifier, form common-mode (CX1 and CX2) and differen tial-

mode (CX3) low-pass filter s with t he t wo resist ors, RX. Time const an ts RX-CX1 and

RX-CX2 should be well-matched (1% or better), because imbalances in these

impeda nces can genera te a d ifferent ial err or volta ge which will be amp lified.

On the oth er ha nd, a n additiona l benefit of using a different ially-conn ected

capacitor is tha t it can r educe common-mode capa citive imbalan ce. This differen tia l

connection helps to preserve high-frequency AC common-mode rejection. Since

series resistors a re r equired to form th e low-pass filter , errors du e to poor layout

(CMR imba lan ce), component tolera nce of RX (input bias current-induced offset

voltage) and r esistor th erma l noise mu st be considered in the design process. In

applications where t he sensor is an RTD or a resistive str ain gau ge, RX can be

omitted, pr ovided th e sensor is close to th e am plifier.

EXTERNAL COMMON-MODE AND DIFFERENTIAL-MODEINPUT FILTERS PREVENT RFI RECTIFICATION IN

INSTRUMENTATION AMPLIFIER CIRCUITS

Figure 1.18


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R E F E R E N C E S

1. S ys t ems App l ica t i on Gu ide , Cha pt er 1, pg. 21-55, Ana log Devices,

Incorporated, Norwood, MA, 1993.

2. L i n e a r D e s i g n Se m i n a r , Section 1, pp. 19-22, Ana log Devices,Incorporated, Norwood, MA, 1995.

3. Lew Count s, Pr oduct Line Director, Advan ced Linear Pr oducts,

Ana log Devices, In corpora ted, p ersona l comm un icat ion, 1995.

4. Walt J ung, and J am es Wong, Op am p selection m inim izes im pact of

single-supply design , E DN, May 27, 1993, pp . 119-124.

5. E. J acobsen, and J . Baum , Hom e-brew ed circu it s tail or sen sor ou tpu ts

to specialized needs , E DN, J an ua ry 5, 1995, pp. 75-82.

6. Walt J un g, Corpora te Sta ff Applicat ions En gineer, Analog Devices,Incorporated, per sona l commu nicat ion, J an ua ry 27, 1995.

7. Walt J ung,An alog-S ign al-Processi n g Con cepts Get More E ff icien t,

Elec t r on i c Des ign Ana log App l ica t i ons I s sue , Ju ne 24, 1993,

pp. 12-27.

8. C.Kitchin an d L.Coun ts , I n s t r u m e n t a t i o n Am p l ifi e r Ap p l ic a t i o n

G u i d e, Ana log Devices, Incorpora ted, Norwood, MA, 1991.


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SECTION 2

HIGH SPEED OP AMPS

Driving Capacitive Loads

Cable Driving

Single-Supply Considerations

Application Circuits


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SECTION 2

H I G H S P E E D O P AMP S

W a l t J u n g a n d W a l t K est er Modern system design increa singly ma kes us e of high speed ICs a s circuit bu ilding

blocks. With ban dwidths going up a nd u p, deman ds ar e placed on the designer for

faster an d more power efficient circuits. The defau lt high speed a mplifier ha s

chan ged over th e years , with high speed complemen ta ry bipolar (CB) process ICs

such as t he AD846 and AD847 in u se just about ten years a t t his writing. During

th is time, the gener al ut ility/availability of th ese and oth er ICs ha ve raised th e high

speed comm on per form an ce denomina tor t o 50MHz. The most r ecent extended

frequency complemen ta ry bipolar (XFCB) process h igh speed devices su ch as th e

AD8001/AD8002, the AD9631/9632 and the AD8036/AD8037 now extend the

operat ing range into the UH F r egion.

Of course, a tra ditiona l performa nce barrier has been speed, or per ha ps more

accurately, pain less speed. While fast IC am plifiers ha ve been ar ound for some time,

un til more recently they simply ha vent been th e easiest to use. As an exa mple,

devices with su bsta nt ial speed increases over 741/301A era types, na mely the 318-

family, did so at th e expense of relatively poor s ett ling and capacitive loading

char acter istics. Modern CB process par ts like th e AD84X series provide far great er

speed, faster sett ling, and d o so at low user cost. St ill, th e a pplicat ion of high

perform an ce fast am plifiers is n ever en tirely a cookbook pr ocess, so designers still

need t o be wary of ma ny inter -related key issues. This includes not just t he a mplifier

selection, but a lso cont rol of para sitics a nd oth er p oten tially perform an ce-limiting

details in th e sur rounding circuit.

It is worth un derscoring t ha t r easons for t he "speed revolution" lie not just in

affordability of the n ew high speed ICs, but is also rooted in th eir ease of use.

Compa red t o ear lier high speed ICs, CB process devices ar e genera lly more sta ble

with capa citive loads (with h igher pha se mar gins in genera l), have lower DC errors,

consu me less power for a given speed, a nd a re a ll around more "user friendly".

Tak ing this a step fur th er, XFCB family devices, which exten d th e ut ility of th e op

am p to litera lly hun dreds of MHz, are un dersta ndably less str aightforwar d in term s

of th eir application (as is a ny am plifier operat ing over such a ra nge). Thu s, gett ing

th e most from th ese modern devices definitely stresses t he total environmen t

aspects of design.

Anoth er ma jor ea se of use featu re foun d in today's linear I Cs is a much wider ra nge

of supp ly voltage cha ra cterization. While the older 15V sta nda rd is st ill mu ch in

use, ther e is a tr end towards including more performa nce data at popular lower

voltages, such as 5V, or +5V only, single supply operation. The most recent devices

using the lower voltage XFCB process use supply voltages of either 5V, or simply

+5V only. The tr end t owar ds lower su pply volta ges is unm ista ka ble, with a goal of

squeezing th e highest perform an ce from a given volta ge/power circuit environmen t.

These "ease of use" design a spects with curr ent ICs ar e illustra ted in t his chapter,


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along with par asit ic issues, optimizing perform an ce over su pply ran ges, and low

distortion sta ges in a var iety of applicat ions.

D RIVING CAPACITIVE LOADS

Fr om system an d signa l fidelity points of view, tra nsm ission line coupling betweensta ges is best, and is described in some deta il in t he n ext section. However, complete

tr an smission line system design m ay not a lways be possible or pr actical. In a ddition,

various other parasitic issues need careful consideration in high performance

designs. One such pr oblem par asit ic is am plifier load capa cita nce, which poten tially

comes int o play for all wide ban dwidth sit ua tions which do not use tr an smission line

signal coupling.

A genera l design r ule for wideban d linear drivers is th at capacitive loading (cap

loading) effects sh ould always be consider ed. This is becau se PC boar d capacitan ce

can bu ild up quickly, especially for wide and long signa l run s over gr oun d plan es

insu lated by t hin, h igher K dielectr ic. For examp le, a 0.025 PC t ra ce using a G-10

dielectr ic of 0.03 over a groun d pla ne will ru n a bout 22pF/foot (Reference 1). Evenrela tively small load capa cita nce (i.e.,


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CAPACITIVE LOADING ON OP AMP GENERALLY REDUCESPHASE MARGIN AND MAY CAUSE INSTABILITY,

BUT INCREASING THE NOISE GAIN OF THE CIRCUITIMPROVES STABILITY

Figure 2.1

Forcing a h igh n oise gain, is shown in F igure 2.1, where t he capa citively loaded

am plifier with a noise gain of un ity at t he left is seen to be un sta ble, due t o a 1/ -

open loop rolloff inter section on th e Bode diagra m in a n u nst able 12dB/octave

region. For su ch a case, quite often sta bility can be rest ored by intr oducing a higher

noise gain to the sta ge, so th at th e int ersection then occurs in a sta ble 6dB/octave

region, as depicted at t he diagra m right Bode plot.

RAISING NOISE GAIN (DC OR AC) FORFOLLOWER OR INVERTER STABILITY

Figure 2.2

To ena ble a higher n oise gain (which does not necessar ily need t o be the sa me a s th estages signal gain ), use is ma de of resistive or RC pads a t t he a mplifier inpu t, as in

Figur e 2.2. This trick is more broad in scope th an overcompen sat ion, an d ha s th e

adva nt age of not requ iring access to any inter na l amplifier nodes. This genera lly

allows use with an y amp lifier setu p, even voltage followers. The t echnique a dds a n

extra r esistor RD, which works aga inst RF to force th e noise gain of th e sta ge to a

level appr eciably higher th an th e signa l gain (which is unit y in both cases her e).

Assuming tha t CL is a value wh ich pr oduces a pa ra sitic pole nea r t he a mplifiers

na tu ra l crossover, th is loadin g combina tion would likely lead to oscillation due t o the


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excessive phas e lag. However wit h RD conn ected, th e higher am plifier noise gain

produces a new 1/ - open loop rolloff intersection, about a decade lower in

frequency. This is set low enough th at th e extra p ha se lag from CLis no longer a

problem, and am plifier sta bility is rest ored.

A dra wback to th is trick is th at th e DC offset a nd inpu t n oise of th e amplifier a re

ra ised by th e value of th e noise gain, when th e optional CD is notpresent. But, when

CD is used in series with RD, the offset voltage of th e am plifier is not r aised, an d th e

gained-up AC noise component s a re confined t o a frequen cy region above

1/(2pi RD CD). A furt her caut ion is th at the t echn ique can be somewhat tr icky

when separ at ing these opera ting DC and AC regions, an d should be applied

carefully with r egard t o sett ling time (Referen ce 2). Note tha t t hese simplified

examples ar e generic, an d in pra ctice the a bsolute component values sh ould be

ma tched t o a specific amplifier.

Passive cap load compensation, sh own in Figure 2.3, is the most simple (an d m ost

popu lar) isola tion tech nique availab le. It uses a sim ple out-of-the-loop series res is tor

RX to isolate the cap load, and can be used with any amplifier, current or voltagefeed ba ck , FET or bipolar in put.

OPEN-LOOP SERIES RESISTANCE ISOLATES CAPACITIVELOAD FOR AD811 CURRENT FEEDBACK OP AMP

(CIRCUIT BANDWIDTH = 13.5 MHz)

Figure 2.3

As noted, th is technique can be a pplied to virtu ally any am plifier, which is a m ajorrea son why it is so useful. It is shown her e with a curr ent feedback am plifier

suit able for high curr ent line driving, th e AD811, an d it consist s of just t he simple

(passive) series isolation r esistor, RX. This resistors minim um value for st ability

will var y from d evice to device, so the am plifier da ta sheet should be consu lted for

other ICs. Genera lly, inform at ion will be provided as to th e am oun t of load

capa citance tolerat ed, and a suggested minimum resistor value for stability

purposes.


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Dra wbacks of th is appr oach ar e th e loss of ban dwidth a s RX works a gainst CL, the

loss of voltage swing, a possible lower slew rate limit due to I MAXand CL, and a

gain error due to the RX-RL division. Th e gain er ror can be optionally compensa ted

with RIN, which is r at ioed to RF as RL is to RX. In th is example, a 100mA outpu t

from t he op amp in to CLcan slew VOU T at a r at e of 100V/s, far below the int rinsic

AD811 slew rat e of 2500V/s. Although t he dr awba cks ar e serious, th is form of cap

load compen sat ion is n everth eless useful becau se of its simplicity. If the am plifier is

not otherwise protected, then a n R Xresist or of 50-100ohm s sh ould be used with

virtu ally an y am plifier facing capa citive loading. Although a non-inverting a mplifier

is shown, th e technique is equally applicable to invert er st ages.

With very speed h igh am plifiers, or in applications wher e lowest set tling time is

critical, even sm all values of load capacitan ce can be disru ptive to frequency

response, but are nevertheless sometimes inescapable. One case in point is an

am plifier u sed for d riving ADC input s. Since high speed ADC input s quit e often look

capa citive in na tu re, this pr esents a n oil/water type problem. In such cases the

amplifier must be stable driving the capacitance, but it must also preserve its best

ban dwidth a nd set tling time char acter istics. To addr ess th is type of cap load caseperform an ce, Rs and CL dat a for a sp ecified settling time is most a ppropria te.

Some a pplicat ions, in pa rt icular those tha t require dr iving the relatively high

impeda nce of an ADC, do not ha ve a convenient back ter mina tion resistor to damp en

the effects of capacitive loading. At high frequencies, an amplifiers output

impeda nce is rising with frequency and a cts like an inducta nce, which in

combina tion with C L causes pea king or even worse, oscillat ion. When t he ba ndwidth

of an am plifier is a n a ppreciable percenta ge of device ft ,the sit ua tion is complicat ed

by the fact tha t t he loadin g effects a re r eflected ba ck int o its inter na l stages. In spite

of th is, the basic behavior of most very wide bandwidth am plifiers such a s th e

AD8001 is very similar .

In genera l, a sma ll damping resistor (Rs) placed in series with CL will help rest ore

th e desired response (see F igure 2.4). The best choice for th is resist ors valu e will

depend upon t he criterion used in determining th e desired response. Tra ditionally,

simply stability or a n a ccepta ble amount of peak ing has been u sed, but a m ore strict

mea sur e su ch as 0.1% (or even 0.01%) settling will yield differen t values. F or a given

am plifier, a family of Rs - CLcurves exists, su ch as t hose of Figur e 2.4. These da ta

will aid in selecting Rs for a given a pplicat ion.


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AD8001 RS REQIRED FOR VARIOUS CL VALUES

Figure 2.4

The ba sic sha pe of th is cur ve can be easily explained. When CLis very small, no

resist or is necessar y. When CLincreases t o some th reshold value an Rs becomes

necessary. Since th e frequency at which t he da mping is required is related t o the

Rs CLtime consta nt , the Rs needed will initially increa se r apidly from zero, an d

then will decrease as CLis increased further. A relatively strict requirement, such

as for 0.1%, sett ling will gener ally require a larger Rs for a given CL, giving a curve

falling h igher (in ter ms of Rs) tha n th at for a less stringent r equirement, such as

20% overshoot. F or th e comm on gain condition of +2, th ese two curves a re plott ed in

th e figur e for 0.1% sett ling (upper-most cur ve) and 20% overshoot (middle cur ve). It

is also wort h m ent ioning th at higher closed loop gains lessen t he pr oblemdra ma tically, and will requ ire less Rs for t he sa me performa nce. The th ird (lower-

most) cur ve illustr at es th is, demonst ra ting a closed loop gain of 10 Rs requirement

for 20% overshoot for th e AD8001 amp lifier. This can be relat ed to th e ear lier

discussion ass ociat ed with F igure 2.2.

The r ecomm ended valu es for Rs will optimize response, but it is import an t t o note

tha t generally CLwill degra de the ma ximum bandwidth a nd sett ling time

perform an ce which is achievable. In th e limit, a la rge Rs CLtime constant will

dominat e the r esponse. In an y given applicat ion, th e value for Rs should be taken a s

a st ar ting point in an optimizat ion pr ocess which accoun ts for board pa ra sitics an d

other seconda ry effects.

Active or in -th e-loop cap load com pen sa tion can also be u sed as sh own in Figu re

2.5, and th is scheme modifies the passive configu ration to provide feedba ck correction

for the DC & low frequ ency gain error associa ted wit h RX. In contrast to the passive

form , a cti ve com pensa tion can only be used with voltage feedback am pl if iers, beca use

current feedback am plifiers dont allow t he in tegrating conn ection of CF.


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ACTIVE IN-LOOP CAPACITIVE LOAD COMPENSATIONCORRECTS FOR DC AND LF GAIN ERRORS

Figure 2.5

This circuit r etu rn s th e DC feedback from th e out put side of isolat ion r esistor RX,

th us corr ecting for er rors. AC feedback is retu rn ed via CF, which bypas ses RX/RF at

high frequencies. With an appr opria te value of CF (which varies with CL, for fixed

resistan ces) this st age can be adjusted for a well damped tr ansient response

(Reference 2,3). Ther e is still a bandwidt h r eduction, a h eadr oom loss, an d also

(usua lly) a slew ra te r eduction, but th e DC errors can be very low. A dra wback is the

need to tune CF to CL, as even if th is is done well initially, any chan ge to CL will

alt er t he r esponse awa y from flat. The circuit as s hown is useful for volta ge feedback

am plifiers only, becau se capa citor CF provides integra tion ar oun d U1. It also can be

implement ed in invert ing fash ion, by driving the bott om en d of RIN

.

In ternal cap load com pensa tion in volves th e u se of an am pl if ier which in ternal ly has

topological provisions for the effects of external cap loadin g. To the user, th is is th e

most transparent of the various techniques, as it works for any feedback situation, for

any value of load capacitance. Drawbacks are that it produces higher distortion than

does an otherwise similar am plifier with out the network, and the com pensation

against cap loading is somewh at signal level depend ent.


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AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNALCOMPENSATION FOR DRIVING CAPACITIVE LOADS

Figure 2.6

The int ern al cap load compen sat ed amp lifier soun ds at first like th e best of all

possible worlds, since the u ser n eed do noth ing at all to set it u p. Figure 2.6, asimplified diagra m of an am plifier with in ter na l cap load compen sat ion, shows how

it works. The cap load compen sat ion is t he CF -resistor n etwork sh own ar ound the

un ity gain out put sta ge of th e am plifier - note th at th e dott ed connection of th is

net work u nder scores t he fact tha t it only ma kes its presen ce felt for certa in load

conditions.

Un der n orma l (non-capa citive or light r esistive) loadin g, ther e is limited

input/outpu t volta ge error across th e output stage, so the CF network then sees a

rela tively sma ll volta ge drop, and ha s little or n o effect on t he a mplifiers high

impeda nce compensa tion node. However when a capa citor (or oth er h eavy) load is

present, t he h igh curr ents in th e output stage produce a voltage difference across th e

CF net work , which effectively adds capacitan ce to th e compen sat ion n ode. With th isrelatively heavy loading, a net larger compensation capacitance results, and reduces

the amplifier speed in a man ner which is ada ptive to the extern al capacitance, CL.

As a poin t of referen ce, n ote that it requ ires 6.3m A pea k to suppor t a 2V p-p sw in g

across a 100pF load at 10MHz .

Since this mechanism is resident in t he am plifier outpu t st age an d it affects t he

overa ll compen sat ion cha ra cteristics dynam ically, it a cts independen t of th e specific


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feedback hooku p, as well as size of the exter na l cap loading. In other words, it can be

tr an sparen t t o the user in the sen se tha t n o specific design conditions n eed be set t o

ma ke it work (oth er t ha n selecting an IC wh ich em ploys it). Some a mplifiers usin g

intern al cap load compensat ion a re t he AD847 and th e AD817, and th eir dual

equivalent s, AD827 an d AD826.

Ther e ar e, however, some caveats a lso associat ed with th is int ern al compen sat ion

scheme. As with th e passive compensat ion techniques, ban dwidth decreases as the

device slows down t o prevent oscillation with higher load curr ent s. Also, this

ada ptive compensat ion n etwork has its greatest effect wh en enough output curr ent

flows t o produce significan t voltage drop a cross t he CF net work . Conversely, at

sma ll signal levels, th e effect of the net work on speed is less, so great er r inging may

actually be possible for some circuits for lower-level outputs.

RESPONSE OF INTERNAL CAP LOADCOMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL

Figure 2.7

The dynam ic nat ur e of this intern al cap load compensat ion is illustr ated in Figure

2.7, which shows an AD817 un ity gain invert er being exercised at both high a nd low

output levels, with common conditions of Vs = 15V, RL= 1kohm, CL= 1nF , and

usin g 1kohm in put /feedback resistors. In both photos the inpu t signal is on t he top

tr ace and t he output signa l is on the bottom t ra ce, and th e time scale is fixed. In the10Vp-p out put (A) photo at th e left, th e out put ha s slowed down a ppreciably to

accommodate t he capa citive load, but sett ling is still relat ively clean, with a sm all

percent age of overshoot. This indicates t ha t for t his high level case, the ba ndwidth

redu ction du e to CL is most effective. However, in th e (B) photo at th e right , th e

200mVp-p outpu t sh ows great er overshoot a nd r inging, for t he lower level signa l.

The point is made t ha t, to some degree at least, the relative cap load immun ity of

th is type of int ern ally cap load compen sat ed am plifier is signa l dependent .


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Finally, because the circuit is based on a nonlinear principle, the internal network

affects distortion a nd load drive ability, and th ese factors influen ce amplifier

perform an ce in video applicat ions. Th ough th e net work s pr esence does n ot by a ny

mea ns ma ke devices like th e AD847 or AD817 unu sable for video, it does not per m

practical analog design techniques

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