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    DESIGN AND VERIFICATION OF SPI(SER

    PERIPHERAL INTERFACE) PROTOCO

    CHAVAN SUYOG MADHU

    13MVD0058 Guide:

    Prof.Rajeev Pankaj N.

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    OBJECTIVES

    Design Seria Peri!"era In#erfa$e %SPI & !ro#o$o using Verio

    Verifi$a#ion 'sing 'niversa Verifi$a#ion (e#"odoog)

    *. Cons#ru$#ing 'V( Tes#+en$" ,r$"i#e$#ure using S)s#e- V

    and O+je$# Orien#ed Progra--ing %OOP&.

    . Tes#$ases genera#ion for /un$#ionai#) Verifi$a#ion0. (a1i-i2e Coverage

    3. /inding Bugs

    Too 'sed 45ues#aSi- %(en#or Gra!"i$s&

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    INTROD'CTION

    SPI %Seria Peri!"era In#erfa$e& is an in#erfa$e #"a# fa$i

    #ransfer of syn!"#n#$sseria da#a.

    SPI %Seria Peri!"era In#erfa$e& is a s)n$"ronous seria da#a

    o!era#es in %$&& '$&*-ode.

    I# $o--uni$a#es in -as#er6save -ode 7"ere #"e -as#+n+,+-,s#"e da#a fra-e.

    (u#i!e save devi$es are ao7ed 7i#" individua sa

    ine%SS&.

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    8ITER,T'RE S'RVE9

    T"ere are o#"er $o--uni$a#ion !ro#o$os ike ETERNET; '

    E1!ress. Bu# #"ese !ro#o$os are -ean# for ou#side #"e +o1

    $o--uni$a#ion.

    SPI is of#en $onsidered for on

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    SPI (OD'8E

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    SPI CORE ,RCITECT'RE

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    DESIGN /E,T'RES

    /u du!e1 s)n$"ronous seria da#a #ransfer

    Varia+e eng#" of #ransfer 7ord u! #o *= +i#s

    (SB or 8SB firs# da#a #ransfer

    R1 and T1 on +o#" rising or faing edge of seria $o$k

    inde!enden#)

    /u) s#a#i$ s)n$"ronous design 7i#" one $o$k do-ain

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    OPER,TION

    OPER,TION

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    >ISBONE INTER/,CE SIGN,8S

    SPI E?TERN,8 SIGN,8S

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    CORE REGISTERS 8IST

    CONTRO8 ,ND ST,T'S REGISTER%CTR8&

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    VERI/IC,TION PROCESS

    (ain !ur!ose is #o -ake sure #"e devi$e $an a$$o-!is" #"e #su$$essfu)

    /inding Bugs

    Verifi$a#ion avoids !rodu$# faiure +) re-oving #"e +ugs

    In#egra !ar# of deveo!-en# of an) IP $ore

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    S9STE( VERI8OG /OR VERI/IC,TI

    ard7are Verifi$a#ion 8anguage

    Cons#rained 4rando- s#i-uus genera#ion

    /un$#iona $overage

    ig"er 8eve s#ru$#ures ;es!e$ia) O+je$# Orien#ed Progra-

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    O!en sour$e i+rar) dire$#) !rovided fro- ,$$eera.

    Co-!a#i+e 7i#" an) D8 si-ua#or #"a# su!!or#s S)s#e-Veriog

    If Tes#+en$" is !ro!er) designed; i# is "ig") reusa+e.

    Tes# $ases 7ri##en as se!ara#e $asses.

    Configura+e; /e1i+e Tes#+en$"es

    ,# run #i-e; 7e $an de$ide 7"i$" #es#$ases #o run in 7"i$" order

    'NIVERS,8 VERI/IC,TION

    (ETODO8OG9 %'V(&

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    TESTBENC ,RCITECT'RE

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    'V( Cass 8i+rar)

    !rovides a #"e +uiding +o$ks : verifi$a#ion $o-!onen#s and

    environ-en#s.

    T"e i+rar) $onsis#s of +ase $asses; u#ii#ies; and -a$ros.

    >e $an e1#end #"is !redefined $ass #o $rea#e our o7n $ass u

    In"eri#an$e.e.g . uv-@-oni#or;uv-@#es#;uv-@driver

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    VERI/IC,TION P8,N

    Des$ri!#ion of 7"a# fea#ures of design need #o +e e1er$ised an#e$"niAues #o +e used .

    I . /ea#ures E1#ra$#ion Pan

    (ISO and (OSI signas are !ro!er) genera#ed

    Da#a #ransfer o$$urs $orre$#) on Nega#ive or !osi#ive edge of $o$k

    Transfer of 8SB or (SB +i# firs#

    Transfer of varia+e $"ara$#er eng#" 7ord

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    Verifi$a#ion Pan%Con#.&

    II. Coverage Pan/un$#iona Coverage

    Code Coverage

    *. Bran$" Coverage

    . S#a#e-en# Coverage0. Togge Coverage

    3. /EC Coverage

    .Covergrou! is 7ri##en 7i#" a !ossi+e $over!oin#s

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    TEST CASES OVERVIE.

    * ,SS*;8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd3. ,SS*;8SB; T1@NEG; R1@NEG*; C"ar eng#"Fd00.

    0 ,SS*;8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd00.

    3 ,SS*;8SB; T1@NEG*; R1@NEG; C"ar eng#"FdH.

    H ,SS*;8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd.

    ,SS*;8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd*.

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    * ,SS*;8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd3.

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    UVM REPORT (T"-ns"+, .+n'#/)

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    UVM REPORT (Transcript Window)

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    ,SS*8SB; T1@NEG; R1@NEG*; C"ar eng#"Fd00.

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    0 ,SS*8SB; T1@NEG*; R1@NEG; C"ar eng#"Fd00.

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    3 ,SS*8SB*; T1@NEG; R1@NEG*; C"ar eng#"FdH.

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    H ,SS*8SB; T1@NEG; R1@NEG*; C"ar eng#"Fd.

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    ,SS*8SB*; T1@NEG*; R1@NEG; C"ar eng#"Fd*.

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    /'NCTION,8 COVER,GE REPORT

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    CODE COVER,GE REPORT

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    CONC8'SION

    T"e Co-!e#e /un$#ionai#) $an +e e1er$ised using 'V(.

    'V( is -os# effi$ien# 7a) for +ug de#e$#ion.

    Deveo!ing and Verifi$a#ion of IP +e$o-es ver) si-!e +) us

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    RE/ERENCES

    Tian1iang 8iu and 9unfeng >ang;KIP Design of universa devi$es SPI In#erfa$$onferen$e **.

    ,.M. Oudjida; (.8. Berrandjia; ,. 8ia$"a; R. Tiar; M. Ta"raoui 9.N. ,"ou-

    KDesign and Tes# of Genera

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    RE/ERENCES

    Jani$k Bergeron; K>ri#ing Tes#+en$"es: /un$#iona Verifi$a#ion of D8 (ode'S; =

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    Tan *o#+++


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