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© 2009 Pearson Education, Upper Saddle River, NJ 07458 !ll Ri"#ts ReservedFloyd, Digital Fundamentals, 10 th ed

$i"ital

%unda&entals'ent# Edition

Floyd

(#apter 7

© 2008 Pearson Education

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! latch is a te&porar) stora"e device t#at #as t*o sta+lestates +ista+le- .t is a +asic /or& o/ &e&or)

Su&&ar)Su&&ar)

atc#es

'#e S1R Set1Reset- latc# is t#e &ost +asic t)pe .t can +e constructed/ro& N R "ates or N!N$ "ates 3it# N R "ates, t#e latc# respondsto active1 . inputs6 *it# N!N$ "ates, it responds to active1 3inputs

N R !ctive1 . atc# N!N$ !ctive1 3 atc#

R

S

Q Q

Q

S

RQ

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'#e active1 . S-R latc# is in a sta+le latc#ed- condition*#en +ot# inputs are 3

Su&&ar)Su&&ar)

atc#es

R

S

Q

Q

!ssu&e t#e latc# is initiall) RESE'Q 0- and t#e inputs are at t#eir

inactive level 0- 'o SE' t#e latc#Q -, a &o&entar) . si"nal

is applied to t#e S input *#ile t#e R re&ains 3

0

0

R

S

Q

Q

0

0

'o RESE' t#e latc# Q 0-, a&o&entar) . si"nal isapplied to t#e R input *#ile t#e S re&ains 3

0

0 0

0

atc#initiall)RESE'

atc#initiall)SE'

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S

R

'#e active1 3 S-R latc# is in a sta+le latc#ed- condition*#en +ot# inputs are .

Su&&ar)Su&&ar)

atc#es

Q

Q0

0

atc#initiall)RESE'

Q

Q

0

0

atc#initiall)SE'

S

R

!ssu&e t#e latc# is initiall) RESE'Q 0- and t#e inputs are at t#eir

inactive level - 'o SE' t#e latc#Q -, a &o&entar) 3 si"nal

is applied to t#e S input *#ile t#e R re&ains .

'o RESE' t#e latc# a &o&entar)3 is applied to t#e R input

*#ile S is .

Never appl) an active set andreset at t#e sa&e ti&e invalid-

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'#e active1 3 S-R latc# is availa+le as t#e 74 S279! .(

Su&&ar)Su&&ar)

atc#es

(5)

1S1(2)

(1)

(6)

1R

2S

2R

1S2 (4)

(9)

(13)

(7)

(3)

(14)

3S1(11)

(10)

(15)

3R

4S

4R

3S2(12)

Q

2Q

Q

4Q

74 S279!

.t /eatures /our internal latc#es *it#t*o #avin" t*o S inputs 'o SE' an)o/ t#e latc#es, t#e S line is pulsed lo*

.t is availa+le in several pac:a"es

1

2

Position to 2

Position2 to

S

R

Q

V ((

S-R latc#es are /re;uentl) used /ors*itc# de+ounce circuits as s#o*n<

S

R

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! "ated latc# is a variation on t#e +asic latc#

Su&&ar)Su&&ar)

atc#es

'#e "ated latc# #as an additionalinput, called ena+le EN - t#at &ust

+e . in order /or t#e latc# to

respond to t#e S and R inputs

R

S Q

Q

EN

S#o* t#e Q output *it#relation to t#e input si"nals!ssu&e Q starts 3=eep in &ind t#at S and R are onl) active *#en EN is .

S R

EN Q

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Su&&ar)Su&&ar)

atc#es

'#e D latc# is an variation o/ t#e S-R latc# +ut co&+inest#e S and R inputs into a sin"le D input as s#o*n<

! si&ple rule /or t#e D latc# is<Q /ollo*s D *#en t#e Ena+le is active

D

EN

Q

QQ

Q D

EN

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Su&&ar)Su&&ar)

atc#es

'#e trut# ta+le /or t#e D latc# su&&ari>es its operation ./ EN is 3, t#en t#ere is no c#an"e in t#e output and it islatc#ed

Inputs

Comments

01X

EN D

110

Outputs

01

Q 0

QQ

10

Q 0

RESETSET

o "#$n%e

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Su&&ar)Su&&ar)

atc#es

$eter&ine t#e Q output /or t#e D latc#, "iven t#e inputs s#o*n

EN

Q

D

Notice t#at t#e Ena+le is not active durin" t#ese ti&es, sot#e output is latc#ed

Q

Q D

EN

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Su&&ar)Su&&ar)

%lip1/lops

! /lip1/lop di//ers /ro& a latc# in t#e &anner it c#an"esstates ! /lip1/lop is a cloc:ed device, in *#ic# onl) t#ecloc: ed"e deter&ines *#en a ne* +it is entered

'#e active ed"e can +e positive or ne"ative

D Q

C

Q

(a) Positive edge-triggered

D Q

C

Q

(b) Negative edge-triggered

$)na&icinputindicator

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Su&&ar)Su&&ar)

%lip1/lops

'#e trut# ta+le /or a positive1ed"e tri""ered $ /lip1/lops#o*s an up arro* to re&ind )ou t#at it is sensitive to its

D input onl) on t#e risin" ed"e o/ t#e cloc:6 ot#er*ise it is

latc#ed '#e trut# ta+le /or a ne"ative1ed"e tri""ered $/lip1/lop is identical e?cept /or t#e direction o/ t#e arro*

Inputs

Comments

1

C&'D

Outputs

1

QQ

0 SET0 0 1 RESET

Inputs

Comments

1

C&'D

Outputs

1

QQ

0 SET0 0 1 RESET

a- Positive1ed"e tri""ered +- Ne"ative1ed"e tri""ered

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Su&&ar)Su&&ar)

%lip1/lops

'#e J1= /lip1/lop is &ore versatile t#an t#e $ /lip /lop .naddition to t#e cloc: input, it #as t*o inputs, la+eled J and

K 3#en +ot# J and K , t#e output c#an"es states

to""les- on t#e active cloc: ed"e in t#is case, t#e risin"ed"e-Inputs

Comments

1

1 1

1

C&'K J

Outputs

1

QQ

Q 0

Q 0

Q 0

Q 0

0 SETTo%%le

0

0

00 0 1 RESET

o "#$n%e

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Su&&ar)Su&&ar)

%lip1/lops

$eter&ine t#e Q output /or t#e J-K /lip1/lop, "iven t#e inputs s#o*n

CLK

Q

K

J

CLK

K

J

Q

Q

Notice t#at t#e outputs c#an"e on t#e leadin" ed"e o/ t#e cloc:

Set 'o""le Set atc#

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Su&&ar)Su&&ar)

%lip1/lops

CLK

D

CLK

Q

Q

! $1/lip1/lop does not #ave a to""le &ode li:e t#e J1= /lip1/lop, +ut )ou can #ard*ire a to""le &ode +) connectin" Q

+ac: to D as s#o*n '#is is use/ul in so&e counters as )ou

*ill see in (#apter 8%or e?a&ple, i/ Q is 3, Q is

. and t#e /lip1/lop *ill to""leon t#e ne?t cloc: ed"e @ecause t#e

/lip1/lop onl) c#an"es on t#e activeed"e, t#e output *ill onl) c#an"eonce /or eac# cloc: pulse

$ /lip1/lop #ard*ired /ora to""le &ode

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Su&&ar)Su&&ar)

%lip1/lops

S)nc#ronous inputs are trans/erred in t#e tri""erin" ed"eo/ t#e cloc: /or e?a&ple t#e D or J-K inputs- Aost /lip1/lops #ave ot#er inputs t#at are asynchronous , &eanin"

t#e) a//ect t#e output independent o/ t#e cloc:'*o suc# inputs are nor&all) la+eled

preset PRE - and clear CLR- '#eseinputs are usuall) active 3 ! J1=

/lip /lop *it# active 3 preset and( R is s#o*nCLK

K

J

Q

Q

PRE

CLR

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Su&&ar)Su&&ar)

%lip1/lops%lip1/lops

$eter&ine t#e Q output /or t#e J-K /lip1/lop, "iven t#e inputs s#o*n

CLK

K

J

Q

Q

PRE

CLRSet 'o""le Reset 'o""le

Set

Set

Reset

atc#

CLK

K

J

Q

PRE

CLR

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Propagation delay time is speci/ied /or t#e risin" and/allin" outputs .t is &easured +et*een t#e 50B level o/ t#ecloc: to t#e 50B level o/ t#e output transition

Su&&ar)Su&&ar)

%lip1/lop (#aracteristics

50B point on tri""erin" ed"e

50B point

50B point on 31to1. transition o/ Q

t PLH t PHL

( = ( =

Q Q 50B point on . 1to13 transition o/ Q

'#e t)pical propa"ation dela) ti&e /or t#e 74! ( /a&il) (A S-is 4 ns Even /aster lo"ic is availa+le /or speciali>ed applications

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!not#er propagation delay time speci/ication is t#e ti&ere;uired /or an asynchronous input to cause a c#an"e in t#eoutput !"ain it is &easured /ro& t#e 50B levels '#e

74! ( /a&il) #as speci/ied dela) ti&es under 5 ns

Su&&ar)Su&&ar)


50B point

t PLH t PHL

Q 50B point50B point

50B point

Q

PRE CLR

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Set-up time and hold time are ti&es re;uired +e/ore anda/ter t#e cloc: transition t#at data &ust +e present to +erelia+l) cloc:ed into t#e /lip1/lop

Su&&ar)Su&&ar)


Setup time is t#e &ini&u&ti&e /or t#e data to +e presentbefore t#e cloc:

Hold time is t#e &ini&u&ti&e /or t#e data to remain a/tert#e cloc:

CLK

D

CLK

D

Set1up ti&e, t s

old ti&e, t H

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t#er speci/ications include &a?i&u& cloc: /re;uenc),&ini&u& pulse *idt#s /or various inputs, and po*erdissipation '#e po*er dissipation is t#e product o/ t#e

suppl) volta"e and t#e avera"e current re;uired

Su&&ar)Su&&ar)


! use/ul co&parison +et*een lo"ic /a&ilies is t#e speed-power product *#ic# uses t*o o/ t#e speci/ications discussed< t#e avera"e propa"ationdela) and t#e avera"e po*er dissipation '#e unit is ener")

3#at is t#e speed1po*er product /or 74! (74!CUse t#e data /ro& 'a+le 715 to deter&ine t#e ans*er

%ro& 'a+le 715, t#e avera"e propa"ation dela) is 4 D ns'#e ;uiescent po*er dissipated is &3 '#ere/ore, t#espeed1po*er product is 5 pJ

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Su&&ar)Su&&ar)

%lip1/lop !pplications

Principal /lip1/lop applications are /orte&porar) data stora"e, as /re;uenc)dividers, and in counters *#ic# are

covered in detail in (#apter 8-

')picall), /or data storage applications,a "roup o/ /lip1/lops are connected to

parallel data lines and cloc:ed to"et#er

$ata is stored until t#e ne?t cloc: pulse

C

R

C

R

C

R

C

R

Parallel datainput lines

(loc:

(lear

utput

linesQ0

Q

Q2

Q

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Su&&ar)Su&&ar)

%lip1/lop !pplications

%or frequency division , it is si&ple to use a /lip1/lop int#e to""le &ode or to c#ain a series o/ to""le /lip /lops tocontinue to divide +) t*o

ne /lip1/lop *ill divide f in +) 2, t*o /lip1/lops *illdivide f in +) 4 and so on-! side +ene/it o/ /re;uenc)division is t#at t#e output#as an e?act 50B dut)c)cle

. .

CLK

K

J Q !

CLK

K

J

f in

Q@ f out

3ave/or&s<

f in

f out

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Su&&ar)Su&&ar)

ne1S#ots

'#e one-shot or monosta le &ultivi+rator is a device*it# onl) one sta+le state 3#en tri""ered, it "oes toits unsta+le state /or a predeter&ined len"t# o/ ti&e,t#en returns to its sta+le state

%or &ost one1s#ots, t#e len"t# o/ ti&ein t#e unsta+le state t W - is deter&ined

+) an e?ternal RC circuit 'ri""er

C E ' RE '

FV

(

R G(

Q

Q

t W

'ri""er

Q

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Su&&ar)Su&&ar)

ne1S#ots

Retri""era+le one1s#ots respond to an) tri""er, even i/

it occurs in t#e unsta+le state ./ it occurs durin" t#eunsta+le state, t#e state is e?tended +) an a&ounte;ual to t#e pulse *idt#

Retri""ers

t W

'ri""er

Q

Retri""era+le one1s#ot<

Nonretri""era+le one1s#ots do not respond to an)tri""ers t#at occur durin" t#e unsta+le state

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Su&&ar)Su&&ar)

ne1S#ots

!n application /or a retri""era+le one1s#ot is a po*er/ailure detection circuit 'ri""ers are derived /ro& t#eac po*er source, and continue to retri""er t#e one

s#ot .n t#e event o/ a po*er /ailure, t#e one1s#ot isnot tri""ered and an alar& can +e initiated

t W

t W

t W

Retri""ers Retri""ers

'ri""ersderived/ro& ac

Q

Aissin" tri""erdue to po*er/ailure

Po*er /ailure indication

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(7)

(6)

(2)

(3)

(5)

(4) ( )

(1)

Su&&ar)Su&&ar)

'#e 555 ti&er

'#e 555 ti&er can +e con/i"ured in various *a)s,includin" as a one1s#ot ! +asic one s#ot is s#o*n '#e

pulse *idt# is deter&ined +) R C and is appro?i&atel) t W

R C

'#e tri""er is ane"ative1"oin"

pulse

RESE D!SCH

HRES

R!""ND

C#N

#$

V ((

%V ((

t W R C

C

R

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(7)

(6)

(2)

(3)

(5)

(4) ( )

(1)

Su&&ar)Su&&ar)

'#e 555 ti&er

RESE D!SCH

HRES

R!""ND

C#N

#$

V ((

%V ((

t W R C

C

R

$eter&ine t#e pulse *idt# /or t#e circuit s#o*n

t W R C 0 : Ω- 2 2µ%-

0 : Ω

2 2µ%

24 2 &s

F 5 H

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Su&&ar)Su&&ar)

'#e 555 ti&er

'#e 555 can +e con/i"ured as a +asic asta+le &ultivi+rator*it# t#e circuit s#o*n .n t#is circuit C c#ar"es t#rou"#

R and R2 and disc#ar"es t#rou"# onl) R2 '#e output

/re;uenc) is "iven +)<

'#e /re;uenc) and dut) c)cleare set +) t#ese co&ponents

( )244

2 f

R R C =

+(7)

(6)

(2)

(3)

(5)

(4) ( )

(1)

RESE D!SCH

HRES

R!""ND

C#N

#$

V ((

C

R

R2

%V ((

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Su&&ar)Su&&ar)

'#e 555 ti&er

iven t#e co&ponents, )ou can read t#e /re;uenc) /ro&t#e c#art !lternativel), )ou can use t#e c#art to pic:co&ponents /or a desired /re;uenc)

(7)

(6)

(2)

(3)

(5)

(4) ( )

(1)

RESE D!SCH

HRES

R!""ND

C#N

#$

V ((

C

R

R2

%V ((

10

1*0

0*1

0*01

0*0010*1 1*0 10 100 1*0+ 10+ 100+

100

C 8

, µ

% -

f >-

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© 2009 Pearson Education, Upper Saddle River, NJ 07458 !ll Ri"#ts Reserved%lo)d, $i"ital %unda&entals, 0 t# ed

Selected =e) 'er&sSelected =e) 'er&s

Latch

Bistable

Clock

D flip-flop

J-K flip-flop

A bistable digital circuit used for storing a bit.

Having two stable states. Latches and flip-flops arebistable multivibrators.

A triggering input of a flip-flop.

A type of bistable multivibrator in which theoutput assumes the state of the D input on the

triggering edge of a clock pulse.

A type of flip-flop that can operate in the SET,RESET, no-change, and toggle modes.

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Selected =e) 'er&sSelected =e) 'er&s

Propagation delay time

Set-up time

Hold time

Timer

The interval of time required after an input signalhas been applied for the resulting output signal tochange.The time interval re;uired for the input levels to be

on a digital circuit.

'#e ti&e interval re;uired /or t#e input levels tore&ain steady to a flip-flop after the triggeringedge in order to reliably activate the device.

! circuit t#at can +e used as a one1s#ot or as anoscillator .

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'#e output o/ a $ latc# *ill not c#an"e i/

a t#e output is 3

+ Ena+le is not activec $ is 3

d all o/ t#e a+ove


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2 '#e $ /lip1/lop s#o*n *ill

a set on t#e ne?t cloc: pulse

+ reset on t#e ne?t cloc: pulsec latc# on t#e ne?t cloc: pulse

d to""le on t#e ne?t cloc: pulse


CLK

D

CLK

Q

Q

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%or t#e J1= /lip1/lop s#o*n, t#e nu&+er o/ inputs t#atare as)nc#ronous is

a

+ 2

c

d 4


CLK

K

J

Q

Q

PRE

CLR

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4 !ssu&e t#e output is initiall) . on a leadin" ed"etri""ered J1= /lip /lop %or t#e inputs s#o*n, t#e output*ill "o /ro& . to 3 on *#ic# cloc: pulseC

a

+ 2

c

d 4


CLK

K

J

2 4

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5 '#e ti&e interval illustrated is called

a t P

+ t P

c set1up ti&e

d #old ti&e


50B point on tri""erin" ed"e

50B point on 31to1. transition o/ Q

( =

Q

C

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© 2009 Pearson Education, Upper Saddle River, NJ 07458 !ll Ri"#ts Reserved%lo)d, $i"ital %unda&entals, 0 t# ed© 2008 Pearson Education

CLK

D

C

D '#e ti&e interval illustrated is called

a t P

+ t P

c set1up ti&e

d #old ti&e

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7 '#e application illustrated is a

a asta+le &ultivi+rator

+ data stora"e device

c /re;uenc) &ultiplier

d /re;uenc) divider


. .

CLK

K

J Q !

CLK

K

J

f in

Q@ f out

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8 '#e application illustrated is a


+ data stora"e device


d /re;uenc) divider

C

R

C

R

C

R

C

R

Parallel datainput lines

(loc:

(lear

utput

linesQ0

Q

Q2

Q

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9 ! retri""era+le one1s#ot *it# an active . output #asa pulse *idt# o/ 20 &s and is tri""ered /ro& a D0 > line'#e output *ill +e a

a series o/ D 7 &s pulses

+ series o/ 20 &s pulses

c constant 3

d constant .


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0 '#e circuit illustrated is a


+ &onosta+le &ultivi+rator


d /re;uenc) divider

(7)

(6)

(2)

(3)

(5)

(4) ( )

(1)

RESE D!SCH

HRES

R!""ND

C#N

#$

V ((

%V ((

C

R

R2

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!ns*ers<

+

2 d

+

4 c

5 +

D d

7 d

8 +

9 d

0 a

pp07 floyd

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