Power Supply Design Seminar

GaN FET-Based CCM Totem-Pole Bridgeless PFC

Reproduced from2014 Texas Instruments Power Supply Design Seminar

SEM2100, Topic 6

TI Literature Number: SLUP327

© 2014, 2015 Texas Instruments Incorporated

Power Seminar topics and online power- training modules are available at:

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GaN FET-Based CCM Totem-Pole Bridgeless PFC Zhong Ye, Alvaro Aguilar, Yitzhak Bolurian and Brian Daugherty

AbstrAct

Gallium nitride (GaN) technology has recently gained traction in power conversion applications due to the superior switching characteristics and improved figure of merit. Safety GaNs with low parasitic capacitance and zero reverse recovery lead to higher switching frequency and efficiency, opening up new applications and topology options. Continuous conduction mode (CCM) totem-pole PFC is an example topology that benefits from the GaN merits. Compared with commonly used dual-boost bridgeless PFC topologies, the CCM totem-pole bridgeless PFC reduces the number of semiconductor switches and boost inductors by half, while pushing peak efficiency above 98.5%. The root cause of current spike in the AC crossover region is analyzed and solutions are provided. A 750W totem-pole PFC prototype is built to characterize the experimental safety GaN with an integrated gate driver and demonstrate the performance improvements. Keywords-GaN; PFC; totem-pole; digital control

I. IntroductIon

When a button is pushed on a smart phone, the phone fires up a vast communication network and connects to a datacenter thousands of miles away. The power consumption to carry communication data is invisible and mostly beyond people’s imagination. The total power consumption of the world’s Information Communication Technologies (ICT) ecosystem is approaching 10% of world electricity generation [1]. A single datacenter, like the Facebook datacenter in North Carolina, consumes as much as 40 MW. Two more ambitious 200 MW datacenters in Nevada, US and Chongqing, China are under construction. With the rapidly growing demand of data storage and communication networks, efficiency of continuously operating power systems becomes more and more important. Now more than ever, unprecedented improvements in efficiency will be needed.

Almost all power consumed by ICT ecosystems is converted from AC. The AC input is first rectified and then boosted to a preregulated voltage level. Downstream DC/DC converters convert the voltage into an isolated 48 V or 24 V for telecom wireless systems as well as core voltages for memory and processors. With the emergence and development of MOSFET technology, power conversion efficiency has dramatically increased in the past thirty years. Energy Star 80 PLUS

efficiency specification [2] adds higher efficiency levels for AC/DC rectifiers from Gold to Platinum and continuing on to Titanium since it went into effect in 2007. However, the efficiency improvement is slowing down due to MOSFET’s performance limitations as well as the significant design challenges associated with Titanium level efficiency requirements. To hit 96% Titanium peak efficiency, the budgetary efficiency of power factor correction (PFC) circuit efficiency should be 98.5% and above for high lines and 96.4% and above for low lines. The most promising topologies are bridgeless PFC circuits, which do not have a full-wave AC rectifier bridge and hence reduce related conduction losses. [3] gives a good summary of different bridgeless PFCs’ performance evaluations. The performance evaluations are based on the presumption that MOSFETs or IGBTs are the active switching devices used. Most Titanium-graded AC/DC rectifier designs use the topology of Figure 6 in [3], consisting of two boost circuits. Each boost circuit rates at full power, but it operates only for one half AC line cycle and idles for the other cycle. As such, the PFC converter achieves a good efficiency at the cost of materials and power density [4]. Typically, a totem-pole PFC cannot operate at continuous conduction mode (CCM) efficiently due to the slow reverse recovery of the MOSFET’s body diodes. However, it can achieve

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an excellent efficiency when operating at transition mode (TM) with zero voltage switching (ZVS). Several papers [5-8] have reported the accomplishment of 98.5% - 99% PFC efficiency. For high power applications, multiple totem-pole boost circuits can be interleaved to increase the power level and reduce input current ripple. However, the downside of this approach is control complexity and high driver and zero-current-detection circuit costs. Furthermore, the resulting increased power component count may produce a low power density design. Therefore, it is desirable for this simple totem-pole circuit to operate at CCM efficiently for the high power region and switch to TM with ZVS at light loads. In that way, both high efficiency and high power density can be achieved at the same time. A newly emerging semiconductor switch, Gallium-Nitride (GaN) FET, is maturing and makes such an application possible. Transphorm Inc. has demonstrated a GaN-based totem-pole CCM PFC achieving 99% peak efficiency in APEC 2013 [9]. [10-12] also address the superior switching characteristics of GaN devices as well as application benefits. To better understand GaN characteristics and further address application concerns, especially switching frequency and crossover current spike, this paper discusses: II. Overview of GaN Technology, III. Totem-Pole CCM PFC control, IV. Experiment and V. Conclusion.

II. overvIew of GAn technoloGy

GaN High Electron Mobility Transistor (HEMT) first appeared around 2004. The HEMT structure demonstrates unusually high electron mobility described as a two-dimensional electron gas (2DEG) near the interface of an AlGaN and GaN heterostructure. For this reason, GaN HEMT is also known as heterostructure FET (HFET), or simply called FET. The basic GaN transistor structure is shown in Figure 1 [13]. The source and drain electrodes pierce through the top the AlGaN layer and contact the underlying 2DEG. This creates a low resistance path between the source and drain and results in a naturally on D-mode device. By applying a negative voltage to the gate electrode, which is placed on top of the AlGaN layer, the electrons of the 2DEG are depleted and the transistor is turned off.

Enhancement mode (E-mode) GaN transistor devices use the same foundation process of D-mode GaN devices beginning with growing a thin Aluminum Nitride (AlN) insulator on the top of a Si or SiC substrate. A highly resistive GaN and then a heterostructure of aluminum gallium nitride and GaN are grown on the AlN subsequently. The source electrodes contact with the 2DEG, while the drain electrodes connect to the GaN. Further processing of a gate electrode forms a depletion region under the gate. The basic structure is depicted in Figure 2. To turn on the FET, a positive voltage must be applied to the gate.

B. Physical Property Comparison of GaN, SiC and Si

Physical properties of a semiconductor material determine the end device’s ultimate performance. The key properties that affect the device performance are shown in Table 1.

Properties GaN Si SiCEG (eV) 3.4 1.12 3.2

EBR (MV/cm) 3.3 0.3 3.5VS (x107 cm/s) 2.5 1.0 2.0

µ (cm2/Vs) 990-2000 1500 650Table 1 – Material properties of GaN, SiC

and Si at 300 Kelvin [14-18].

EG is band-gap energy. Semiconductors with EG > 1.4 are usually called wide band gap materials. A material with a larger EG will need

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Figure 1 – D-mode GaN FET structure.

Figure 2 – E-mode GaN FET structure.

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more energy to break an electron from its bond to cross the band gap. It has a lower leakage current and higher temperature stability. EBR is the critical field break down voltage, which directly impacts ionization and avalanche breakdown voltage level. VS is saturation velocity. The peak electron drift velocity determines the switching frequency limitation. μ is the electron mobility, which is inversely proportional to on-resistance. The relationship between the on-resistance and the parameters is [19]:

Compared with a Si device, the on-resistance of silicon carbide is decreased by a factor of about 500 and the values for GaN are even higher for a given size of semiconductor, as shown in the Figure of Merit in Figure 3.

Figure 3 – Theoretical on-resistance vs. blocking voltage capability for silicon, silicon-carbide, and gallium nitride [16].

Silicon (Si) has dominated power applications in the past thirty years, but as its performance approaches the theoretical limit, the performance improvement becomes very limited. Two newly emerging semiconductor materials, SiC and GaN, seem like promising candidates for future high performance applications.

C. GaN Devices Operating in FET Mode and Diode Mode

The output characteristics of D-mode and E-mode GaN FETs are shown in Figure 4 [13]. It is obvious that D-mode devices are inconvenient to use because a negative bias must first be applied

to power devices before a power stage is connected to a DC input. In contrast, E-mode GaN FETs, just like MOSFETs, are normally off and more application-friendly. However, the normally on GaN devices are easier to manufacture and perform significantly better [20]. For a given area or on resistance, D-mode GaN FETs have less than half the gate charge and output capacitance of E-mode GaN FETs. This gives a significant advantage in switching power converter applications. For high voltage GaN devices, most vendors are using D-mode GaN with a cascode LV NMOSFET structure, as shown in Figure 5. The LV NMOS is a 20 V – 30 V silicon N-Channel MOSFET with low Rds-on and a fast reverse recovery body diode. When a positive voltage is applied between the drain and source of the GaN cascode FET, Vds of the internal MOSFET starts to rise if the FET is off, which results in a negative voltage across the GaN device’s gate and source, turning off the GaN device. The Vds of the MOSFET will normally maintain a few volts, which is large enough for the GaN device to stay off. When a gate voltage is applied, the MOSFET is turned on, which shorts the GaN device’s gate and source and subsequently turns on the GaN device. In FET mode, a GaN cascode FET works very much as an integrated MOSFET with extended GaN voltage rating and added GaN resistance. However, the GaN device dominates the output capacitance, which is much less than a counterpart MOSFET’s Coss. A GaN device itself doesn’t have a body diode, but when a reverse current is applied to the GaN cascode FET, the MOSFET’s body diode conducts first, which literally applies Vf of the body diode to the GaN device’s gate and the GaN device is subsequently turned on. As such, the low voltage FET’s body diode acts as the cascode switch “body diode”. This is desirable because an LV MOSFET has lower forward voltage drop and Qrr than a high voltage MOSFET. Excellent body diode behavior is one of the main features and advantages of the GaN cascode FET. Since the requirement for GaN cascode FET driving is the same as traditional MOSFETs, direct drop-in replacement of a MOSFET is another advantage of the GaN cascode FET in terms of application adoption. The downside of the cascode approach is that the

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D. Safety GaN FETTo overcome the drawback of the cascode

structure, a new safety GaN FET structure is introduced here, as shown in Figure 6.

Figure 6 – Safety GaN FET structure.

The safety GaN FET integrates a normally on GaN device, an LV MOSFET, a startup circuit and a gate driver for the GaN device. The MOSFET does the same function as in the GaN cascode FET structure. It ensures that the normally on GaN device turns off before Vcc bias is applied. After Vcc is applied and the gate driver establishes a stable negative bias, the startup logic circuit turns the MOSFET on and it stays on thereafter. Since the GaN device doesn’t have minority carriers, there is no reverse recovery and the GaN has about 10 times less gate capacitance and several times less output capacitance than high voltage MOSFET counterparts. The safety GaN FET fully embraces GaN benefits. The superior switching characteristics promise a new level of switching converter performance. It should also be pointed out that since there is no physical body diode in the safety GaN FET, the GaN device acts as a diode when a negative current passes through the GaN FET and generates a negative voltage across the drain and source. The GaN FET starts to conduct reversely when Vds reaches a certain negative threshold value, which is the “body diode” forward voltage drop. The forward voltage can be high, up to a few volts. It is necessary to turn on the GaN FET to reduce conduction losses when operating at diode mode.

integrated MOSFET has to switch in each switching cycle. The GaN cascode FET inherits some of MOSFET’s switching characteristics, including large gate charge and reverse recovery. These characteristics limit the GaN device’s performance.

Figure 4 – Output characteristics of D-mode GaN FET (top) and E-mode GaN FET (bottom)

[13].

Figure 5 – GaN Cascode FET structure.

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III. totem-pole pfc ccm control

Totem-pole PFC is a good test vehicle to evaluate safety GaN FET performance at the hard-switching mode. A typical totem-pole PFC power circuit is shown in Figure 7. Q3 and Q4 are safety GaN FETs; Q1 and Q2 are AC rectifier FETs, which switch at AC line frequency; and D1 and D2 are surge path diodes. When AC voltage is input and Vac1-Vac2 is in a positive cycle, Q2 is turned on, Q4 acts as an active switch and Q3 works as a boost diode. To reduce the diode’s conduction loss, Q4 operates in a synchronous rectification mode. For negative AC input cycles, the circuit operates in the same manner but with alternating switch functions.

Figure 7 – Totem-pole PFC operates at active switching cycles (top) and freewheel cycles

(bottom) with positive AC input.

As discussed in section II, the “body diode” has a significant forward voltage drop. The GaN FET should be turned on during freewheel period. For CCM operation, the active FET and the freewheel FET switch at duty cycle D and 1-D respectively with certain dead-time inserted. At heavy loads, the inductor current can be all positive, but at light loads, the current can become negative, as shown in Figure 8.

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Certain negative current is helpful for soft switching, but too high negative current could result in a large circulating power and low efficiency. To achieve optimal efficiency, both turn-on and turn-off dead-time of the GaN FETs needs to be controlled in real time based on load and line conditions. Since GaN FET output capacitance, Coss, does not vary much versus Vds voltage, the dead-time, Td_on, from the active FET turning off to the freewheel FET turning on can be calculated with,

where Vo is PFC output voltage and IL_peak is peak inductor current.

The dead-time Td_off, defined as the time from the freewheel FET turning off to the active FET turning on, should be kept as small as possible at CCM. When the zero current detection (ZCD) signal is received, the corresponding PWM is then chopped off to avoid a negative current and circulating power, as shown in Figure 9. As such, the GaN FET works as an ideal diode, which is often called Ideal Diode Emulation (IDE).

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Figure 9 – Ideal diode emulation control.

To implement the CCM control with ideal diode emulation, UCD3138, a fusion digital controller, is chosen. The controller block function is shown in Figure 10. The PFC’s voltage loop is implemented by firmware and the current loop by hardware CLA. IDE is realized by utilizing the controller’s cycle-by-cycle (CBC) hardware, which uses ZCD as a triggering signal.

Figure 10 – UCD3138 for totem-pole PFC control.

To minimize the AC input rectifier diode’s conduction loss, the low speed rectifier diodes are often replaced by low Rds_on MOSFETs, as denoted as Q1 and Q2 in Figure 7. The MOSFETs and high speed GaN FETs, Q3 and Q4, alternate operating states between positive and negative AC input cycles based on AC voltage crossover point detection. This task looks simple, but a lot of consideration should be taken in order to achieve a clean and smooth AC crossover current. The accuracy of the crossover detection is important to maintain proper operating states and operation. The accuracy is often affected by sensing resistor tolerance and phase delay of the sensing circuit filter. A few volts miscalculation could lead to a large current spike. To avoid input AC short

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circuits, caused by premature turning on the rectifier FETs, sufficient blanking time, where both Q1 and Q2 are off, is necessary and should be inserted at the detected crossover point. The typical blanking time is around 100 μs to 200 μs. Since the MOSFETs have significant output capacitance, Coss, the voltage across Q1 and Q2 could hold almost constant in the blanking time. Before the complementary rectifier FET is turned on, the PFC operation stays at the previous state, where the voltage applied to the boost inductor is near zero and the active GaN FET operates at near full duty cycle. At this point, either turning on the complementary rectifier FET or alternating the two GaN FET functions between an active switch and synchronous switch can cause a large voltage second surge to the boost inductor and consequently a large current spike. Theoretically, simultaneously changing the rectifier FETs and the GaN FETs operating state at the ideal AC voltage crossover point could avoid the current spike and maintain the current loop’s negative feedback, but in reality it is difficult to accomplish. Furthermore, any current spike caused by sudden state changes can disturb the current loop and result in a certain level of current ringing. [9] suggests using PFC soft start at the crossover point. The concern is that an AC crossover detection circuit usually has phase offset and may not be precise enough. Changing state too soon or too late could cause an AC line short circuit or current loop positive feedback, which results in a current spike. A new reliable control scheme is proposed in this paper to ensure a smooth state change. Figure 11 shows the timing diagram of the state change.

Figure 11 – PFC state change time diagram.

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The input AC line voltage VAC_L and neutral voltage VAC_N are sensed separately. The resulting subtraction of the two sensed voltages is used for the AC voltage crossover detection, literally a differential sensing scheme. It eliminates Y-Cap current effects on the sensing accuracy. The sign of VAC_L-VAC_N is used to determine the positive and negative cycles of the input. The absolute value of VAC_L-VAC_N is compared with the AC voltage crossover threshold VT_H for the high line or VT_L for the low line to determine if the AC voltage is in the crossover region. If the answer is yes, both rectifier FETs and boost switches are turned off and the control loop’s integrator is stalled. When the AC voltage increases and exits the crossover region, the corresponding rectifier FET is turned on softly. The turn-on speed can be limited by inserting a proper value gate resistor. After the rectifier FET is turned on, a short delay, such as 20 μs, is inserted before the integrator is unstalled and PWM outputs are enabled again.

Iv. experIment

To evaluate the safety GaN FET’s performance and validate the CCM totem-pole PFC control scheme, a 750 W PFC circuit operating at 140 kHz was designed as a test vehicle. The circuit’s key component parameters are listed in Table 2.

Components ParametersEMI Common Mode Chokes

L = 5 mH, 52 mΩ (two windings)

EMI X-Caps 1 μF, 275 VACRelay 177S1D10-12, 7 mΩ contact resistanceQ1,Q2 IPW60R045CPQ3,Q4 Experimental GaN FETs

Rds_on=130 mΩ, Coss = 230 pFBoost Inductor L =300 μH @ 0 A, RDC = 76 mΩOutput capacitor 470 μF, 450 V

Table 2 – 750 W PFC circuit key component parameters.

Figure 12 and Figure 13 show D-mode GaN FET switching on and off waveforms. Vg4 is the gate driver signal, Vds is the drain to source voltage, and IL is the boost inductor current.

Figure 12 – GaN FET switching on waveforms.

Figure 13 – GaN FET switching off waveforms.

As seen in the figures, the GaN FET switches on in 7 ns with a maximum 79 V/ns dv/dt. There is about 10-20 V of ringing observed at the end of switching. The ringing is caused by the resonance of the H-bridge trace leakage inductance and H-bridge output high frequency ceramic capacitor. At turn-off, the Vds rises softly with around 20 V overshoot. The dv/dt is limited by the GaN FET output capacitance. Zero GaN “ body diode” forward recovery characteristics minimize the voltage overshoot amplitude.

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Figure 14 shows the Safety GaN FET “body diode” forward voltage drop. Around 6.6 V forward voltage drop is observed when the “body diode” conducts a current of 2.8 A. When the GaN is turned on, the voltage reduces to tens of mV range depending on the Rds_on of the device. A separate test with a DC current shows that the forward voltage drop ranged from 4.3 V to 7.3 V. To minimize the “body diode” conduction loss, it is necessary to have a good SyncFET control scheme.

Figure 14 – GaN FET “body diode” forward voltage test.

Figure 15 – GaN FET reverse recovery test.

Figure 15 provides reverse recovery comparison data between ST’s Turbo-2 diode STTH8R06D, Cree’s SiC diode C3D04060E and TI’s experimental Safety GaN. ST’s Turbo diode had excellent performance and dominated PFC applications before SiC started to appear in the market around 10 years ago. The ST Turbo diode

turns off softly but has significant reverse recovery, while SiC diode has zero reverse recovery. Inevitable circuit and device terminal leakages primarily cause the observed ringing. TI’s experimental GaN FET also exhibits zero reverse recovery. Due to a larger Coss, compared to SiC’s junction capacitance, a larger ringing is observed, but at lower frequency. The ringing is a free ringing characteristic of zero reverse recovery.

Figure 16 shows AC current spikes and ringing caused by improper state changes and control. The root causes of each spike and ring are marked on Figure 16. Figure 17 shows clean and smooth current waveforms with the proposed control.

Figure 16 – Crossover waveforms at 230 VAC input with Q2 hard switching on, 3.8 V VT_H and

integrator running during blanking time.

Figure 17 – Crossover waveforms at 230 VAC input with Q2 soft on, 7.6V VT_H and stalled

integrator during blanking time.

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Figure 18 and Figure 19 show AC current waveforms at 450 W low line and 750 W high line. 0.999 Power Factor and 3.3% THD at low line and 0.995 Power Factor and 4.0% THD are achieved. Figure 20 shows the PFC efficiency curves. Peak efficiency reached 98.53% at 230 VAC input and 97.1% at 115 VAC input. A low line efficiency spike was observed in the light area, which results from partial ZVS when the PFC operates around the boundary of CCM and DCM.

Figure 18 – AC voltage and current waveforms at 115 V input and 450 W load.

Figure 19 – AC voltage and current waveforms at 230 V input and 750 W load.

Figure 20 – Totem-pole PFC efficiency.

Figure 21 – 750 W Totem-pole PFC prototype.

v. conclusIonsGaN FETs exhibit superior switching

characteristics. Pushing a PFC to 750 W with 8 mm x 8 mm QFN GaN FETs and reaching an efficiency of 98.53% at high line input and 97.1% at low line input with the early stage of experimental GaN samples is a positive sign of the GaN FET potential. With safety GaN FET structure, the FETs have zero “body diode” reverse recovery, making it ideal for totem-pole or half-bridge hard switching applications. The devices operate at a much higher frequency without suffering reverse recovery loss and significant gate loss. It promises a new level of switching converter performance, in terms of efficiency and physical size. To minimize “the body diode” conduction loss, a precise and reliable dead-time and IDE control scheme is necessary. A good controller will play a big role in the success of the safety GaN FET applications.

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Precise AC voltage crossover detection is the precondition to achieve a smooth AC current in the crossover region. The root causes of current spike and ringing were analyzed and a solution provided. The proposed control scheme demonstrates a reliable way to smooth current transition.

GaN-based totem-pole CCM PFC has the potential to operate at TM with ZVS at light loads for efficiency optimization. The control is much more complex. The discussion of the CCM and TM with ZVS control will be covered by a separate paper.

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[2] EPA, “Energy Star Specification 5.0 for Computers,” www.energystar.gov.

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[4] Biela, J.; Kolar, J.W.; Deboy, G., “Optimal Design of a Compact 99.3% Efficient Single-Phase PFC Rectifier,” Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE.

[5] Badstuebner, U.; Miniboeck, J.; Kolar, J.W., “Experimental Verification of the Efficiency/Power-Density (ᵑ–ᵖ) Pareto Front of Single-Phase Double-Boost and TCM PFC Rectifier Systems,” Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE.

[6] Su, B.; Zhang, J.; and Lu, Z., “Totem-Pole Boost Bridgeless PFC Rectifier with Simple Zero-Current Detection and Full-Range ZVS Operating at the Boundary of DCM/CCM,” IEEE Trans. Power Electron., Vol. 26, No. 2, Feb. 2011.

[7] Biela, J.; Power Electron. Syst. Lab., ETH Zurich, Zurich, Switzerland; Hassler, D.; Miniböck, J.; Kolar, J.W., “Optimal Design of a 5kW/dm3 / 98.3% Efficient TCM Resonant

Transition Single-Phase PFC Rectifier,” Power Electronics Conference (IPEC), 2010 International.

[8] Su, B.; Lu, Z., “An Interleaved Totem-Pole Boost Bridgeless Rectifier with Reduced Reverser-Recovery Problems for Power Factor Correction,” IEEE Transactions on Power Electronics, Vol. 25, Issue 6, 2010, pp. 1406 – 1415.

[9] Zhou, L.; Wu, Y.F., “99% Efficiency True-Bridgeless Totem-Pole PFC Based on GaN HEMTs,” www.transphormusa.com.

[10] Nakao, Hiroshi; Yonezawa, Yu; Sugawara, Toshihiko; Nakashima, Yoshiyasu; Horie, Takashi; Kikkawa, Toshihide; Watanabe, Keiji; Shouno, Ken; Hosoda, Tsutomu; Asai, Yoshimori, “2.5-KW Power Supply Unit with Semi-Bridgeless PFC Designed for GaN HEMT,” Applied Power Electronics Conference and Exposition (APEC), 2013.

[11] Mitova, R.; Ghosh, R.; Mhaskar, U.; Klikic, D.; Miao-Xin Wang; Dentella, A., “Investigation of 600-V GaN HEMT and GaN Diode for Power Converter Applications,” IEEE Transactions on Power Electronics, Vol. 29, Issue 5, 2014.

[12] Zhang, Weimin; Xu, Zhuxian; Zhang, Zheyu; Wang, F.; Tolbert, L.M.; Blalock, B.J., “Evaluation of 600 V Cascode GaN HEMT in Device Characterization and All-GaN-Based LLC Resonant Converter,” Energy Conversion Congress and Exposition (ECCE), 2013 IEEE.

[13] Lidow, Alex; Strydom, John; de Rooij, Michael; Ma, Yanping, “Gallium Nitride (GaN) Technology Overview,” www.epc-co.com.

[14] Gaska, R.; Yang, J.W.; Chen, Q.; Khan, Asif; Orlov, A.O.; Snider, G.L.; and Shur, M.S., “Electron Transport in AlGaN-GaN Heterostructures Grown on 6H-SiC Substrates,” App Physics Letters, 72, No.6, pp. 707-709.

[15] Kaminski, N., “State of the Art and Future of Wide Band-Gap Devices,” Proc. EPE 2009, Barcelona, 2009.

[16] Baliga, B.J., “Semiconductors for High-Voltage, Vertical Channel Field-Effect

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[17] Ambacher, O.; Smart, J.; Shealy, J.R.; Weimann, N.G.; Chu, K.; Murphy, M.; Schaff, W.J.; Eastman, L.F.; Dimitrov, R.; Wittmer, L.; Stutzmann, M.; Rieger, W.; and Hilsenbeck, J., “Two-Dimensional Electron Gases Induced by Spontaneous and Piezoelectric Polarization Charges in N- and Ga-Face AlGaN/GaN Heterostructures”, J. Applied Physics, 85, No. 6, pp. 3222-3233.

[18] Tolbert, L.M.; Ozpinecci, B.; Islam, S.K.; and Chinthavali, M.S., “Wide Bandgap Semiconductors for Utility Applications”, www.ioffe.ru/SVA/NSM/Semicond/GaN/index.html.

[19] Kaminski, N., “State of the Art and the Future of Wide Band-Gap Devices,” Power Electronics and Applications, 2009, EPE 2009, 13th European Conference.

[20] Roberts, John and Klowak, Greg, “ GaN Transistors – Drive Control, Thermal Management, and Isolation,” Power Electronics, Feb 19, 2013.

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