Power Quality Monitoring System based on FPGA João Pedro de Matos Serra IST Técnico Lisboa

Abstract— One important problem in electrical power distribution, is the quality of the energy provider to the final users.

There are several factors that reduce the energy quality. The

generalized usage of switched mode power supplies, industry

motors start event, the usage of wind turbines connected to the

power grid providing instability due to wind variation, are good

examples of the problems that can affect energy. It is imperative to

measure and analyse the disturbances induced to energy by these

factors.

The present work's goal is to study and implement a power quality

analysis system. Consists in a data acquisition module to sample

and convert from analogue to digital, the voltage of the power grid

three phases. An FPGA will be used for digital signal processing

and system control. The analysis will attend mainly to sag swell,

interruption and THD.

The system will be stand alone and will save abnormal events to a

memory SD card. It will be possible to connect the system to a

computer for data extraction, system configure and command. Data

extraction will be faster if SD card is unplugged from FPGA and

plugged to a computer to extract data.

Keywords— power quality, data acquisition module,

FPGA, FFT.

I. INTRODUCTION

An FPGA be used together with a data acquisition module to allow capture and processing of power distribution voltage in order to detect defects in power signal. This work center its attention mainly in sag, swell and harmonic distortion events. The characterization of the events is based on IEEE standard 1159 [1]. The acquisition module converts from analog to digital the voltage signal form power and delivers it to the FPGA true SPI protocol for processing and error events detection. A connection to computer is possible with RS-232 interface for retrieving data and event logs. It's also possible to retrieve data with an SD card that is used to store data and events by the FPGA. The FFT algorithm used to calculate the harmonic distortion is based on a modified butterfly diagram algorithm.

II. POWER DISTURBANCE EVENTS

Sag

Sag is distortion in rms value that can be reduced down to 20% of the voltage value. It can be caused by the switching of heavy load or starting of large motor. Fig. 1 represents a typical voltage sag [1].

Fig 1 - Voltage sag [1].

Swell

Swell is defined as an increase of rms value at the power frequency for durations from 0.5 cycle to 1 min. Swells are normally related to system fault conditions. Fig. 2 represents a swell event [1].

Fig 2 - Voltage swell [1].

harmonics

harmonics are sinusoidal voltages or currents with frequencies that are integer multiples of the fundamental, in

power distribution is normally 50 Hz. In this work the interest of the harmonics is to calculate the harmonic distortion that is a relation from the fundamental sinusoid to the sum of the remaining sinusoids present in the signal, equation 1.

( )2

210 2

1

20log dBn

n

A

THDA

+∞

=

=

∑. (1)

Fig 3 represents the harmonic spectrum of a current

waveformion 1

Fig 3 - Current waveform and harmonic spectrum[1].

III. AQUISITION MODULE

The acquisition module is based on two main components, the voltage sensor, and the ADC. The voltage sensor is the LV 25-P [2] in Fig 4, it converts the current that passes by R1 and forces a current in RM creating a voltage proportional to the one applied to input of the system.

Fig 4 - Voltage sensor LV 25-P[3].

The ADC is the AD 7980 [3] from Analog Devices. It has 16 bit resolution and its configured to accept voltages from 0 V to 5 V. for this to be possible it was used an instrumentation amplifier with gain 1 to receive the signal from the sensor, that is between -2.5V and 2.5 V, and add a reference voltage of 2.5 V and drive the ADC with the correct values that it expects. The acquisition module is controlled by the controlling system implemented in the FPGA and sends data by SPI protocol back to the FPGA for processing. The layout of the PCB board was developed with Altium Designer software Fig 5 is the final print for production.

Fig 5 - Printed layout for PCB production.

Fig 6 shows the finalized data equitation module developed for this project.

Fig 6 - Finished Acquisition Module

IV. CONTROL AND PROCESSING IN FPGA

Stratix III FPGA Development Kit was used to implement the control and processing module. The hardware synthesized in the FPGA was described in VHDL language. The module receives the data from the acquisition module sequentially bit by bit and three shift registers rebuild the 16 bit word of the ADC. The signals are stored in 2 banks of RAM memories when one bank is used to stored data the other one's data is being processed. The top module is represented in Fig7.

Fig 7 - Main Block Diagram.

There are two main processing blocks, the FFT and the RMS (SagSwellDetect). They are inside Datapath block in Fig 7. The FFT processing is done with memory banks, one in and one out of a complex multiplication block that implements the simple element of the butterfly diagram algorithm. The FFT works on 16384 points acquired from 10 periods of the power

voltage signal. It is performed in a cycle of N2log being N the 16384 points. That is 14 cycles of the butterfly diagram iterations. Fig 8 is the FFT diagram block.

Fig 8 - FFT diagram Block.

The SagSwellDetect module processes the shift registers data to calculate the rms of the signal. It generates rms value every half period because it has 2 processes running with half period difference and each returns a one period based rms value. Then a comparator detects if there is a failure in the rms level and alerts the main processing state machine to store the data and information the same goes to the harmonic distortion being calculated from FFT. Fig 9 is the SagSwellDetect block diagram.

Fig 9 - SagSwellDetect

Fig 10 shows the a simulated signal and the FFT calculated in the system.

0 2000 4000 6000 8000 10000 12000 14000 16000

−600

−400

−200

0

200

400

600

Sinal de entrada, RMS = 553.3049

Nº de Amostras

Tensão [

V]

0 500 1000 1500 2000 25000

100

200

300

400

500

600

700

FFT

Frequência [Hz]

Tensão [

V]

Fig 10 - simulated signal and the FFT calculated.

Fig 11 shows the a real signal captured by the Acquisition Module and the FFT calculated in the system.

0 2000 4000 6000 8000 10000 12000 14000 16000

−300

−200

−100

0

100

200

300

Sinal de entrada, RMS = 232.8793

Nº de Amostras

Te

nsã

o [V

]

Fig 11 - Real signal

0 500 1000 1500 2000 2500−30

−20

−10

0

10

20

30

40

50

FFT

Frequência [Hz]

Te

nsã

o [

dB

V]

Fig 12 - FFT calculated from the real signal.

Fig 11 shows the a real signal captured by the Acquisition

Module and Fig 12 the FFT calculated in the system.

CONCLUSION

The present work allowed to get much knowledge on the performance of an FPGA based control and processing system and on many aspects of hardware description in VHDL. It was possible to create and a prototype system that can measure some characteristics of power voltage signals and process the data to detect problems. Much has to be perfected in the system, to speed the communication to the computer , the increase of the complex multiplication of the FFT, to perform more than two points multiplication at a time in order to increase the FFT speed and a bather use of the Stratix III Kit peripherals

REFERENCES

[1] IEEE Std 1159-1995 - IEEE Recommended Practice for

Monitoring Electric Power Quality J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68

[2] LV 25-P datasheet

[3] Analog Devices components datashets