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Low Power System DesignLow Power System Design

Module 2 (3 hours):Source of Power Consumption

Jan. 2007

Naehyuck Chang

EECS/CSE

Seoul National University


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Source of PowerConsumption (1)Source of PowerConsumption (1)

Naehyuck Chang

EECS/CSESeoul National University

[email protected]
mailto:[email protected]:[email protected]


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ContentsContents

Overview

Dynamic power Transition probability Signal probability Decreasing the switching activities


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Power and EnergyPower and Energy

Power consumption of digital circuits is defined by the

supply voltage times the current flow from VDD to GND Generally, VDD is constant and IDD is variable

Instantaneous power:

Energy:

Average power:


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Source of Power ConsumptionSource of Power Consumption

Dynamic power

Current flow from VDD to GND when logic transition occurs Static power

Current flow from VDD to GND regardless of logic

transition


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Dynamic power Switching power Short-circuit power Glitch power

Static power

DC current Leakage current

Weak inversion current Drain-induced barrier lowering

Gate-induced drain leakage Channel punch-through Oxide leakage tunneling Hot carrier injection


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Traditional CMOS circuits

Slow operation Negligible dynamic power consumption Electric watches, calculators, etc.

High VDD and Vt Negligible leakage power consumption Small short-circuit current

Modern high-speed CMOS Fast operation Low VDD and Vt Power is the most important design constraints


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Pull-up and pull-down networkPull-up and pull-down network

NMOS pull-up transistor

PMOS pull-downtransistor


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Dynamic PowerDynamic Power

Switching power

A step voltage is applied at t=0

Energy transferred from the power supply


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When

is dissipated by heat is stored in the capacitor The remaining is dissipated by heat again

when high-to-low transition occurs High-to-low transition does not

draw additional current from thepower supply


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Switching power:


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Gate capacitance

: sum of the gate-to-bulk capacitances

Overlap capacitance

Due to Miller effect:

Diffusion capacitance Interconnect capacitance


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Activity Factor:

System clock frequency = f Let fsw = f, where = activity factor

If the signal is a clock, = 1 If the signal switches once per cycle, = Dynamic gates: switch either 0 or 2 times per cycle, = Static gates: depending on design, but typically = 0.1

Switching power:


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Reduced swing

Rail-to-rail swing: VDD to GND When VOH < VDD, swing is VOH to GND Reduced bit-line in memory


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Short-circuit power

Transient current from VDD to GND when logic transitionoccurs


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Short-circuit power


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Glitch power

Power dissipated inintermediate transitionsduring the evaluation ofthe logic function

Unbalanced delay pathsare principle cause

Usually 8% -25% of

dynamic power


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Transition ProbabilityTransition Probability

Dynamic power is data dependent

Activity factor is dependent on the run-time data Switching activity, P0 1, has two components

A static component: function of the logic topology A dynamic component: function of the timing behavior

(glitch) Static transition probability

P0 1 = Pout=0Pout=1= P0(1-P0) With input signal probabilities

PA=1=1/2 and PB=1=1/2 NOR static transition probability

= 3/4 * 1/4 = 3/16

2-input NOR Gate


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Switching activity is a strong function of the input signal

statistics Generalized switching activity of a 2 input NOR gate

P0 1 = P0P1= (1-(1-PA)(1-PB)) (1-PA)(1-PB)

Transition probability for basic gates

Transition probability for 2 input NOR gates


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Transition probability propagation

C: P0 1 = P0P1= (1-PA) PA =1/2 *1/2 = 1/4 D: P0 1 = P0P1= (1-PCPB) PCPB

= (1 (1/2 * 1/2)) x (1/2 * 1/2) = 3/16


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Signal Probability (Advanced)Signal Probability (Advanced)

Switching activity in combinational logic

Boolean difference:

Switching activity in sequential logic Estimation of glitching power


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Decreasing the Switching ActivitiesDecreasing the Switching Activities

No or little performance and/or functional degradation

Different coding techniques Fewer bit transitions between two states

Boolean expressions simplification Gate minimization

Avoid glitches Get rid off unnecessary transitions

Power down modes Turn off parts of that are not in use


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Decreasing the Switching ActivitiesDecreasing the Switching Activities

Gray coding

Hamming distance of one Used when a sequence is

predictable FSMs Address busses

Makes full use of the bit-width

000100

101

111

110

001

011

010


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Source of PowerConsumption (2)Source of PowerConsumption (2)

Naehyuck Chang

EECS/CSESeoul National University

[email protected]
mailto:[email protected]:[email protected]


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ContentsContents

Static power

Leakage power introduction Short-channel effect Leakage power components (VDD-Vt) design space Total power management


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Static PowerStatic Power

DC current

Pseudo NMOS logic


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DC current

Steady current flow from VDD to GND Either logic value is 0 or 1 depending on the logic structure

Mostly when the output is 0


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Leakage current

A transistor switch is a resistive-capacitive networkbetween the power supply and GND Non-ideal off-state characteristics (a finite resistance)

makes current draw even when the transistor is in the cut-off state


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Leakage Power IntroductionLeakage Power Introduction

Long channel (L>1um): negligible leakage Short channel (L>180nm, Tox>30): subthreshold leakage Very short channel (L>90nm, Tox>20): subthreshold+gate leakage Nano scaled (L


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Scaling makes the leakage power worse

Transistor scaling road mapYear 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35

Logic trans/Chip (M) 15 60 235 925 3,650 14,400

Power supply Vdd (V) 1.8 1.5 1.2 0.9 0.7 0.6

Threshold VT (V) 0.5 0.4 0.4 0.35 0.3 0.25


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Drain leakage increases as Vt decreases to meetfrequency demands leading to excessive leakage power

8KW

1.7KW

400W

88W

12W

0%

10%

20%

30%

40%

50%

2000 2002 2004 2006 2008

DrainLeakagePower

10

100

1,000

10,000

100,000

30 40 50 60 70 80 90 100

Temp (C)

Ioff(nA/nm)

180nm

130nm

100nm

70nm

50nm

Source: Intel


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Short-Channel EffectShort-Channel Effect

Long-channel MOSFET Source and drain-to-body PN junction region is relatively smaller

than the entire channel region The extensions of the source and drain depletion regions into the

channel area have a negligible effect on Vt Short-channel MOSFET

Depletion regions around the source and drain terminals becomecloser

Depth of the source and drain depletion regions becomescomparable to the effective channel length

More charge is contributed to the depletion region beneath thegate area by source-to-substrate and drain-to-substratedepletion layers


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Vt roll-off Vt is reduced with

decreasing L Increasing dependence of Vt

on L threaten the futuretechnology scaling due to

variations WID D2D


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Novel device techniques Overcome the drawback of

the short-channel MOSFET Super-halo doping Multiple gate device

Planar devices Lmin = 10nm Silicon-on-insulator (SOI)

device


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Leakage Power ComponentsLeakage Power Components

Reverse bias PN junction leakage

Minority carrier diffusion/drift near the edge of thedepletion region Election-hole pair generation in the depletion region of the

reverse bias junction


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Subthreshold leakage current Weak inversion current The most significant leakage in DSM technologies A MOSFET operates in the weak inversion (subthreshold)

region when VGS < Vt Source to drain current conduction is primarily due todiffusion of the carriers Ioff is when VGS = 0, is affected by the Vt, W, L, depletion

width beneath the channel area, channel/surface dopingprofiles, drain/source junction depths, gate oxide thickness,

VDD, and junction temperature


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Subthreshold leakage current

Thermal voltage:

Boltzmann constant:

Unit charge:

Subthreshold swing coefficient:

Permittivity

Permittivity

Thickness of the gate oxide

Thickness of the depletion layer


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Subtherehod leakage current Assuming the body effect is approximately linear for low

source-to-body voltages

Subthreshold leakage is exponentially dependent on thejunction temperature, VGS, VDS, and Vt Simplified BSIM (Berkeley short-channel insulated gate FET model)

Body effect coefficient DIBL coefficient


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Subthreshold leakage current

Frequently used equations


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Subthreshold leakage current Subthreshold leakage decreases exponentially as S decreases

Lowering the gate oxide thickness and/or doping concentration of thesubstrate due to increasing thickness of the depletion layer of the substrate

Lowing the junction temperature

A subthreshold slope of 60 mV/decade is a lower theoretical limit

at room temperature for bulk silicon MOSFET with fully depletedSOI devices

Typical values are ranging from 80 mV/decade to 100mV/decade


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Drain-induced barrier lowering (DIBL)

The depth of the junction depletion layer increases as thereverse bias voltage across the drain-to-body PN junctionincreases

Increased drain-to-body reverse bias voltage enhances the

short-channel effects and lowers Vt A significant portion of the subthreshold leakage current of

a DSM MOSFET can be due to DIBL at high reverse bias

voltage across the drain-to-body PN junction


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Oxide leakage tunneling When the gate of an NMOS (PMOS) device is positively (negatively) biased,

the electrons (holes) in the inverted channel can tunnel to the poly gate


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Two gate tunneling mechanisms Fowler-Nordheim tunneling

Through the oxide layer conduction band Observed at unusually high oxide voltage due to the electrons

tunneling into the conduction band of the gate insulator

Are not typically encountered during the normal operation of a CMOScircuit


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Two gate tunneling mechanisms Direct tunneling

Through the forbidden energy gap of the gate insulator Under normal bias conditions

With very thin oxide layer The electrons or holes in the inverted silicon surface tunnel directly

through the forbidden energy gap of the ultra-thin gate insulator Typically observed for tox less than about 4nm


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Two gate tunneling mechanisms Direct tunneling

Dependent on the voltage across the gate dielectric, the thickness ofthe dielectric, the tunneling barrier height, the effective mass of thecarriers, and the number of free carriers available for tunneling onthe MOS electrodes

Primary sources of the gate dielectric direct tunneling Electron tunneling from the conduction band (ECB) Electron tunneling from the valence band (EVB) Hole tunneling from the valence band (HVB)

k


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Direct tunneling of an NMOS transistor

L k P C


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Components of gate dielectrictunneling Igs0 and Igd0 are the leakage

current through the gate-to-source and gate-to-drainoverlap region

Igc is the gate-to-channeltunneling current duringoperation in the inversionregion

L k P C t


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Components of gate dielectrictunneling Gate to source/drain

overlap region (Igs0, Igd0) Controlled by VGD and VGS

Gate to channel (Igc

)=tosource (Igcs) + to drain(Igcd) Controlled by VoxVGS-VFB (flat-

band voltage) - sVpoly(voltage across the polysilicondepletion region)

Gate to body (Igb) Controlled by VGB

L k P CL k P C t


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Components of gate dielectric tunneling Transistor off (Vg=0)

Igd0 and Igs0 dominates Transistor on (Vg=1)

Igc (Igcs & Igcd) dominates Igb small compared to others

L k P C tL k P C t


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Maximum gate oxide leakage A transistor operates in the active region with the maximum

voltage difference across the gate-to-source and the gate-to-drain terminals

Maximum subthreshod leakage: cut-off transistor

L k P C tLeakage Power Components


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Semi-empirical gate oxide tunneling model Assuming Direct current density (A/cm2)

L k P C tLeakage Power Components


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Semi-empirical gate oxide tunneling model

3.1 eV for electrons tunneling from the conduction band 4.2 eV for electrons tunneling from the valence band 4.5 eV for holes tunneling from the balance band



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Hot carrier injection Short-channel transistors are more susceptible to the

injection of hot carriers (holes and electrons) into the oxide Theses charges are a reliability risk and are measurable as

gate and substrate currents Can occur in the off-state, but more typically occurs during

the transistor bias states in transition



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Junction band-to-band tunneling (BTBT)

VD=VDDEquilibrium



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Junction band-to-band tunneling (BTBT) Tunneling probability should involve the barrier height (E

G

)

and the barrier width (depletion layer)

High BTBT

Strong Halo, small depletion region and large electric field



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BT increases exponentially with the increase indrain/source-to-substrate bias



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Gate-induced drain leakage (GIDL) In the high electric field under the gate/drain overlap

region Carriers are generated from

Direct band-to-band tunneling Trap-assisted tunneling Thermal emission and tunneling

Thinner Tox and higher VDD cause a higher potential

between the gate and drain that enhances the electric fielddependent GIDL



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Channel punch-through When the drain and source depletion regions approach

each other and electrically touch deep in the channel A space-charge condition that allows the channel current to

exist deep in the sub-gate region Causing the gate to lose control of the sub-gate channel

region



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Summary of leakage power components

(DIBL)

On-state leakage

Off-state leakage

(VDD-V ) Design Space(VDD-Vt) Design Space


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(VDD Vt) Design Space(VDD Vt) Design Space

Two key transistor scaling schemes CE (Constant electric field) scaling

All the horizontal and vertical dimensions are scaled with the powersupply to maintain constant electric fields throughout the device

Standard scaling methodology in industry in a 30% reduction(1/S=0.7) of all dimensions per generation

Supply and threshold voltages are scaled down by the factor of 1/S Current, gate capacitances, and delay also scaled by 1/S Results in 50% improvement in frequency Improvement gradually degrades due to interconnect dominant delay

CV (Constant voltage) scaling Maintains a constant power supply Gradually scales the gate oxide thickness to slow down the growth of

fields in the oxide

(VDD-Vt) Design Space(VDD-Vt) Design Space


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CE scaling Switching energy scaled down by 1/S3

Dynamic power scaled down by 1/S2 Operating frequency scaled up by S Dynamic power for a constant die size is the same Number of switching elements scaled up by S2 Leakage power increases exponentially Total effective width of a device scaled up by S

Example Leakage power is 0.1% in 25um technology Leakage power is 25% in 0.1um technology

(VDD-Vt) Design Space(VDD-Vt) Design Space


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(VDD-Vt) Design Space Delay of a gate

Subthreshold leakage current increases exponentially as Vtdecreases

For a given process and VDD/Vt ratio, the energy efficient Vtpoint is significantly below the typical threshold levels of todaystechnology Excessive headroom for (VDD-Vt) scaling But lowering Vt results in bad noise margin, short-channel effect, and Vt

variation

Short-channel effect

Total Power ManagementTotal Power Management


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Total Power Managementota o e a age e t

Power minimization in both active and standby modes Dynamic power in active mode Subthreshold leakage power in standby mode

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