ISSN 1345-3041

Power Electronics Edition

VOL. 97/MAR. 2002

GCT

SGCT

GTO

IGBT

IGBT

IGBT

AS-IPM

DIP-IPMDIP-IPM

IPM

IPM

Vol. 97/March 2002 Mitsubishi Electric ADVANCE

A Quarterly Survey of New Products, Systems, and Technology

TECHNICAL REPORTSOverview ............................................................................................. 1by Katsuhiro Tsukamoto

1200V LPT Trench IGBTs .................................................................... 2by Katsumi Nakamura and Shigeru Kusunoki

Intelligent Power ICs: BiC-DMOS ....................................................... 5by Tomohide Terashima and Fumitoshi Yamamoto

Sixth Generation Low-Voltage MOSFETs withLow On-Resistance ............................................................................ 8by Atsushi Narazaki and Katsumi Uryuu

Transfer Mold-Type IPMs forDriving Small-Power Motors ............................................................. 11by Mitsutaka Iwasaki and Toru Iwagami

Advances in Integrated Intelligent Power Modules forHybrid Electrical Vehicles ................................................................. 14by Masakazu Fukada and Hirotoshi Maekawa

4.5kV HVIGBT Series Modules ......................................................... 18by Satoru Chikai and Koichi Mochizuki

R & D PROGRESS REPORTAnalysis and Simulation Technologies forHigh-Reliability Design of Power Modules ....................................... 21by Toshiyuki Kikunaga and Takeshi Ohi

TECHNICAL HIGHLIGHTNext-Generation IGBTs (CSTBTs) .................................................... 26by Hideki Takahashi and Yoshifumi Tomomatsu

NEW PRODUCTS AND TECHNOLOGIESFourth Generation IPM, “S-DASH Series” ........................................ 28

SiC Element Technology ................................................................... 28

CONTENTS

Mitsubishi Electric Advance is published online quarterly (in March, June, September,and December) by Mitsubishi ElectricCorporation.Copyright © 2002 by Mitsubishi ElectricCorporation; all rights reserved.Printed in Japan.

Cover StoryOur cover shows samples of MitsubishiElectric power devices that make significantcontributions to environmental protection.Main current devices are IGBT modules, whichare achieving ever lower switching lossesand higher switching speeds. Similar rapidgrowth is occurring among IPMs, bothindustrial-use ASIPMs and DIP-IPMs for homeappliances. Power capacities of GCTs arealso increasing.

Kiyoshi Ide

Haruki NakamuraKoji KuwaharaKeizo HamaKatsuto NakajimaMasao HatayaHiroshi MuramatsuMasaki YasufukuMasatoshi ArakiHiroaki KawachiHiroshi YamakiTakao YoshiharaOsamu MatsumotoKazuharu Nishitani

Tetsuji Yamaguchi

Keizo HamaCorporate Total Productivity Management& Environmental ProgramsMitsubishi Electric Corporation2-2-3 MarunouchiChiyoda-ku, Tokyo 100-8310, JapanFax 03-3218-2465

Yasuhiko KaseGlobal Strategic Planning Dept.Corporate Marketing GroupMitsubishi Electric Corporation2-2-3 MarunouchiChiyoda-ku, Tokyo 100-8310, JapanFax 03-3218-3455

Editor-in-Chief

Editorial Advisors

Vol. 97 Feature Articles Editor

Editorial Inquiries

Product Inquiries

Power Electronics Edition

· 1March 2002

TECHNICAL REPORTS

*Katsuhiro Tsukamoto is General Manager of the Power Device Division.

OverviewThe Outlook for Power Devices in the 21st Century

by Katsuhiro Tsukamoto*

As we face the needs of the 21st century, power electronics and its keycomponents–power devices–are becoming increasingly important in the revo-lutionary technological developments needed to move to a society based onecological recycling. This society will make the best use of energy and otherEarth resources and make full use of information technology. Progress in powerdevices has largely centered around insulated gate bipolar transistors (IGBTs)and their main use in controling inverters. The powers that can be controlledby these devices cover a very wide range, from those of a few Watts for switch-ing to Gigawatt-class DC power transmission.

The constant effort to reduce switching losses, improve switching speeds andincrease short-circuit ruggedness has resulted in IGBTs of which a fifth genera-tion is now in sight. The intelligent power module (IPM) is largely responsiblefor the extreme convenience and compact size of power devices by modularizingthe circuits needed to operate and protect IGBTs and diagnose their operation.As IPMs with designs optimized to meet market needs in home and industrialappliances, automobiles, locomotives, etc., are developed, the market promisesto expand still further.

In the future, there is good reason to believe that silicon will be replaced asthe semiconductor material of choice by silicon carbide, and accordingly a greatdeal of activity is being concentrated in the rapid development of power devicesbased on MOSFETs, etc., and their practical applications.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE2 ·

*Katsumi Nakamura and Shigeru Kusunoki are with ULSI Development Center.

by Katsumi Nakamura and Shigeru Kusunoki*

1200V LPT Trench IGBTs

Trench insulated gate bipolar transistors (IGBTs)that provide low on-state voltage and low switch-ing losses are already in practical use primarilyas 600V- and 1200V-class devices. A newly de-veloped light punch-through (LPT) trench IGBTadopts a novel device structure for further im-provements in cost performance and short-cir-cuit ruggedness and a reduction in gate capacitywhile maintaining the outstanding features ofconventional trench IGBTs. This article de-scribes the features and performance character-istics of this new device.

Device StructureThe schematic cross-sections in Fig. 1 compare(a) the usual punch-through (PT) structure, (b)conventional non-punch-through (NPT) struc-ture and (c) the novel LPT structure. Comparedwith the usual PT IGBT, the NPT type has amarkedly different collector structure and gen-erally has the following features:

1. The total substrate thickness (tsub) is thin.2. The collector is formed of only a shallow and

low concentration P layer without any N+

buffer layer.3. Since no N+ buffer layer is formed, the N− layer

is thick.4. Local lifetime control is not performed for the

N− layer.

Accordingly, one problem with the conven-tional NPT structure has been large losses.These include an increase in leakage current athigh temperature (398K), an increase in on-statevoltage and large switching loss due to greatertail current at turn-off.

The concept of the LPT trench IGBT is shownin Fig. 2 based on a comparison with a conven-tional NPT trench structure. This novel 1200VLPT trench IGBT effects the following devicestructural improvements to resolve the aboveproblems with the conventional NPT structure.

1. A low-concentration N layer is formed on thecollector side to suppress leakage current athigh temperature and tail current at turn-off.

2. An N layer that serves as a carrier stored (CS)layer[1] is formed directly below the P base forthe purpose of reducing the on-state voltageby using the carrier storage effect.

3. A wide cell pitch structure[2] with a large gatepitch has been adopted to improve short-cir-cuit ruggedness and to reduce the gate ca-pacity.

Fig. 1 Schematic cross section of various trenchIGBTs.

Con

vent

iona

l NP

T

WMOS : Small

VMOS : LargeVMOS : SmallJSAT : Large

Con. NPT LPTVCE

VD

VG VMOS ON

SC

WMOS : Large

VD : Large VD : Small

Fig. 2 Concept of wide cell pitch CSTBTs.

As shown in Fig. 2, the wide cell pitch struc-ture reduces the effective MOS gate width(WMOS), thereby suppressing the saturationcurrent (JSAT) and reducing the gate capacity. Inaddition, the provision of a damping trenchsuppresses oscillation under short-circuit

TECHNICAL REPORTS

· 3March 2002

conditions. As a result, high short-circuitruggedness and a small gate capacity areattained. The adoption of this CS structure lowersthe N- layer resistance caused by carrier storageeffect and reduces the on-state voltage.

Electrical Characteristics

OUTPUT CHARACTERISTIC AND BREAKDOWNVOLTAGE. The measured I-V characteristics at298K and 398K for trench IGBTs incorporatingthe device structures illustrated in Fig. 1 areshown in Fig. 3. Compared with the PT trenchIGBT, the I-V characteristic curves of theconventional NPT trench IGBT at 298K and 398Kcross at a lower current density, which is effec-tive in preventing device destruction due to ther-

Fig. 3 Measured I-V characteristics of varioustrench IGBTs.

mal runaway. In addition, the LPT trench IGBTachieves a lower on-state voltage than the con-ventional NPT trench IGBT on account of itsincreased carrier density due to the formationof the CS layer.

The junction leakage characteristics measuredat 398K for the three different device structuresare shown in Fig. 4. It is seen that the leakagecurrent (JC,Leakage) of the conventional NPT trenchIGBT is twice as great as that of the PT trenchIGBT. However, because of the shallow- and low-concentration N layer formed on the collector,the LPT trench IGBT achieves a leakage

Fig. 4 Measured junction leakage characteristicsof various trench IGBTs.

characteristic approaching that of the PTstructure device, enabling it to avoid thermalrunaway under high-temperature/high-voltageconditions.

SWITCHING CHARACTERISTIC. Fig. 5 shows theturn-off switching waveforms measured in half-bridge circuits of the three device structures inFig. 1 under an induction load condition(@VCC=600V, 398K). Compared with the PTtrench IGBT, the conventional NPT trench IGBT

Fig. 5 Turn-off switching waveforms of varioustrench IGBTs under inductive loadcondition (@VCC=600V, VGE±15V, RG=2Ω,398K).

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE4 ·

displays a larger tail current at turn-off. Incontrast, owing to its modified collectorstructure, the LPT trench IGBT attains a lowturn-off loss characteristic by suppressing thetail current at turn-off that occurs in theconventional NPT trench IGBT. The LPT trenchIGBT also shortens the switching delay time asa result of its reduced gate capacity achievedwith the wide cell pitch structure.

SHORT-CIRCUIT RUGGEDNESS. Fig. 6 shows theshort-circuit waveforms measured at VG = 19Vfor the 1200V LPT trench IGBT with a 15V gate

teristic equal to that of the conventional NPTtrench IGBT while at the same time maintain-ing high destruction ruggedness. As seen in thefigure, the trade-off characteristic of the LPTtrench IGBT has also been improved, thanks toits optimized substrate thickness and emitterresistance. As a result, it provides a device char-acteristic approaching that of the PT trenchIGBT.

Fig. 6 Short circuit waveforms of 1200V LPTtrench IGBT (@VCC=800V, RG=2Ω, 398K).

Owing to its novel device structure, the newlydeveloped 1200V LPT trench IGBT achieves a losscharacteristic equal to that of conventional trenchIGBTs, high destruction ruggedness on a par withplanar gate IGBTs, and reduced gate capacity. Asa result, this new device features high overallperformance, enabling the gate drive circuit tobe downsized and simplified without sacrificingthe low loss characteristic of trench IGBTs. Theconcept of this new device is expected to becomethe mainstream approach to the development oftrench IGBTs developing high voltage powerdevice over voltages of 1200V.

References1. H. Takahashi, H. Haraguchi, H. Hagino and T. Yamada, "Carrier

Stored Trench-Gate Bipolar Transistor (CSTBT) -A Novel PowerDevice for High Voltage Application-", Proc. ISPSD'96, pp349-352,1996

2. H. Nakamura, K. Nakamura, S. Kusunoki, H. Takahashi, Y.Tomomatsu and M. Harada, "Wide Cell Pitch 1200V NPT CSTBTswith Short Circuit Ruggedness", Proc. ISPSD'01, pp299-302, 2001

Fig. 7 Trade-off characteristics between on-statevoltage (VCE(sat)) and turn-off loss (EOFF) forvarious trench IGBTs.

driver. The PT trench IGBT and conventionalNPT trench IGBT require an overcurrent pro-tection circuit for clamping a short-circuit cur-rent to prevent destruction of the device.However, the newly developed LPT trench IGBTfeatures a wide cell pitch structure that reducesthe MOS saturation current, enabling the chipitself to achieve better short-circuit ruggednessthan conventional trench IGBTs. The measuredshort-circuit destruction energy (ESC) is ESC =8.15J/cm2.

TRADE-OFF CHARACTERISTICS. The trade-offcharacteristics between the turn-off loss(EOFF)and on-state voltage VCE(sat) for the varioustrench IGBTs in Fig. 1 are shown in Fig. 7. Thenew LPT trench IGBT achieves a loss charac-

TECHNICAL REPORTS

· 5March 2002

*Tomohide Terashima and Fumitoshi Yamamoto are with ULSI Development Center.

by Tomohide Terashima and Fumitoshi Yamamoto*

Intelligent Power ICs: BiC-DMOS

A 0.5µm BiC-DMOS device has been developedthat integrates 5~90V bipolar and MOS transis-tors and 30~90V power MOS transistors withoptimized on-resistance. This device processenables the development of ICs for a wide vari-ety of applications, typified by motor control usein automobiles and flat panel display drive cir-cuits.

BiC-DMOS refers to a process technology forintegrating CMOS, bipolar transistors andDMOS (NMOS) transistors characterized byhigh breakdown voltage and large current ca-pacity. Various companies have been workingon the development of this process for some twodecades now, as the technology offers analog/digital signal processing and power managementon a single chip. Process development effortshave been accelerating worldwide over the lastfew years under the combined effect of two fac-tors in particular. One is the use of fine-patterntechnology to attain lower resistance and higher

5V/12V NPN 30V NPN 5V/12V L-PNP 30V L-PNP 60V/90V L-PNP

5V PMOS 5V NMOS 12V PMOS 12V NMOS 30V/60V HV-NMOS

30V/60V HV-NMOS (full isolation type) 90 DMOS60V DMOS

30V/60V PMOS 30V/60V/90V Full isolation diode90V PMOS

Fig. 1 Schematic views of main devices on BiC-DMOS

performance for power devices at low cost. Theother is greater demand for smaller devices withlower power consumption for such typical ap-plications as mobile communications products.Mitsubishi Electric Corporation has developeda 90V, 0.5µm BiC-DMOS process that is the op-timal technology for meeting this demand.

The main devices integrated on a chip withthis process are shown schematically in Fig. 1.The use of an optimized structure for the burieddiffusion layer on the epitaxial substrate, reducedsurface field (RESURF) technology, finer doublediffused MOS (DMOS) cells, optimized offsetdiffusion and 5V/12V gate drive circuits fabri-cated from 14nm/35nm thick-gate oxide filmshas made it possible to integrate so many de-vices and a low on-resistance power NMOS overa wide range of voltages.

Power NMOSThe specific on-resistance of a power NMOSdevice must be optimized over a broad range of

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE6 ·

breakdown voltages in order to meet the require-ments for lower device costs and applicabilityto a wide range of applications. To accomplishthis, an HV-NMOS was adopted on the lowbreakdown voltage side and a DMOS on the highside. This facilitated the development of a de-vice with an overall outstanding specific on-re-sistance characteristic across a wide range ofvoltages.

DMOSAs the 90V DMOS in Fig. 1 illustrates, a P-wellfloating ring was added to the field plate above thelocalized oxidation of silicon (LOCOS) region. Thisworks to reduce the field concentration in theLOCOS region while restricting the device break-down voltage in the internal DMOS cell region,making it possible to achieve a 90V device. Im-provement of the specific on-resistance requires anarrower pitch and a shallower DMOS cell diffu-sion depth while maintaining the proper P-typebody concentration upon which Vth depends.Therefore, a method was adopted for forming theP-type body region by tilt-rotated implantation plushigh-energy vertical implantation. As shown inFig. 2, this resulted in an exceptionally shallowP-type body diffusion depth of less than 1µm andhigh-density DMOS cell packing (8.2µm pitch).At a breakdown voltage of 95V, specific on-re-sistance of 130mΩmm2 was measured in theDMOS cell region. That is an extremely goodon-resistance value for a discrete power deviceby itself.

Fig. 3 Cross sectional view of DMOS(fullisolation type)

Electron flow line

Source Drain Source Drain

2.0 4.0 0.0

4.0

6.0

6.0 2.0

Fig. 2 SCM micrograph of DMOS cell (unit: µm)

DMOS (full isolation type)With BiC-DMOS devices, inductive load driveis necessary as a power management measure.Consequently, it is necessary to prevent powerloss due to parasitic bipolar operation caused bythe back-electromotive force of L. A full isola-tion type DMOS was developed as a device thatis capable of minimizing such parasitic opera-

tion. A cross-sectional view of the device struc-ture and the electron flow line when back- elec-tromotive force is applied are shown in Fig. 3.

The structure is designed so that the drain istotally surrounded by the P well and P+ burieddiffusion layer that become the source potentialand by the N well and N+ buried diffusion layerformed on the outside. With this device struc-ture, if the drain potential is less than the sourcepotential, the carriers injected from the drainare electrons and holes are injected from thesource only in the direction of the drain elec-trode. In terms of the operating principle, there-fore, the phenomenon of hole current leaking tothe P− substrate does not occur. Measured re-sults show that the leakage current is suppressedto approximately 1/107 of the main current. Onthe other hand, with respect to the breakdownvoltage, the RESURF effect of the depletion layerthat extends above the P+ burier layer makes itpossible to keep the drain-source distance shorterthan that of conventional DMOS devices. As aresult, the specific on-resistance of the 80V de-vice is superior to that of ordinary DMOS de-vices.

HV-NMOSAnother method of fabricating a high breakdownvoltage NMOS device is the HV-MOS processwith the offset drain formed by the N- epitaxiallayer and the N well. One advantage stemmingfrom the gentle impurity profile of the pn junc-tion between the P well and the N well is that ahigh breakdown voltage device can be obtainedwhile maintaining a thin N− epitaxial layer.Another advantage is that the gate length canbe changed to match the circuit by varying thepositional relationship between the gate and theP well. Moreover, with the full isolation typeHV-NMOS to which a RESURF effect is impartedby adding a P+ buried layer to the lower region ofthe device, N well depletion is further promotedto yield a device with an even higher breakdown

TECHNICAL REPORTS

· 7March 2002

voltage. As shown in Fig. 4, the breakdown volt-age increases monotonically in both types ofdevice as X becomes longer. In addition, theRESURF effect increases with higher breakdownvoltages. Similar to DMOS devices, a breakdownvoltage improvement of approximately 20V isobtained.

Trade-Off with Specific On-ResistanceAs indicated in the foregoing discussion, DMOSand HV-NMOS are both available in a standardtype and a full isolation type, making a total offour types of device. In real-world applications,the device having the best specific on-resistancecharacteristic relative to the breakdown voltageof the application is naturally applied. The trade-off between the specific on-resistance and break-down voltage is shown in Fig. 5 for all of thedevices. The curve of each device plots thechange in this relationship accompanying achange in the breakdown voltage hold structure(e.g., source-drain distance, etc.). There is evi-dently an optimum breakdown voltage regionfor each device. As a result, as the power NMOSof the BiC-DMOS, the 90V, 80V, 60V and 40Vdevices adopt a DMOS, a full isolation typeDMOS, a full isolation type HV-NMOS and anHV-NMOS, respectively.

Fig. 4 Relation between the length X and the breakdown voltage

Length of X [µm]

Source SourceE E

Drain DrainSource Drain DrainSource

HV-NMOS HV-NMOS (full isolation type)

Bre

akdo

wn

volta

ge [V

]

0

0.05

0.1

0.15

0.2

0.25

0 20 40 60 80 100

Breakdown voltage [V]

Sp

eci

fic o

n-r

esi

sta

nce

[Ω

mm

2] HV-NMOS(E=1µm)

HV-NMOS(full isolation type, E=1µm)HV-NMOS(E=2µm)HV-NMOS(full isolation type, E=2µm)DMOSDMOS(full isolation type)

Fig. 5 Trade-off relation between specific on-resistance and breakdown voltage

The corporation’s new lineup of BiC-DMOS de-vices now makes it possible to provide a serieswith the best on-resistance characteristics tomatch the desired breakdown voltages of a widerange of specific applications.

ReferencesT. Terashima, F. Yamamoto and K. Hatasako, “Multi-voltage deviceintegration technique for 0.5µm BiCMOS & DMOS process”, Proc.ISPSD, pp. 331-334, 2000.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE8 ·

*Atsushi Narazaki is with ULSI Development Center and Katsumi Uryuu is with Fukuryo Semi-con EngineeringCorporation.

by Atsushi Narazaki and Katsumi Uryuu*

Sixth Generation Low-Voltage MOSFETswith Low On-Resistance

Mitsubishi Electric Corporation has developed thesixth generation of low-voltage trench gateMOSFETs designed for battery-control use inmobile communications devices. Featuring atrench gate structure with a 0.35µm design ruleand a 2.5V gate drive, these latest generationMOSFETs provide low on-resistance and highdestruction immunity. Compared with fifth-gen-eration MOSFETs using a 0.6µm design rule, thecell density has been increased and the on-resis-tance has been reduced by approximately 25%.

Power MOSFETs with low breakdown voltagehave traditionally been used in office-automa-tion equipment and in switching applicationssuch as DC/DC converters and switching powersupplies. In addition, as a result of the recentdiffusion of mobile communications devices,they have also found extensive application aspower-management circuits and as protectioncircuits for lithium-ion batteries. These applica-tions require a low-voltage drive circuit capableof being driven directly from the battery and re-duced on-resistance for minimizing loss whilecurrent flows.

A general approach to reducing on-resistanceis to improve the current capacity by increasingthe cell density through a reduction in the unitcell size. However, this approach requires theuse of complex fine-pattern technology, whichcan give rise to the problem of lower yields inthe manufacturing process. Another inherentproblem of MOSFET device structure is thatdevices are apt to be destroyed by the accumu-lated energy of the circuit’s own floating induc-tance during switching at high frequencies. Thenewly developed sixth generation powerMOSFETs with low breakdown voltage over-come these problems by incorporating tech-niques described below and utilize uniquefine-pattern technology to achieve high destruc-tion immunity with low on-resistance. The spe-cific on-resistance (Ron,sp) of the new devices is18mΩµm2 at VGS = 4V, which is approximately25% lower than that of the previous generation.

Reduction of On-ResistanceFor 20V-class power MOSFET chips, channel

resistance accounts for approximately 68% ofthe total resistance, excluding substrate resis-tance. In the case of low breakdown voltagepower MOSFETs, reducing channel resistanceis the most effective way of lowering chip resis-tance.

Fig. 1 shows the specific on-resistance (Ron,sp) oftwo generations of power MOSFETs as a functionof their normalized unit cell size. These resultswere obtained by using a certain test pattern. Table1 compares the cell densities of the sixth and fifthgenerations of power MOSFETs.

0

5

10

15

20

25

30

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Ron

,sp

[mΩ

mm

2 ] @

VG

S=

4V

6th gen.

5th gen.

Unit cell size (normalized)

Fig. 1 The relationships between the normalizedcell size and Ron,sp

Compared with the fifth-generation devices,the new sixth-generation MOSFETs have alarger specific channel width (i.e., total chan-nel area) for the same cell size. This was ac-complished by narrowing the trench width,making it possible to reduce channel resistanceand thereby also to lower the on-resistance ofthe chip. Moreover, reducing the unit cell sizeincreased the cell density for an improvementin current capacity and a reduction of on-resis-tance.

The design of the sixth-generation MOSFETsfeatures a trench width of 0.35µm, obtained withthe same level of fine-process technology as thatof the fifth-generation device design. This wasaccomplished by using a process technologyoriginally developed by the corporation to formthe trench pattern of the unit cell. As a result,

TECHNICAL REPORTS

· 9March 2002

compared with the fifth-generation devices, thecell size has been shrunk by 27% and the celldensity has been increased by 87% (Table 1).

Table 1 The Comparison of Cell Densities(relative value)

hcnerThtdiw

(µ )m

llectinUezis

latoTlennahc

htdiw

lleCytisned

.neght5 6.0 1 1 1

.neght6 53.0 37.0 14.1 78.1

Improvement of Destruction ImmunityReducing the cell size lowered the on-resistance,but it was necessary to resolve the decline inperformance and yield that occurred owing tothe insufficient pattern margin resulting fromthe finer pattern.

Fig. 2 shows a cross-sectional view of the cellstructure of a power MOSFET with a trench gatestructure. Reducing the cell size narrowed the

The narrower trench width adopted for thenewly developed sixth-generation MOSFETsmade it possible to secure the same overlapmargin between the trench gates and sourcecontact holes and also the same p+ contact sizeas the fifth-generation devices. That enabled theon-resistance to be reduced without degradingeither the gate yield or avalanche destructionimmunity. Moreover, as shown in Fig. 3, destruc-tion immunity was also improved at the sametime due to the avalanche current dispersioneffect of the higher cell density.

Mesa region

p+ n+p+ p+ n+ n+ n+

p

A AB

A: Tolerance of gate and contact holeB: p+ contact size

Trench gate

Trench gate

Fig. 2 The cross sectional view of the unit cell

silicon mesa region separated by the mesh-pat-tern trenches. However, taking into account thefollowing problems, it is desirable to design awide silicon mesa region:1. Gate defects caused by the insufficient over-

lap margin between the trench gates andsource contact holes (Fig. 2 (a))

2. Decline in avalanche destruction immunityduring unclamped inductive switching due tothe smaller p+ contact size (Fig. 2 (b))

Device CharacteristicsThe graph in Fig. 4 shows the dependence ofthe specific on-resistance (Ron,sp) on the gate volt-

Fig. 4 Dependence of Ron,sp on the gate voltage.

0

10

20

30

40

50

60

0 1 2 3 4 5

Ro

n,s

p [m

Ωm

m2]

Gate voltage [V]

6th gen.

5th gen.

Fig. 3 Dependence of the avalanche currentdensity on the cell density with the same p+contact size.

0

5

10

15

20

25

30

35

0 2 4 6 8 10

6th gen.

Cell density [Mcell/cm2]

5th gen.

Ava

lanc

he c

urre

nt d

ensi

ty J

DA [A

/mm

2 ]

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE10 ·

age. The major characteristics of the fifth- andsixth-generation MOSFETs are compared inTable 2. The newly developed sixth-generationMOSFETs display specific Ron,sp of 18 mΩµm2 atVGS = 4V. Compared with the fifth-generationdevices, on-resistance has been reduced by ap-proximately 25%. In addition, the new devicesalso provide avalanche destruction immunity ofJDA = 30A/mm2 at Tc = 150°C during unclampedinductive switching. This performance stemsfrom their amply large p+ contact size and highercell density achieved with the fine-pattern pro-cess providing a 0.35µm design rule.

The corporation’s newly developed sixth-genera-tion power MOSFETs can contribute to extend-ing the battery life of mobile devices and toenergy-saving systems by making the most oftheir features such as low on-resistance and highdestruction immunity. We plan to create a se-ries of devices with varying drive voltages andbreakdown voltages in order to meet a broadrange of market needs.

Table 2 Characteristics of 5th and 6th Generation MOSFETs

V ssd

I@( d )Am1.0=)V(

V ht

I@( d )Am1=)V(

R ps,no

V@( SG )V4=m( •Ω mm 2)

R ps,no

V@( SG )V5.2=m( •Ω mm 2)

J AD

T( C 051= O )Cmm/A( 2)

.neght5 03 8.0 52 83 82

.neght6 82 57.0 81 92 23

TECHNICAL REPORTS

· 11March 2002

*Mitsutaka Iwasaki and Toru Iwagami are with Power Device Division.

by Mitsutaka Iwasaki and Toru Iwagami*

Transfer Mold-Type IPMs for DrivingSmall-Power Motors

Mitsubishi Electric Corporation has been com-mercializing transfer mold-type dual-inline pack-age intelligent power modules (DIP-IPMs) for theinverter-driven home appliances market. We arenow developing a DIP-IPM series featuring im-proved functionality and reliability to meet morerigorous market requirements. This article de-scribes the design technology and major featuresof this series.

DIP-IPM Series and ApplicationsProducts in the DIP-IPM series come in two typesof packages—large or small—to match the cur-rent rating of the intended application. Large-package modules are used for air-conditionercompressors driven by power chips of the12~25A/600V class, and small-package modulesare used for driving washing machine motorsand refrigerator compressors that employ powerchips of the 3A/500V~10A/600V class. The ex-ternal appearances of the large- and small-pack-age DIP-IPMs are shown in Figs. 1 and 2,respectively.

Fig. 1 The larger transfer-mold IPM package.Mold size is 79 x 31 x 8mm.

Functions of DIP-IPM SeriesThe major functions and features of the DIP-IPM series are described below.

POWER CIRCUIT. The three-phase inverter con-sists of IGBTs and associated free-wheeling di-odes (FWDs).

CONTROL IC. This contains the drive circuit forthe P-side IGBTs, a high-voltage level-shift cir-cuit and a control supply under-voltage (UV) pro-tection circuit, although without any erroroutput. For the N-side IGBTs, it includes a drivecircuit and a short-circuit protection circuit (withFo). It also contains an N-side control supply UVprotection circuit (with Fo). An internal blockdiagram of a small-package DIP-IPM is shownin Fig. 3.

Key Technologies

POWER-DEVICE CHIP TECHNOLOGY. The DIP-IPM series achieves lower loss levels by adopt-ing fourth-generation planar structure IGBTs. Byapplying fine pattern technology to the IGBTsand vertically oriented lifetime control technol-ogy, collector-emitter saturation voltage hasbeen reduced by approximately 10% and the in-verter loss (three-phase sine-wave control) byapproximately 8% compared with the perfor-mance of third-generation planar structureIGBTs.

ASIC TECHNOLOGY. The DIP-IPMs represent anall-silicon solution, consisting only of IGBTs,FWDs and drive ICs. A frame configuration hasbeen adopted for the circuit wiring to reduce self-inductance and the generation of noise. This

Fig. 2 The smaller transfer-mold IPM package.Mold size is 49 x 30.5 x 5mm.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE12 ·

measure to prevent noise in the ICs has made itpossible to reduce the number of noise filtersused.

PACKAGE TECHNOLOGY. The establishment oftransfer mold technology has resulted in morecompact power modules. In addition, optimiza-tion of the frame structure and the use of a plas-tic material with excellent heat radiation andconduction properties have achieved a high heatradiation characteristic.

Features of DIP-IPM Series

LOWER NOISE. Lower noise levels are requiredof home appliances used indoors in order to re-duce the effect of any noise generated uponnearby electronic products. For the N series ofsmall-package DIP-IPMs, the collector-emittersaturation voltage of the IGBTs was reduced,making it possible to optimize the turn-on speed,which is one cause of noise, and to improve therecovery characteristic of the FWDs.

As a result, an in-house evaluation has con-firmed that the conducted emission level hasbeen reduced by more than 10dB in the 8~10MHzfrequency band, for example, compared with thatof previous devices. This improvement allows

Gate Drive

Protection Circuit

Input Signal Conditioning

Fault Logic & UV lock out

+VCC

LV-ASIC

UN

VN

WN

FO

CFO

VN1

UP

VP1 Gate Drive & UV lock out

Level Shift

Input Signal Condition

+VCC

HVIC

VUFB

VUFS

VP

VP1Gate Drive & UV lock out

Level Shift

Input Signal Condition

+VCC

HVIC

VVFB

VVFS

WP

VP1Gate Drive & UV lock out

Level Shift

Input Signal Condition

+VCC

HVIC

VWFB

VWFS

P

U

V

W

N VNC

CIN

Fig. 3 Internal block diagram of the smallertransfer-mold DIP-IPM

fewer noise-control components to be used, re-ducing system cost. Fig. 4 compares the turn-onwaveforms of a conventional device and a low-noise device.

Fig. 4 Turn-on waveforms

Irr=2.26A

trr=100ns

Ic:1A/div Vcc:100V/div

t:200ns/div

(a) Previous product (PS20351-G)

(b) Low-noise product (PS20351-N)

Irr=1.20A

trr=264ns

Ic:1A/divVcc:100V/div

t:200ns/div

REDUCTION OF ARM SHORT-THROUGH LOCKINGTIME. White goods installed indoors often havetheir carrier frequency set high on account ofnoise considerations. In this case, the arm short-through locking time when the motor is beingdriven can have a variety of undesirable effects,including a decline in motor output, an increasein torque pulsations and unstable operation. Byoptimizing the switching time and the delay timeof the control IC, the arm short-through lockingtime of the small-package DIP-IPMs has beenreduced to 1.5µs.

TECHNICAL REPORTS

· 13March 2002

ENHANCED FUNCTIONALITY. Previously, the ap-proaches taken for over-temperature (OT) pro-tection have included the attachment of athermistor to the heat-radiation fin of a DIP-IPMto detect the temperature. However, it has be-come necessary to incorporate an OT protec-tion function within DIP-IPMs. To meet thisrequirement, DIP-IPMs with a built-in OT pro-tection function have been added to the productlineup.

IPM with New Package ConstructionThere are strong demands for further reductionsin device size, especially in the small-powermotor market such as the segment for refrigera-tor and air-conditioner fan motors. In responseto that demand, we are developing a single-inlinepackage IPM (SIP-IPM)with vertical mounting.This SIP-IPM is shown in Fig. 5. Vertical mount-ing reduces the mounting area of a large-pack-age DIP-IPM by approximately 90% comparedwith that of previous devices. It also has the ad-vantage of facilitating easier peripheral wiringby separating the high- and low-voltage termi-nals on the two sides. The major functions andfeatures of the SIP-IPM are described below.

LOSS REDUCTION. Next-generation planar IGBTswith a 0.6µm design rule for reduced collector-emitter saturation voltage and low-VF FWDshave been adopted to achieve lower power losses.In addition, the supply current of the ICs hasbeen reduced by approximately 50% comparedwith existing devices.

HIGHER EFFICIENCY. An arm-short-through lock-ing time of 1µs has been attained.

Inverters are being applied in a wide range ofareas in the home appliances market today, ex-tending from 50W-class fan motors to 2.2kW-class or larger motors for the compressors ofair-conditioning units. Moreover, it is expectedthat the requirements for power modules willbecome increasingly rigorous due to regulationsgoverning energy savings and higher harmon-ics, recycling legislation and other factors.Against this backdrop, we intend to develop newpackages that revolutionize previous conceptsas well as low-loss power chips.

Reference1. M. Iwasaki, H. Kawafuji, T. Shinohara, K.H. Hussein, G. Majumdar,

J. Yoshioka, T. Roth: "Miniature Dual In-line Package IntelligentPower Module," PCIM '99

Fig. 5 The SIP-IPM

ENHANCED FUNCTIONALITY. In addition to thefeatures of the small-package DIP-IPMs, this newdevice incorporates arm short-through interlockprotection for improved reliability by preventingarm shorts due to spurious signal inputs, noiseor other causes.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE14 ·

Mitsubishi Electric intelligent power modules(IPMs) have been adopted in various generalpurpose and industrial applications all over theworld. For hybrid electric vehicle (HEV) applica-tions, the high temperature and other environ-mental conditions in the engine room subjectthe IPM to severe stress. HEVs are expected toaccount for 10% of the world’s total vehicle pro-duction by the year 2010 and, in addition to im-proved IPM electrical characteristics, durabilityand cost-performance are very important factorsfor the future. This article introduces a next-generation IPM system model with detection,protection and control features and a built-insmoothing capacitor. This embodies advancedintegration and miniaturization, forming an in-telligent integrated power-drive unit (IPU). Newtechnologies enable the IPU concept to achievehigh durability and reliability without using spe-cial high-temperature resistant materials.

Improving Power-Module Reliability for HEVs

POWER-MODULE HEAT CYCLE. Unlike pure elec-tric vehicles (EVs) which have no engine, the highengine-room temperatures of HEVs impose severeheat cycle (H/C) conditions on the power module.Therefore, the use of a copper compound base-platemetal material with a low linear expansion coeffi-cient is indispensable to satisfy the H/C require-ments. Such materials were successfully adoptedin the second generation HEV-IPM (CGA Series),but for the newly developed IPU (third generationHEV-IPM) the severe heat-cycle target specifica-tions (–40 ~125°C for at least 1,000 cycles) wereachieved through the use of a copper base platewith superior heat-transfer characteristics. Themajor improvements achieved are as follows.

CHIP LAYOUT OPTIMIZATION. As illustrated inFig. 1 (a), the conventional layout subjects thepower chip to high temperature rise with theslightest solder-crack at the corners (due to un-balanced heat dissipation), and this promotes fur-ther extension of the solder crack. Through theuse of electromagnetic thermal-stress simula-tion, the chip layout was optimized for minimalchip thermal stress on the solder between the

*Masakazu Fukada is with Power Device Division and Hirotoshi Maekawa is with Himeji Works.

by Masakazu Fukada and Hirotoshi Maekawa*

Advances in Integrated Intelligent PowerModules for Hybrid Electrical Vehicles

High temp. due to solder crack

(b) Improved layout(a) Conventional layout

Solder crack

Fig. 1 Chip layout optimization

ceramic plate and the base plate near the cor-ner as shown in Fig. 1 (b). Thus, the new layoutextends the time until the power chip experi-ences increased thermal stress even if a soldercrack occurs near the corner. As a result, dete-rioration in the junction-to-case thermal resis-tance was inhibited, meeting the H/C require-ments and improving thermal-stress endurance.

SOLDER CONTROL. Solder thickness is known toexert a powerful influence on the power module’sability to satisfy H/C requirements. As shown inFig. 2 (a), increased solder thickness improves theability to endure cracks but in conventional de-signs it proved difficult to secure reasonable anduniform solder thickness. This is evident from Fig.2 (b), which shows solder thickness distribution

99.99

50

0.10.1 1

1

110

Cum

ulat

ive

prob

abili

ty (

%)

Conventionalproduct

Cra

ck le

ngth

Crack length

IPU

Solderthickness

(a) Crack vs Solder thickness (b) Crack vs Process parasitic

Fig. 2 Effect of solder thickness on the cracklength

TECHNICAL REPORTS

· 15March 2002

(neglecting other process parasitic factors). Thismeans that the highest concentration of thermalstress occurs at the thinnest part of the solder layer,which in turn determines the H/C capability.

In the newly developed IPU, variations in thethickness of ceramic-plate solder were limited(ensuring the minimum necessary thickness) byhighly precise soldering, and enforced parasitic con-trol, thus extending the period before solder-crackoccurrence and establishing suitable productionconditions to satisfy the H/C requirements.

POWER CYCLE. Functional integration is ex-pected to increase in the future, and high-per-formance water cooling is being considered as apossible replacement for air-cooling in the imple-mentation of compact HEV-IPMs with large cur-rent capacity. In conventional industrial andgeneral-purpose IPM designs utilizing air-cool-ing fins, the ∆Tjmax values have been set ataround 30°C. On the other hand, for high ca-pacity HEV-IPMs with water-cooled fins, since∆Tjmax values of at least 50°C are expected, wire-bonding improvement becomes important in or-der to satisfy the power cycle (P/C) requirements.For the newly developed third-generation HEV-IPM (IPU), optimization of the chip-electrodemetallization and wire bonding is planned to pro-duce at least a two-fold P/C improvement overthe traditional third generation HEV-IPM (withDTj = 50°C). Further, with the help of optimizedwire bonding, an improvement in Tjmax of about10°C has been achieved as shown in Fig. 5 (a).The resulting P/C has a favorable increase of anorder of magnitude under rated current and ac-tual operating conditions, as shown in Fig. 5 (b).

148OC

123OC

152OC

147OC

ON-chip temp. sensor

(a) Before solder crack (b) After solder crack

Fig. 4 Chip-temperature distributions.

Previous

Improved

Max temp. : 110.1OC

Max temp. : 98.2OC

(a) Chip temp. reduction (b) Power-cycle improvement

40 50 100OC

1

2

10

Cycle count

ConventionalProduct

Fig. 5 Chip temp. reduction and power-cycleimprovement

The Power ChipSub-micron design rule was adopted for the IGBTchips exclusively developed for this IPU, thusallowing chip miniaturization without loweringthe saturation current level. Variations in the gate-threshold level were carefully addressed allowingsufficient margin for safe inverter operation.Further, due to the low power losses of the newchips under actual operating conditions, it waspossible to raise the current density to 200A/cm2.

Anti-noise measures were considered in theIPU switching characteristics leading to an op-timized performance level equivalent to that ofthe fourth-generation power chips. Ultrasoft-recovery free-wheeling diode chips were also de-veloped for the IPU.

ON-CHIP TEMPERATURE SENSOR. The IPU is fit-ted with an on-chip temperature sensor thatquickly reports the temperature and guaranteesfail-safe IPU operation even if a solder crackpropagates despite the optimized chip layout, aswill be evident from Fig. 4 (a) and Fig. 4 (b). Con-ventionally, various materials with low linearexpansion coefficients were used to satisfy highH/C requirements, but we have established tech-nology enabling the IPU to safely satisfy severeH/C requirements (–40~125°C for at least 1,000cycles) by utilizing a copper base plate.

Fig. 3 Heat-cycle and heat-shock test results.

*Note: The crack length is measured from the corner of the ceramic substrate.

Initialcondition

After 500cycles

After 1000cycles

Cycle count at -40~125OC

0 1000 2000 3000 4000

Cra

ck le

ngth

(m

m)

0

2

4

6

8

10

12

14

HC/HS-Test results<Corner crack>

HCHS

hherm OOCC

Thus, since the base-plate thermal conductiv-ity was improved by about 1.5 times when com-pared with traditional composite materials withlow linear expansions, it became possible to in-crease the current density even using the samechip.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE16 ·

Super-Fine Planar Gate IGBTsBecause of the severe conditions under which HEVIPMs operate, caution is necessary when design-ing the IGBT gate drive power supply with respectto control-board temperature increases. This isparticularly true for high capacity IPMs (rated atseveral hundred amperes) where the high gate ca-pacitance cannot be ignored. Further, to overcomeground-potential variations of each IGBT arm, sixisolated drive power supplies were integratedwithin the IPU; therefore in order to achieve alow IGBT gate capacitance, the super-fine planarIGBT gate structure was adopted. The low ON-voltage characteristics of the developed IGBT chipare shown in Fig. 6 and Table 1.

Table 1 IGBT Saturation Voltage Comparison

IGBTgeneration

Designrule

VCE(sat)@200A/cm2

Unit-cell size

3rd Planar 3µm 2.7V 1

4th Planar 1µm 2.0V 0.6

5th Planar Sub-µm 1.6V 0.5

4th Trench 1µm 1.5V 0.1

Fig. 6 IGBT ON-voltage characteristics

400K

300K

Y-axis : 50A/cm2 X-axis : 0.2V

0

0.05

0.1

0.15

0.2

0 500 1000 1500 2000Motor

Sensor

Smoothing capacitorIGBT/FWDi

Pro

tect

ive

& In

sula

ting

curr

ents

Pre

-driv

e un

it

Mot

or c

ontr

olle

r

Hig

h le

vel c

ontr

olle

r

Previous 600V/400A class HEV-IPMplus smoothing capacitor (2nd generation)

New type IPU with built-in smoothing capacitor (3rd generation)

Hea

t res

ista

nce

Rth

(j-c)

[ OC

/W ]

No. of heat cycles

Target no. of heat cycles

Target heat resistanceRth(j-c) =0.17OC/W

Conventional products (using low thermal expansion alloys) : Max.

New product (copper) : Max. : Min.

Fig. 7 Conventional HEV-IPM and IPU (prototype) at − 40~125°C on a 15 x 15mm IGBT chip

Future DevelopmentsThrough the improvements achieved in the IPUdevelopment, it is possible to meet the require-ments of 55kW motor applications (400A-class)utilizing only one chip instead of the conven-tional two-chip parallel standard module styleshown in Fig. 7. With conventional low linearexpansion coefficient composite materials it is dif-ficult to achieve high current densities becausethe lateral heat-transfer performance is poor andhigh temperatures are concentrated directly un-der the power chips. This is particularly true whenthe thermal-grease layer between the base plateand the cooling fin transforms into oil locallybeneath the power chips (due to the high tem-peratures there) and resulting in even worse ther-mal-transfer characteristics. Development of awater-cooled IPU module that dispenses with ther-mal grease is planned. Such a module will be ca-pable of supporting 360A rms rated output currentwith only one chip, as suggested by the simula-tion results shown in Fig. 8.

TECHNICAL REPORTS

· 17March 2002

References1. G. Majumdar, K.H. Hussein, K. Takanashi, M. Fukada, J.

Yamashita, H. Maekawa, M. Fuku, T. Yamane, and T. Kikunaga:High-Functionality Compact Intelligent Power Unit (IPU) for EV/HEVApplications, Proc. of ISPSD 2001.

2. J. Yamashita, C. Yoshida, C. Fujii, K. Takanashi, J. Moritani: The5th Generation Highly Rugged Planar IGBT Using Sub-micronProcess Technology, Proc. of ISPSD 2001.

100

150

200

250

300

350

400

450

500

1 10 100

∆Tjc = 50OC

PM400 CGA DC current limit

New IPU

PM400CGA060

IPU DC current limit

Carrier frequency (kHz)

Out

put c

urre

nt (

Arm

s)

Fig. 8 IPU simulated output current capability

This IPU development achieved high functionalintegration in a compact intelligent module forHEV applications. High reliability and high du-rability were achieved without using specialbase-plate materials thus greatly improving thecost-performance figures. The IPU represents atechnical initiative aiming at lower losses, com-pactness and effective high productivity. TheIPU seems sure to make a positive contributionto the future spread of hybrid-electric and elec-tric vehicles.

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE18 ·

*Satoru Chikai is with Power Device Division and Koichi Mochizuki is with Fukuryo Semi-con Engineering Corporation.

by Satoru Chikai and Koichi Mochizuki*

4.5kV HVIGBT Series Modules

Mitsubishi Electric Corporation has used an op-timized design for IGBT chips to develop 4.5kV(rated voltage) HVIGBT modules with a satura-tion voltage between the collector and emitterlower than the 3.3kV of the corporation’s previ-ous products. Three new products of this typeshave now been released, with rated currents of400A, 600A and 900A.

Development TargetsSemiconductor devices able to withstand in-creasingly high voltages are needed in order tomake power systems smaller and lighter in thefield of high-voltage applications. In response,the corporation will release the new products inthe same package types as the 2.5kV/3.3kVHVIGBT modules previously released. One goalin the project was to reduce the saturation volt-age between the collector and the emitter to avalue lower than the 4.0V saturation voltage inthe 3.3kV HVIGBT module (at the rated collec-tor current and a junction temperature ofTJ=125°C).

Description of the ModulesFig. 1 is a view of the 4.5kV HVIGBT module.On the left is a 400A/600A single HVIGBT mod-ule, measuring 38 × 140 × 130mm (H × W × L),the same as the 2.5kV/3.3kV, 800A product. Onthe right is the 900A single HVIGBT module,

Fig. 1 4.5kV HVIGBT modules

measuring 38 × 140 × 190mm, the same as the2.5kV/3.3kV, 1200A product.

When designing high-voltage IGBT chips, then− base layer thickness must be increased tosuppress the hot leakage current (to preventthermal runs); however, because this has anegative effect on the boundary between theswitching loss and the collector-emittersaturation voltage, the design used reduced thethickness of the n− base layer as far as possible.

Fig. 2 shows the dependencies of the collec-tor-emitter saturation voltage VCE(sat) and the hot

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

400 450 500 550 600 6500

5

10

15

20

25

30

VCE(sat)

I CE

S(h

ot) [

mA

/cm

2 ](V

CE

S=

4.5k

V, T

j=12

5o C)

VC

E(s

at) [

V]

(Jc=

50A

/cm

2 , T

j=12

5o C)

thermal run

ICES(hot)

tn-[µm]

Fig. 2 Dependence of VCE(sat) and ICES(hot) ontn- in the 4.5kV-IGBT chip

TECHNICAL REPORTS

· 19Month Year

leakage current ICES(hot) on the n− base layerthickness tn− in the conventional IGBT chipstructure. Although it is evident from Fig. 2 that a designwith Tn− = 500µm would cause VCE(sat) = 3.6V,fulfilling the original target value of 4.0V, theresults of other investigations made it clear thatICES(hot) could be reduced by optimizing thedensity in the p+ collector layer, so the develop-ment target was changed to VCE(sat) = 3.3V, anda thickness of tn− = 450µm was selected. Note

n+ buffer layer

p+ collector layer

p

n+

Emitter Gate

Collector

Local lifetime control area

n- base layer

Fig. 3 Cross-section of the high-voltage IGBT chip

In order to reduce ICES(hot) still further, investi-gations were also performed from the aspect oflifetime control, that is, looking at the depth ofproton irradiation from the p+ collector side.

Fig. 5 shows the dependence of the hot leak-age current ICES(hot) and the ratio between thecross-point current and the rated current Iztc/IC(rating), on the depth of proton penetration DH+from the p+ collector side. The depth for DH+ wasselected to be as shallow as possible while stillkeeping Iztc/IC(rating) to about 0.5. (Note that thecross-point current (Iztc ) is the intersection ofthe curve of VCE(sat) plotted against IC with the

that Fig. 3 shows the structure of the high-voltage IGBT chip.

After these investigations, further investiga-tions were performed to optimize the p+ collec-tor layer density in order to suppress ICES(hot). Fig.4 shows the dependence of the collector-emit-ter saturation voltage VCE(sat) and the hot leak-age current ICES(hot) on the density ratio γ of thedensities of the p+ collector layer and the n+

buffer layer (=CS(p+) /CS(n+)).Taking into consideration the balance of

VCE(sat) and ICES(hot) in the graph of Fig. 4, a γ ofbetween 10 and 15 was selected. The result wasthe ability to reduce ICES(hot) while avoiding anyincreases in VCE(sat).

Fig. 4 Dependence of VCE(sat) and ICES(hot) on γ in the4.5kV-IGBT chip

0.0

5.0

10.0

15.0

1.E-01 1.E+00 1.E+01 1.E+02 1.E+030.0

5.0

10.0

15.0

20.0

25.0

30.0

γ

VC

E(s

at) [V

](J

c=50

A/c

m2 ,

Tj=

125o C

)

I CE

S(h

ot) [m

A/c

m2 ]

(VC

ES=

4.5k

V, T

j=12

5o C)

ICES(hot)VCE(sat)

(Izt

c/I C

(rat

ing)

)

I CE

S(h

ot) [m

A]

(VC

ES=

4.5k

V, T

j=12

5o C)

ICES(hot)

Iztc/IC

0.01.02.03.04.05.06.07.08.09.0

10.0

0 10 20 30 40 50 600.00.10.20.30.40.50.60.70.80.91.0

DH+[µm]

Fig. 5 Dependence of ICES and Iztc/IC on DH+ in the4.5kV-IGBT chip

collector current IC at TJ =25°C and at TJ = 125°C.)The design described above fulfilled the ini-

tial target of VCE(sat) = 3.3V, while still control-ling ICES(hot). (Conditions: rated collector currentand junction temperature TJ = 125°C) was con-firmed in all three of the 4.5kV HVIGBT moduleproducts, and was thus selected.

Table 1 gives the absolute maximum ratingsand Table 2 the important product characteris-tics (specification parameters).

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE20 ·

Table 1 Maximum Ratings of the 4.5kV HVIGBT Module

lobmyS metI snoitidnoC H09-BH004MC H09-BH006MC H09-BH009MC tinU

V SEC

rettime-rotcelloCegatlov

V EG T,V0= j 52= OC 0054 0054 0054 V

V SEG

rettime-etaGegatlov

V EC T,V0= j 52= OC 02± 02± 02± V

IC tnerrucrotcelloCTC 52= OC 004 006 009 A

I MC esluP 008 0021 0081 A

IE tnerrucrettimETC 52= OC 004 006 009 A

I ME esluP 008 0021 0081 A

Tj

noitcnuJerutarepmet

--- 521+~04- 521+~04- 521+~04- OC

T gts

egarotSerutarepmet

--- 521+~04- 521+~04- 521+~04- OC

V osi egatlovnoitalosI

ottrapdegrahCsmr,etalpesab

,ladiosunis.nim1zH06CA

0006 0006 0006 V

---euqrotgnitnuoM

).xam~.nim(

lanimretniaM8M:wercs

00.31~76.6 00.31~76.6 00.31~76.6 m·N

:wercsgnitnuoM6M

00.6~48.2 00.6~48.2 00.6~48.2 m·N

lanimretyrailixuA4M:wercs

00.2~88.0 00.2~88.0 00.2~88.0 m·N

--- ).pyt(ssaM --- 5.1 5.1 2.2 gk

lobmyS metI snoitidnoC H09-BH004MC H09-BH006MC H09-BH009MC tinU

I SEC

ffotucrotcelloC).xam(tnerruc

V EC detaR:egatloV

Tj 52= OC 8 21 81Am

V EG V0: Tj 521= OC 04 06 09

V )ht(EG

rettime-etaGegatlovdlohserht

).pyt(

IC 00001/tnerruCdetaR:

V EG V01= , Tj 52= OC 0.6 0.6 0.6 V

I SEG

tnerrucegakaeletaG).xam( V EG V= SEG , V EC V0= 5.0 5.0 5.0 µA

V )tas(EC

-rotcelloCnoitarutasrettime

).pyt(egatlov

IC detaR:tnerruc

Tj 52= OC 0.3 0.3 0.3V

V EG V51= Tj 521= OC 3.3 3.3 3.3

V CE

-rettimE).pyt(egatlovrotcelloc

IE detaR:tnerruc

Tj 52= OC 0.4 0.4 0.4V

V EG V0= Tj 521= OC 6.3 6.3 6.3

R Q)c-j(ht ecnatsiserlamrehT).xam(

trapTBGI 320.0 510.0 010.0 W/k

R R)c-j(ht trapiDWF 540.0 030.0 020.0 W/k

R )f-c(ht

lamrehttcatnoC).pyt(ecnatsiser

deilppaesaergevitcudnoC 510.0 010.0 700.0 W/k

Table 2 Key Characteristics of the 4.5kV HVIGBT Module

Because the 4.5kV HVIGBT module was de-signed, as described above, to minimize the heatgenerated from the semiconductor chips, thisdesign promises to reduce power loss in systems

using these products. They will also contributeto energy conservation when applied to the con-verters and inverters for use at increasinglyhigher voltages in the future.

R & D P R O G R E S S R E P O R T

· 21March 2002

H igh precision analysis and simulationtechnologies for electrical and thermal phe-nomena within power semiconductor modulesare indispensable if the reliability of the designsof the modules is to be improved. This articlewill discuss three-dimensional electromagneticfield analysis technologies used in the design ofinterconnects within power modules, and willdiscuss electro-thermal simulation technologiesthat combine models of the electrical circuitsin power semiconductor chips with models ofthe thermal paths in the module structure.

Electromagnetic Field Analysis in the Designof Interconnect Lines in Power ModulesHigh-capacity power modules are made byconnecting a large number of power semi-conductor chips, for example, insulated gatebipolar transistors (IGBTs) and free wheelingdiodes (FWDs) in parallel within the module. Cur-rent imbalances between the respective chipsin these modules affect the durability of the mod-ule and the uniformity of the thermal distribu-tion within the chips. Because of this, currentbalancing is important in improving the perfor-mance and long-term reliability of the modules.

Mutual inductance in the three-dimensionalinterconnect systems such as found in electrodesin power modules creates complex linkages be-tween the various interconnect lines. Three-di-mensional electromagnetic field analysis is usefulin evaluating the current distributions and theimpedances in these parallel circuits. Theapplication of this analysis technology makes itpossible to design these interconnects based on aquantitative understanding of the electromagneticlinkages and of difference in impedances in theparallel circuits.

*Toshiyuki Kikunaga and Takeshi Ohi are with the Advanced Technology R&D Center.

by Toshiyuki Kikunaga andTakeshi Ohi*

Analysis andSimulationTechnologies forHigh-ReliabilityDesign of PowerModules

Methods of three-dimensional electromagneticfield analyses include the finite element method(FEM), the boundary element method (BEM), andthe finite difference time domain (FDTD)methods. Here we used the finite elementmethod (FEM), able to analyze precisely the elec-tromagnetic field, current distribution andimpedance for the complex geometries ofinterconnect conductors in power modules. Theanalysis results matched closely the experimen-tal results, confirming the usefulness of thismethod as a design tool.

Fig. 1 is an example of an analysis model for amodule. Copper blocks (1) to (4) in the Fig. wereused instead of the semiconductor chips in orderto isolate the effects of the interconnect im-pedances in the current distribution characteris-tics given. The collector terminal and emitterterminal at the top of the module were connectedto external parallel plate conductors. The currentdistribution characteristics were analyzed for thehigh frequency domain (300kHz) to evaluate thecircuit impedance, and for the low-frequencydomain (50Hz), where the circuit resistancedominates.

Fig. 1 Three-dimensional electromagneticanalysis model for power modules

External bus bar

Collector bus barEmitter bus bar

Collector terminal

Emitter terminal

Bent part

4

3

2

1

Fig. 2 shows the results of the analysis of thecurrent balance between chips. When thefrequency was 300kHz, the average electriccurrent on the chip (3) and (4) side was largerthan the average electric current on the chip (1)and (2) side. This is due to the difference in thecircuit inductance in the left- and right-bentparts of emitter and collector bus bars. In addi-tion, the differences in electric currents in chip(1) and chip (2) and in chip (3) and chip (4), aredue to differences in the electric current path.On the other hand, when the frequency was at50Hz, the differences in the circuit inductanceshad little effect on the distribution of the elec-tric current, and so only the effect of the differ-ences in the circuit resistance was evident.

R & D P R O G R E S S R E P O R T

Mitsubishi Electric ADVANCE22 ·

In order to evaluate the correctness of theanalysis results, the test module that was thebasis for creating the analytical model in Fig. 1was inserted into a half-bridge switching circuit,and the currents were measured for therespective chips. Fig. 3 compares the experimen-tal results with the analytical results. Thecurrent imbalance ratios at the current peak forthe various chips were compared with those ofthe analytical results at a high frequency of300kHz, because the frequency component ofthe rising electric current in the switching testwas about this frequency. The measured resultswith a DC power supply were compared withthe results of the analysis at a low frequency of50Hz. The experimental results closely matchedthe analytical ones at both at high and low fre-quencies.

0

20

40

60

80

100

120

140

Experiment Analysis Experiment Analysis

Cur

rent

Imba

lanc

e R

atio

(%

)

At low frequency At high frequency

1 4 1 4 1 4 1 4

Fig. 3 Comparison of experimental and analyticalresults for chip current imbalance

The current imbalance caused by unbalancedinductance in the interconnect lines may bemore pronounced in the higher-voltage larger-capacity modules, where collector and emitterterminals are further apart and there are morechips in parallel. Thus, this three-dimensional

electromagnetic field analysis technology is use-ful in the designs of such modules. This analy-sis technology was used in the design to optimizethe shapes of the electrodes in a high-voltageintelligent power module (IPM) with a rated volt-age of 3300V/1200A, and excellent current bal-ance results were obtained.

Simulation of Temperature Distribution onSemiconductor Chip SurfacesGenerally, wire bonding to the interconnect lineson the surface of the semiconductor chip is usedin power modules. In power modules, a numberof aluminum wires are bonded onto the powersemiconductor chips and the main current flowsthrough these wires. The bond between an alu-minum wire and the chip surface suffers heatstress through repeated temperature cycles. Thisheat stress eventually causes the bonded wireto separate from the surface, a phenomenon thatlimits the lifetime of power modules. Control oftemperature distribution on the chip is thereforevery important. Optimizing the disposition ofbonds on the chip can reduce temperatureswings and minimize the current concentrationdue to voltage drop along the surface pattern,thereby improving the lifetime and reliability ofthe power module. Here, electrothermalsimulation is presented as a method of evaluat-ing the temperature distribution on a chip; itcan provide a method of optimizing the disposi-tion of wire-bonding points so as to reduce chiptemperature gradients.

Fig. 4 shows the IGBT chip emitter surfaceand the electrical circuit model. The emitterelectrode is separated into stripes, and in thisFig., aluminum wires are bonded near the middleof each stripe. The electrical circuit model forthe IGBT is a circuit model for a single stripe. Inorder to take into consideration the thermaldistribution on the chip and the electricalresistance of the aluminum electrode on theemitter surface, which contribute to thecollector current distribution of the chip, eachstripe is divided into multiple IGBT segments(IGBT0 to IGBTn) and electrical resistances (RA11to RA1n) corresponding to the resistances of thealuminum electrodes between the respectiveIGBT emitters were inserted. In addition, theparameters for each IGBT segment circuitmodels are selected so that the IGBT chips thatare represented by the electrical circuit modelsmatch the actual measured values for the V-Icharacteristics of the actual chips.

Fig. 5 shows both the simulation results (thesolid line) and the measurement results (markedby circles, inverted triangles, etc.) of the volt-age distributions of the various collector currents

0

50

100

150

200

250

50Hz 300kHz

Chi

p C

urre

nt (

A)

12

34

1

2

3

4

Fig. 2 Analysis of current balance characteristics

R & D P R O G R E S S R E P O R T

· 23March 2002

referenced to the potential of the aluminum wirebond on the emitter electrode surface of one ofthe stripes. The simulation results matched themeasurements quite well, indicating that theelectrical circuit models described above wereappropriate.

Fig. 6 shows the layered structure of the crosssection of a module, including the IGBT chips,the ceramic substrate, the baseplate, and theheat sink, doing so as a network of thermal pathsin the electrothermal simulation. The variousthermal resistances are calculated from the ther-mal conductivities and thicknesses of the ma-terials in the structure. This example is a modelof the thermal paths for a single chip, and theinfluence of the adjacent chips is not consid-ered in this model.

The V-I characteristics of the various IGBTsegments in the electrical circuit model of Fig. 6,were modeled, taking the temperature depend-encies into account. The voltages and currentsfor the IGBT segments obtained from the staticcharacteristics of the IGBT chip were used tocalculate the thermal generation in each of theIGBT segments, the temperature fluctuations werecalculated from the thermal path model, and thecalculations iterated until the temperature in each

Fig. 4 Emitter surface of IGBT chip and electrical circuit model separating the IGBT chip into small IGBTsegments

Fig. 5 Simulation results and measurements ofpotential distribution on the emittersurface.

of the IGBT segments reached convergence. Thelosses in the aluminum electrodes on the emittersurfaces and the thermal interference between theIGBT segments within each stripe were taken intoconsideration, and the cross-wise thermalconduction in the solder parts and grease part in

R & D P R O G R E S S R E P O R T

Mitsubishi Electric ADVANCE24 ·

the layered structure of the module cross-sectionwas ignored. The heat sink was held at 23ºC,matching the experimental conditions.

Fig. 7 and Fig. 8 show the results of simula-tions and experiments on the IGBT chip surfacetemperature distribution when wire bonds havebeen made to the center parts and peripheralparts of the emitter electrodes (where the blackshort lines show the positions of the aluminumwire bonds). The collector current was 105A.Power was applied until the temperature

Fig.6 Electrothermal network of an IGBT chip.

distribution on the surface of the chip reached asteady state, and then an infrared camera wasused to measure the temperature distribution.It was found that the temperature distributionswere nearly identical.

Fig. 9 is the result of a simulation of the tem-perature distribution, ignoring the temperaturedependencies of the electrical characteristicsand the electrical resistances of the IGBT chipemitter surface. In other words, the simulationof the thermal distribution assumes uniform

Fig. 7 Results of electrothermal simulation of the temperature distribution in an IGBT chip

Aluminum wires bonded at the central area of emitter.

Aluminum wires bonded at the periphery of emitter.

(oC)130

120

110

100

90

80

R & D P R O G R E S S R E P O R T

· 25March 2002

losses throughout the chip. The total loss withinthe chip is essentially the same as the loss shownin Fig. 7, where a wire bond is made at the cen-ter of the emitter electrode. The thermal distri-bution in Fig. 9 is clearly different from thedistributions in Figs. 7 and 8. Consequently, itis evident that the assumption of uniform lossesis inadequate for accurate evaluations of thetemperature distributions on the surface of thechip, and that electrothermal simulations areessential.

(oC)130

120

110

100

90

80

Fig. 9 Results of an electrothermal simulation ofthe temperature distribution of an IGBTchip, assuming uniform power dissipation

Fig. 8 The comparison of measured temperature distributions in IGBT chips with different wire bondpositions

Aluminum wires are bonded at the central area of emitter.

Aluminum wires are bondedat the periphery of emitter.

(oC)130

120

110

100

90

80

At present, work is proceeding on dynamic simu-lations of power semiconductor circuits in con-junction with electromagnetic field modeling,and on simulations of transient electro-thermalphenomenon.

References1. Takeshi Ohi, Takeshi Horiguchi, Tatsuya Okuda, Toshiyuki

Kikunaga and Hideo Matsumoto. "Analysis and Measurement ofChip Current Imbalances Caused by the Structure of Bus Bars inan IGBT Module." IEEE IAS Annual Meeting, 1999, pp. 1775-1779.

TECHNICAL HIGHLIGHT

Mitsubishi Electric ADVANCE26 ·

*Hideki Takahashi is with ULSI Development Center and Yoshifumi Tomomatsu is with Fukuryo Semi-con EngineeringCorporation.

by Hideki Takahashi and Yoshifumi Tomomatsu*

Next-Generation IGBTs (CSTBTs)

Mitsubishi Electric Corpo-ration has announced a carrierstored trench gate bipolar transis-tor (CSTBT) that has reduced on-state voltages by significantimprovements to the carrierdistribution in trench IGBTs(TIGBTs). The corporation hasdeveloped this CSTBT as its next-generation IGBT. It has demon-strated all of the performanceadvances hoped for in next-gen-eration power chips. This articledescribes the results of evalua-tions of the CSTBT prototypes.

Ever since IGBT modules (usedprimarily in invertors) were firstmarketed, new generations ofIGBT chips have been producedevery few years, steadily improv-ing the performance frontier forthe trade-off between switchingloss and saturation voltage (anindicator of loss). Until the thirdgeneration, improvements re-sulted from technologies to min-iaturize cells, but a revolutionarynew structure was introduced inthe fourth generation; in additionto further miniaturizing the cells,a trench gate structure was in-troduced, resulting in a substan-tial leap in performance.[1]

In response to the needs of amarket constantly searching forimprovements in energy con-servation, the corporation an-nounced its CSTBT in 1996[2],and commenced research anddevelopment in both structuresand manufacturing processes forthese next-generation powerchip products.[3]

The Structure and Benefits ofCSTBTsFig. 1 shows a three-dimensional

Emitter electrode

Polysilicon gate

Gate oxide layer

Emitter layer

P+diffusion layer

Carrier storage N layer

Collector electrodeCollector electrode

N+ buffer layer

N- layer

Barrier metal layer

P+ substrate

P base layer

Fig. 1 Three·dimensional view of CSTBT

cross section of a CSTBT. Struc-turally, the CSTBT is character-ized by the addition of an n-typelayer with a relatively high im-purity density between the p-typebase layer and the n- layer in thetrench IGBT (TIGBT). When theconventional TIGBT is in an ONstate, holes are injected into then- layer from the p+ layer on thecollector side, and these holespass to the emitter side. On theother hand, in the CSTBT, theimpurity density of the n layerthat forms a junction with the pbase is greater than for the n-layer, so the junction voltage atthe junction between the p baseand the n layer is greater thanthe junction voltage at the junc-tion between the p base and then- layer in the TIGBT. This highjunction voltage becomes a bar-rier preventing the holes thatwere injected into the n- layerfrom the p+ layer from passinginto the emitter side. In other

words, the n layer causes theholes to accumulate within theelement by restricting themovement of the holes to the pbase layer. This charge accumu-lation function causes the ONvoltage for the CSTBT to be sub-stantially lower than for theTIGBT.

Performance of the 600-voltCSTBTTo confirm the superior proper-ties of the CSTBT, a CSTBT chipwas prototyped and evaluatedusing the same wafers and thesame 1µm design rule as for theTIGBT. The CSTBT had a re-verse bias voltage of 600V and acurrent-carrying capacity of 50A.Because, in the CSTBT, the pri-mary junctions were formedwith an n-type layer with a rela-tively high impurity density inorder to store the carriers, it wasmore difficult to ensure reverse-bias voltage capabilities than it

TECHNICAL HIGHLIGHT

TECHNICAL HIGHLIGHT

· 27March 2002

was for the TIGBT; however, thereverse bias voltage was success-fully secured by optimizing boththe thickness and the impuritydensity of the carrier storagelayer, and by using high precisioncontrol. Fig. 2 shows the wave-forms for the current and the volt-age when the CSTBT is OFF. Asis clear from the figure, theCSTBT rated at 600V has a 720Vreverse bias capability, so thereis adequate margin above therated voltage.

Fig. 3 shows the output char-acteristics of a CSTBT exposedto electron-beam radiation inthe same way as a TIGBT is ex-posed (in order to control theminority carrier lifetime). Theoutput characteristics are shownat both 25°C and 125°C. The

I C (

A)@

VG

E=

15V

VCE (V)

0

10

20

30

40

50

60

70

80

0 0.5 1 1.5

Tj=25OC

Tj=125OC

Fig. 3 I·V characteristics ofCSTBT.

saturation voltage at the ratedcurrent (VCE(sat)) was 1.22V atTJ=25°C, and 1.15V at TJ=125°C,0.3 to 0.4V less than the conven-tional TIGBT.

Fig. 4 is a curve showing thetradeoffs between the switch-offloss, ESW(off) and the VCE(sat). Asdescribed above, the CSTBT issuperior to the TIBGT in termsof its ON characteristics, andthus the CSTBT tradeoff curveis about 0.4V better than theTIGBT for the same switchingloss. When it comes to thistradeoff relationship betweenthe VCE(sat) and the ESW(off) theCSTBT is superior to any otherMOS gate device so far an-nounced for applications at600V.

4.0

3.5

3.0

2.5

2.0

1.5

1.0ES

W (o

ff) (m

J) (I

C=5

0A, V

CC

=300

V, 1

25OC

)

1.0 1.2 1.4 1.6 1.8 2.0

VCE(sat) V (IC=50A, VGE=15V, 125OC)

TIGBT

CSTBT

0.4V

Fig. 4 Trade·off relationshipbetween on·state voltagedrop and turn·off loss forboth CSTBT and TIGBT.

It was also confirmed that thereverse bias safe operation area(RBSOA) could perform turn-offswitching at 500A (a currentdensity of 2100A/cm2), tentimes the rated current.

As described above, the CSTBTproposed by Mitsubishi Electric ispositioned as the next-generationpower chip after the TIGBT, and,as a step in this direction, thecorporation has developed tech-nologies for insuring reversebiasing capabilities and has estab-lished design technologies for car-rier storage layers, validating theperformance of the 600V/50ACSTBT. As a result, the CSTBThas been able to improve the

tradeoff relationship betweenthe VCE(sat) and the EOFF by about0.4V over the conventionalTIGBTs without incurring anyloss in performance in terms ofthe switching time or reversebias voltage. This tradeoff rela-tionship is the best of any MOSgate element announced to datefor 600V or above.

Development efforts are under-way on high-performance mod-ule products using the CSTBTchips in order to contribute tothe market looking for improvedenergy conservation.

References1. M. Harada, T. Minato, H. Takahashi, H.

Nishihara, K. Inoue, I. Takata, “600VTrench IGBT in Comparison with PlanerIGBT - An Evaluation of the Limit of IGBTPerformance”, Proceedings of ISPSD 94,pp416-pp416, 1994

2. H. Takahashi, H. Haruguchi, H. Hagino, T.Yamada, “Carrier stored Trench-gateBipolar Transistor - Bipolar Transistor - ANovel Power Device for High voltageapplication” Proceedings of ISPSD 96,pp349-pp352, 1996

3. H. Takahashi, S. Aono, E. Yoshida, J.Moritani, S. Hine, “600V CSTBT having ultralow ON - State Voltage” Proceedings ofISPSD 01, pp445-pp448, 2001

0.00

0.50

1.00

1.50

0 200 400 600 800

I CE

S(m

A)

VCES (V)

Fig. 2 Breakdown voltage ofCSTBT.

Mitsubishi Electric ADVANCE28 ·

NEW PRODUCTS AND TECHNOLOGIES

SiC Element Technology

Power devices are used broadly inhome electronics, industrial appli-cations, electric trains, and electricpower generation and transmission.These power devices contain swit-ching elements equipped withcontrol electrodes (typically insulat-ed gate bipolar transistors), alongwith diodes to provide the rectifyingfunction.

When compared to silicon (Si),silicon carbide (SiC) devices havesuperior physical characteristics,suggesting that SiC will be the nextgeneration of semiconductor ma-terials to transcend the physicallimitations of silicon in power de-vices requiring higher blocking vol-tages and lower ON resistances. Asa result SiC has increasinglybecome the focus of research.

Of greatest interest to devicemanufacturers is that SiC has tentimes the dielectric breakdownelectric field strength of silicon,meaning that the high-resistancelayer need only be one-tenth thethickness to maintain the same highvoltages. Because it is also possibleto increase the substrate electrondensity by a factor of 100, the use ofSiC can reduce the ON resistanceto one-thousandth that of silicon in

comparable unipolar structures. Inother words, in a class of deviceswith blocking voltages of the orderof 1kV or higher, the use of SiCenables unipolar structures such asfield-effect transistors and Schottkybarrier diodes, where conventio-nally bipolar structures have beenrequired to reduce the ON resis-tance when silicon was used. Thisis expected to resolve the problemsthat occur in bipolar structureswhen performing high-speed swit-ching.

In diode technology, a Schottkybarrier-type diode rated at 600Vand several amperes was releasedat the beginning of 2001. In fieldsrequiring higher blocking voltages(several kVs), there have beenannouncements relating to recov-ery performance and reliabilitytesting results in bipolar structures,indicating that the release of suchstructures may be imminent.

The most intense research, how-ever, is in the field of voltage-drivingfield-effect transistors (FETs) asswitching elements. Aggressiveefforts are currently being made tobring to market structures wherein,for example, the resistance of thechannel layer is reduced and thislayer is fabricated somewhat more

deeply buried in the substrate be-low the surface itself.

Remarkable progess has beenmade in crystal technologies since1993, due to burgeoning demandfor light-emitting diodes, and ad-vanced firms in the United Stateshave now been joined by substratemanufacturers in Europe and Ja-pan. The issues faced in bringingthis technology to market includereducing defects and increasingdiameters. The density of defectsknown as “micropipes,” with diam-eters of several µm, has reachedthe 1.1 defect/cm2 level, and dis-cussion has started regarding theeffects of, for example, dislocationdefects. As for increased diameters,some crystal manufacturers haveindicated that they will begin salesof four-inch substrates in the nextfew years.

Mitsubishi Electric Corporationbegan technical research in thisMITI-designated critical region inJune 1994, and since 1998 it hasparticipated in the MITI super-lowloss electrical element develop-ment process, engaging in re-search into and development ofMOSFETs.

Fourth Generation IPM, “S-DASH Series”

Given the improvement in perfor-mance of power modules, the mar-ket now has a new set of demandsapplying to power modules in addi-tion to its conventional demands forhigh performance, compact size,and low losses. These new de-mands include greater ease of useand environmental friendliness. Tomeet these needs, Mitsubishi Elec-tric Corporation has released itsfourth-generation intelligent powermodule (IPM) the “S-DASH Series,”in order to reduce the saturationvoltage and reduce electromagnet-ic noise.

ApplicationsApplicationsApplicationsApplicationsApplicationsIdeal for compact inverter servosand other motor-controlled equip-ment for AC 220V and AC 440Vapplications, and for compact in-verters in UPS equipment and otherpower-supply equipment.

FeaturesFeaturesFeaturesFeaturesFeatures1. Reduced losses through the

use of the fourth-generation1-µm design rule planar insulat-ed gate bipolar-transistor chip.

The S-DASH intelligent power module

2. Improved recovery characteris-tics and reduced electromag-netic noise through the use of anewly designed free-wheelingdiode.

3. Maintains package compatibilitywith the corporation’s second-and third-generation intelligentpower modules.

4. Built-in fault-signaling outputs forover-current, short circuits, over-temperature and drive supplyunder-voltage.

57.344.4

5541.5

34.4

16

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13.3

60

0

25

50

75

100

125

150 IGBT DC IGBT SW FWD

2nd PM200DHA060 3rd PM200CSA060 4th PM200CSD060

[600V/200A]

Loss

(W)

A comparison of the losses in each generationof the Mitsubishi Electric Corporation intelligentpower modules.

MITSUBISHI ELECTRIC CORPORATIONHEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100-8310, FAX 03-3218-3455