power distribution status and challengeson the on-chip power distribution system as it erodes the dc...

Georgia Institute of TechnologyGreetings from

Power DistributionPower DistributionStatus and ChallengesStatus and Challenges

Presented by Madhavan SwaminathanPackaging Research CenterSchool of Electrical and Computer Engineering

Georgia Institute of TechnologyGeorgia Institute of Technology

Oct 24, 2004

Acknowledgement

• Prof. Joungho Kim – KAIST, S. Korea

• Dr. Istvan Novak – SUN, USA

• Mr. James Libous – IBM, USA

Oct 24, 2004

Outline• Introduction

• Digital Systems- On-Chip- Package and Board- New Technologies

• Modeling- On-Chip- Package and Board

• Mixed Signal Systems- RF and Digital Integration

• Summary

Oct 24, 2004

Microprocessor Projections

8 GHz

425 W

70 GB/s

μP 140 mm2

Oct 24, 2004

Device Leakage Power Density IncreasingDevice Leakage Power Density Increasing

- In the past, CMOS active power was main concern with power delivery

- As CMOS scales to below 90nm, process related device leakage current contributes a significant passive power component

-Leakage current can be reduced by using high-k dielectric materials as replacement for silicon dioxide as the gate dielectric

-Passive power puts a further strain on the on-chip power distribution system as it erodes the dc IR drop noise budget and compounds the EM problem

Courtesy: J. Libous, IBM

Oct 24, 2004

Importance of Power DistributionImportance of Power Distribution

Reliability Wall

50MHzIncrease

In FMAX

+/- 100mV

+/- 50mV

1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80

825

785

745

705

665

625

FMAX (MHz)

VCC (V)Courtesy: Intel

Oct 24, 2004

RFRFDieDie DigitalDigital

Processor DieProcessor Die

Excitation of Edge RadiationExcitation of Edge Radiation

GNDGND

PWRPWR

MemoryMemoryDieDie

SensorSensorDieDieDecoupling

Capacitor

Wire Bond

Signal Line

SSN Generation SSN Coupling to

Signal/Clock ViaSSN Coupling to Power/Ground Via

P/G Via

Signal Via

Power Distribution in Heterogeneous Systems – A Major Challenge

Oct 24, 2004

Power Distribution Power Distribution –– DC to Daylight ProblemDC to Daylight Problem

VRM Decoupling Capacitors Planes Orthogonal Wiring

Board and Package Power Distribution Chip Power Distribution

Low to Medium Frequency High FrequencyVRM Decoupling Capacitors Planes Orthogonal Wiring


VRM Decoupling Capacitors Planes Orthogonal Wiring


Low to Medium Frequency High Frequency

Package & Board Chip

Chip – Package Co-design of Power Distribution is a necessity for Future Systems

Oct 24, 2004

Digital Systems

Oct 24, 2004

Power Supply SensitivityPower Supply Sensitivity

- Scaling reduces Vdd headroom (operating on a steeper part of the delay versus Vdd curve)

-As Vdd values drop and power densities increase, IR drop becomes more of an issue

-Instantaneous voltage drop and spatial variation must be analyzed and controlled

-On-chip decoupling capacitors used as local power source to handle instantaneous current demands

-Dcaps must be placed where needed and requires a thorough understanding of chip current demand prior to chip physical design


Oct 24, 2004

Legacy I/O Voltages Must Be Distributed Legacy I/O Voltages Must Be Distributed along with Core Voltagesalong with Core Voltages


Oct 24, 2004

Voltage Islands and Power DomainsVoltage Islands and Power Domains• Design approach to manage theactive and passive power problem

• Voltage Islands - Areas on chip supplied through separate, dedicated power feed

• Power Domains – Areas within an island fed by same Vdd source but independently controlled via intra-island header switches

• Distribution Challenges – dcapisolation, transients due to activation & deactivation of islands, multiple supplies

• Simple Concepts….. Complex methodology and design tools Courtesy: J. Libous, IBM

Oct 24, 2004

Target Impedance of Power Distribution NetworkTarget Impedance of Power Distribution Network

Frequency [log]

P/G

Impe

danc

e

kHz MHz GHz

TargetImpedance

THz

IdealImpedance

InductiveImpedance

Skin effect, dielectric, radiation

loss

A concept becoming popular in the packaging community

Courtesy: J. Kim, KAIST

Oct 24, 2004

BSM

V1

G1

V2

G2

VRM

Capacitors CapacitorsCapacitors

25um40um

1 mm

200um

200um

200um

25um

25um

25um

25um

100 mm x 100 mm

er=4

10 mm x 10mm

40 mm x 40mm

TSM

V1

R1

G1

V2

R2

G2

25um

25um

25um

25um

25um

25um

25um

40um

40um

40um

400um

40um

40um

Package on Board

Oct 24, 2004

Impedance seen by Chip on Package With Capacitors

No onchip Cap

Onchip=150nF

Package and Board Decoupling Chip Decoupling

Chip – Package Resonance

Modeling Results

Oct 24, 2004

DCDC--DC ConvertersDC ConvertersState of the ArtState of the Art

SI parameters:Zout, Zin, Vout/Vin

Output ripple

Loop stability

Large-signal response

12x10mm 15A POL converter.Source: www.power-one.com

POL converter in PCCourtesy: I. Novak. SUN

Oct 24, 2004

Potential LowPotential Low--Frequency Problem:Frequency Problem:Peaky/Changing Output ImpedancePeaky/Changing Output ImpedanceImpedance magnitude [ohm]

1.E-03

1.E-02

1.E-01

1.E+00

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency [Hz]

OFF4V_0A4V_1A4V_2A4V_3A4V_5A4V_7A54V_10A

Courtesy: I. Novak. SUN

Oct 24, 2004

Bypass CapacitorsBypass CapacitorsState of the Art, Bulk CapacitorsState of the Art, Bulk Capacitors

Impedance magnitude, inductance [ohm, H]

1.E-3

1.E-2

1.E-1

1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Frequency [Hz]0.0E+0

5.0E-10

1.0E-9

1.5E-9

2.0E-9

2.5E-9

3.0E-9

MagnitudeInductance

A

A

BB

Face-down, low-inductance, low-ESR, low-profile, D-size polymer tantalum capacitor (curves A on the impedance plot)

“Overview of Some Options to Create Low-Q Controlled-ESR Bypass Capacitors,”Proceedings of EPEP2004, October 25-27, 2004, Portland, OR


Oct 24, 2004

Bypass CapacitorsBypass CapacitorsState of the Art, TwoState of the Art, Two--terminal Ceramic Capacitorsterminal Ceramic Capacitors

Impedance magnitude and phase [ohm, deg]

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07Frequency [Hz]

-1.0E+02

-8.0E+01

-6.0E+01

-4.0E+01

-2.0E+01

0.0E+00

2.0E+01

4.0E+01

6.0E+01

8.0E+01

1.0E+02

1210 100uF

Impedance magnitude and phase [ohm, deg]

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+06 1.E+07 1.E+08 1.E+09 1.E+10Frequency [Hz]

-1.5E+02

-1.0E+02

-5.0E+01

0.0E+00

5.0E+01

1.0E+02

0508 4.7uFreverse geometry


Oct 24, 2004

Bypass CapacitorsBypass CapacitorsMultiMulti--terminal Ceramic and Film Capacitorsterminal Ceramic and Film Capacitors

Impadance magnitude of 603-10mm film cap. [ohm]

1.E-3

1.E-2

1.E-1

1.E+0

1.E+6 1.E+7 1.E+8Frequency [Hz]

603-size capacitor

Via array0.0047 ohm

603 pads, mid position0.016 ohm

603 pads, end position

0.048 ohm

BGA capacitor

Film capacitor

Source: AVX Corporation: Low Inductance Capacitors, S-LICC5M396-C brochure

10-mm long film capacitor

60 mils

0603 pads

Multi-terminal capacitor


Oct 24, 2004

New Technologies

Oct 24, 2004

Plane Resonance and Edge RadiationPlane Resonance and Edge Radiation

I

I

Ground Plane

Power Plane

P/G Plane Edge RadiationI

Return Current

MS

-V+


Oct 24, 2004

1478

3rd

Frequency [GHz]

500 MHz CLK

0 0.5 1 1.5 2 2.5 3

Frequency [GHz]

- 70

- 30

-10

- 50

Edg

e R

adia

tion

(SA

-PP

G) [

dBm

] 0

10

100

1

P/G

Plane Im

pedance [Ω]

0.1

0.01

TV2 SA Measurement TV2 P/G Plane Impedance

(7cm,7cm)TV2

14cm

14cm

Short Via

PCB Edge Radiation excited by 500 MHz ClockPCB Edge Radiation excited by 500 MHz Clock


Oct 24, 2004

Thin Film Embedded CapacitorThin Film Embedded Capacitor

A

B

C

D

E

VehicleCode Dielectric Thickness Dielectric Constant (DK)

50 μm

25 μm

12 μm

10 μm

10 μm

4.6

4.6

4.6

16

25

Capacitance/cm2

81.46 pF

162.91 pF

339.40 pF

1416.64 pF

2213.50 pF

Total Capacitance(5cm x 5cm with 2 pairs)

4.07 nF

8.15 nF

16.97 nF

70.83 nF

110.68 nF

“A” with x50 “A” with x100

25μm50μm 12μm

“A” with x500 “B” with x500 “C” with x500


Oct 24, 2004

-50

-40

-30

-20

-10

0

10

20

30

1 10 100 1000 3000Frequency [MHz]

Pow

er/G

roun

d Im

peda

nce

[dB

ohm

]With Thin Film Embedded Capacitor(Thickness : 12μm, DK : 4.6) – “C”

With Thin Film Embedded Capacitor(Thickness : 10μm, DK : 25) – “E”

16 x 100nF Discrete Capacitors

Significant Improvement over GHzWith Thin Film Embedded CapacitorSignificant Improvement over GHz

With Thin Film Embedded Capacitor

Improvement at low frequency rangewith High-DK Embedded Material

Improvement at low frequency rangewith High-DK Embedded Material

Significant improvement over GHz with Thin Film Embedded Capacitor (Very low ESL of Embedded Capacitor)More improvement at low frequency range with high-DK embedded capacitor (More Capacitance)

TM02/20 ModeResonance (5cm x 5cm)

TM02/20 ModeResonance (5cm x 5cm)

Measured PDN Impedance CurveMeasured PDN Impedance Curve


Oct 24, 2004

Low ESL Embedded Decoupling Capacitors in the Package

Low CTE, High Modulus Composite Substrate

Digital ICs (µP, Memory)

10 GHz Microprocessor (Bare die) 50um balls on100um pitchL=27pH perVdd – Gnd ball

Total Bump Inductance6 fH

NegligibleLoop inductancefor charge transfer

Dielectricthickness of0.1um leads to pH spreading inductance

Embedded decoupling1 – 3μF/cm2

charge reservoir

Zero signaldelaypenalty

Oct 24, 2004

Technical Innovation in Embedded Capacitors

High frequency measurement

Low temperature hydrothermal synthesis of BaTiO3

• <100°C Process Temperature• 100-500nm Thick Film• Capacitance Density > 1µF/cm2 Achieved• Loss Tangent ~ 0.05

Sol-gel synthesis of BaTiO3 , SrTiO3• High Temperature Process (~600°C)• Rapid Thermal Process Developed (3 min)• 200-900nm Films Processed on Ni/Ti Foils• Lamination Process for Integration• Capacitance Density ~500nF/cm2

• Loss Tangent ~0.005

100

150

200

250

300

350

400

450

2 3 4 6 7

Frequency (GHz)

Die

lect

ric C

onst

ant

0

0.1

0.2

0.3

Loss

Tan

gent

Oct 24, 2004

Modeling

Oct 24, 2004

On-chip Power Distribution Network

Cross section of ASIC power distribution*

3D view of on-chip power grid

Oct 24, 2004

Finite Difference Time Domain Method

First order Debye equivalent circuit

11

1

11

1

/1

,/1

GCjCjCjGY

RLjLjLjRZ

extdc

extdc

ϖϖϖ

ϖϖϖ

+++=

+++=

hox

hsi

SiO2

Si

Gnd

Cross section of on-chip power grid

Oct 24, 2004

Simulation of Power Supply Noise using FDTD

Chip composed of blocks with different power densities (unit=mw/mm2)

22,645,380Element (RLGC)5,661,354Nodes6 (M1…M6)Metal Layers6×6Size(mm×mm)

Oct 24, 2004

Modeling of Core Power Distribution in Package and Board

Original Plane Grid

* Port 1: ( 0.677, 3.7268)Port 2: ( 1.058, 1.3138)Port 3: ( 3.471, 1.6948)Port 4: ( 3.09, 4.1078) cmUnit cell size: 0.093 X 0.093 cm

∇ DecapsΔ Ferrite + C25

Courtesy: Kodak

Oct 24, 2004

Modeling of Multi-layered Planesin Packages and Boards using Transmission Matrix Method

Horizontal plane pair approximated usingdiscretized RLGC parameters

Planes connected using via inductanceMatrix Reduction

Oct 24, 2004

Bare Board for 1V8 Plane

Z11 Blue: MeasurementRed: T Matrix

Model to Hardware Correlation

Oct 24, 2004

Modeling of I/O Power DistributionModeling of I/O Power Distribution

Differential Transmission Lines (50 Ω)

0.3 V (Vterm)

50 Ω

50 Ω

2. RLGC Models or Macro-models of Transmission Lines

PDN Macro-model

Port 1 Gnd

Port 2

Gnd

Port 3

Gnd

0.6 V (Vdd)

1. Macro-models ofPDN

50 ΩDifferential

Driver

3. Non-linearMacro-modelsOf drivers

Oct 24, 2004

Coupled Signal and Power Distribution Simulation using TMM

Oct 24, 2004

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-8

1

1.5

2

0 0.2 0.4 0.6 0.8 1 1.2 1.41

1.5

2

2

Time (s)

V(p

ort1

)V

(por

t2)

Test Case: IBM HSTL_B 350MHz Driver

0

1000

2000

3000

4000

5000

6000

7000

8000

0 5 10 15 20 25 30 35Number of drivers switching

Sim

ulat

ion

time

in (s

ec)

Blue HSTL model

Red Macro-model

g1

g4g2 g5

g3

1 pFV_ne(t) V_fe(t)transmission line

10 drivers

port1

port2 port4 (Vdd = 1.5 V)

port3

port5

GND

VDD

Time

100XSpeed-up

Oct 24, 2004

GndCore Vdd

GndI/O Vdd

GndI/O Vdd

GndI/O Vdd

Gnd

Interconnects

Interconnects

Interconnects

Interconnects

178 I/O Decoupling Capacitor

195 Core Decoupling Capacitor

750 MHzMicroprocessor

SRAM

Connector

274 Interconnects

128 Interconnects

x

y

Example from SUN[Top View] [Cross Section]

Oct 24, 2004

0 200 400 600 800 1000 1200 1400 1600 1800 2000-70

-60

-50

-40

-30

-20

-10

0

Noi

se P

ower

(dB

)

Frequency (MHz)

125 MHz (Connector Bus)250 MHz (SRAM Bus)

750 MHz 1500 MHz

0 5 10 15 20 25 30 35 40 45 501.47

1.48

1.49

1.5

1.51

1.52

1.53

Volts

Noi

se

Time (nSec)

4 nSec (250 MHz)

8 nSec (125 MHz)

I/O PDS NoiseI/O PDS Noise

I/O switching noise is caused by the return currentflowing on the I/O vdd/gnd planes.

[Frequency Domain] [Time Domain]

Blue: Measurements, Red: ModelingSimulation Time: 124 Seconds with 20 ps time step

Oct 24, 2004

Heterogeneous Systems

Oct 24, 2004

Heterogeneous Integration

Multiband antenna

Multiband filter Multiband Balun

Multiband Differential

Downconverter

ADC +

Processor

f1 f2

Digital-Analog Coupling

Multiple Signal Generator

Multiband Low Noise Amplifier

CHIP DOMAINPACKAGE DOMAIN

Example: 802.11 a/b/g; WiMaX; UWB; Handset

Oct 24, 2004

GND layer

VDD layer

RF circuit

Digital circuit

Load

Dielectric layer (εr = 4.4)

Current EM wave

EM coupling

Electromagnetic Coupling in Mixed-Signal Systems

Oct 24, 2004

Split planes & Ferrite bead- ferrite bead is placed between split planes for DC connection

- require a single power supply

- still poor isolation at high frequencies due to EM coupling through a gap

Power-plane Segmentation- conducting neck is placed

between split planes for DCconnection

- requires a single power supply- poor isolation except narrow frequency range

⇒ Better isolation technique is needed for mixed-signal system applications

Isolation Methods Available

Oct 24, 2004

EBG Structure

Two-dimensional (2-D) square lattice with each element consisting of

a metal patch with two connecting metal branches.

Metal branches introduce additional inductance and capacitance is

mainly formed by metal patches and corresponding parts of other plane.

⇒ Distributed LC network.

Schematic of Novel EBG Structure in GND plane

Unit Cell of Novel EBG Structure

Oct 24, 2004

300MHz FPGA with 2.13GHz LNA

Substrate Coupling

Noise Isolation using Electronic Bandgap Structures

Patterned Ground Plane

EBG Response

Oct 24, 2004

-90

-85

-80

-75

-70

-65

2.09E+09 2.10E+09 2.10E+09 2.10E+09 2.10E+09 2.10E+09 2.11E+09

7th harmonic noise peak at LNA output for mixed-signal system without AI-EBG structure

7th harmonic noise peak at LNA output for mixed-signal system with AI-EBG structure

Frequency (Hz)

Pow

er (d

Bm

)

Noise Reduction with EBG Structure

Oct 24, 2004

Digital SystemsIncreasing chip power and technology scaling placing challenges on IR drop, EM, leakage and active power

Voltage islands on-chip and multiple I/O voltages making the design complex

Decoupling capacitors on package running out of steam

Embedding decoupling increasing design complexity

ModelingOn-chip Modeling: Still very complex due to the feature sizes,

irregular layouts and uncertainty in the return current path

Chip – Package Interface: Integrated modeling of chip and

package still doesn’t exist

Estimation of current signature a big challenge

Modeling of isolation in mixed signal systems with low noise floors

Heterogeneous IntegrationAchieving -85dBm over broad frequency a challenge

3D Integration is making it worse

Summary

Oct 24, 2004

ReferenceM. Swaminathan, J. Kim, I. Novak and J. Libous,

“Power Distribution Networks for System on a Package: StatusAnd Challenges”, IEEE Trans. On Advanced Packaging,

pp. 286 – 300, Vol. 27, No. 2, May 2004

power distribution status and challengeson the on-chip power distribution system as it erodes the dc...

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