poster winter 2011-2012 barak shaashua barak straussman supervisor: idan shmuel
DESCRIPTION
Hardware Connection 250MS/s 1.5MB/s 2.1GS/s 16MB memory Tabor – wx2182 as DAC NI FlexRio FPGA 7965R as TX NI 5761 Digitizer + NI FlexRio FPGA 7965R as RXTRANSCRIPT
![Page 1: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/1.jpg)
Digital Transmitter Implementation
PosterWinter 2011-2012
Barak Shaashua Barak StraussmanSupervisor: Idan Shmuel
![Page 2: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/2.jpg)
Project GoalsImplementation of a transmitter with
Labview on FPGA.
Project modulation types: 4 DQAM 8 DPSK
![Page 3: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/3.jpg)
Hardware Connection
250MS/s
1.5MB/s
2.1GS/s16MB memory
Tabor – wx2182 as DACNI FlexRio FPGA
7965R as TX
NI 5761 Digitizer + NI FlexRio
FPGA 7965R as RX
![Page 4: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/4.jpg)
System ProblemsThe bottleneck of the system is the speed of the DAC (Tabor
wx2182) connection through the GPIB cable. Therefore, the system complexity was reduced by simulating The TX
on the HOST. (Even though the TX works on the FPGA).
Streaming is not supported by the DAC through the GPIB. Transmission is done in packets as big as the memory of the DAC.
The DAC doesn’t transmit both channels synchronically (without trigger). As a result, the two channels are combined on the HOST and
delivered to the DAC as one channel.
![Page 5: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/5.jpg)
Data RatesTransmitter boundary: DAC max sample rate:
2.1GS/sec. In this rate carrier wave frequency: 1.05GHz.
Receiver boundary: The ADC (NI5761) - max sample rate: 250MS/sec --> BW = 125MHz.
Data boundary: Limited by the DAC memory size - 16M samples.
![Page 6: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/6.jpg)
I
Q
Serial /
Parallel
Constellation Mapping
DAC
ISIFilte
r
Up Convert
er
Channel Coder
Source Coder
CombinerSin(wt)
+π/2
I
Q
Transmitter Block Diagram
DAC
![Page 7: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/7.jpg)
Symbol Decision
Constellation
Mapping
Channel Decoder
RF
Parallel /
Serial
Receiver Block-Diagram
ADCSin(wt)
+π/2I
Q
I
Q +(
Source)
Timing &
Carrier Recover
yLPF
LPF
![Page 8: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/8.jpg)
Implementation example - Transmitter Symbol Mapping
***
![Page 9: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/9.jpg)
Implementation example - Acquisition FPGA
![Page 10: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/10.jpg)
Transmission ParametersWe worked with Carrier frequency: 50MHz + 10
samples per period --> DAC operates in 500MS/sec.
Symbol = 1 period of the carrier.Data rate: DQPSK - 2 bit/symbol - 100Mbit/sec.
D8PSK - 3 bit/symbol - 150Mbit/sec.With 16M DAC memory - Data transition per
transmission: 400KB (DQPSK) / 600KB (D8PSK).
![Page 11: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/11.jpg)
Results25MHz transmission --> BER=0(One symbol error at the edge, not dependent on transmission length)
50MHz transmission --> BER=0
80MHz transmission --> BER=1/3No alignment between samples and carried
periods.Over sampling too low.
![Page 12: Poster Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel](https://reader033.vdocuments.us/reader033/viewer/2022050813/5a4d1b627f8b9ab0599ae2e9/html5/thumbnails/12.jpg)
SummeryIn this project we acquired a lot of knowledge about
communication and modulation.
The project involved the integration of variety of systems and work environments.
Future improvements:
Labview - We found it hard to debug FPGA VI.
Tabor - In our project setting, wx2182 wasn’t suitable.