polytech’montpellier – mea4 m2 eea – systèmes

Analog IC design - 2014/2015 - Chapter 2 19/09/2014

1

Polytech’Montpellier – MEA4 M2 EEA – Systèmes Microélectroniques

Analog IC Design Building a DC Small-Signal Model of a CMOS Analog Circuit:

a comprehensive guide

Pascal Nouet – 2014/2015 - [email protected] http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html

Objective / Content

•  Demystify the building of a low-frequency (dc) small-signal model for your CMOS analog circuit

•  A step by step straightforward approach •  Pre-requisites

–  Good practice of solving electrical circuits (Node and Mesh laws)

–  Large- and small-signal models for MOST in strong-inversion

•  Content –  A comprehensive guide –  A set of exercises

•  Next step –  Solving small-signal circuits


2

From Norton (Current) Source to MOS transistor

Practical Current Source ≠ Current supply

I

V

I

V

r 0

I

V

I

V

r 0

I

V

I

V

Ideal Current supply

(e.g. "idc" within simulator)

Norton Source (Model)

MOST Drain-Source Current

Norton

Outline

•  Large- and small-signal models for MOST in strong-inversion –  Overview of theoretical background –  Experiments

•  DC Small-Signal Model of a CMOS Analog Circuit –  Straightforward approach

•  Exercises –  A basic Voltage source : determine Vdd dependency –  A basic Current source : output resistance and Vdd

dependency –  A basic amplifier : voltage gain


3

Large-signal model of the MOS transistor: saturation current, Idsat

Idsat =µnCox

2WLVeff2 = 3.6µA

NMOS W=10µm and L=2µm

Vds (V)

Ids

Vgs = 0.6 V

Veff = 100mV

Value of µ.Cox ?

Small-signal model of the MOS transistor: transconductance, gm

Vds (V)

Ids

Vgs = 0.6 V

Vgs = 0.61 V

Vgs = 0.59 V

0.6 µA

0.6 µA

∂Idsat∂Vgs

= µCoxWLVeff = gm ⇒ gm =

2 ⋅ IdsatVeff

= 2µCoxWLIdsat


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Small-signal model of the MOS transistor: output resistance, rds

Idsat =µnCox

2WLVeff2 = 3.6µA

Vds (V)

Ids

Vgs = 0.6 V

Veff = 100mV

Value of λ for this NMOST ?

ΔIds / ΔVds = 0,145 µA/V

Ids = Idsat 1+λn Vds-Veff( )!" #$

λn =

ΔIdsΔVds

Idsat≅ 4.10−2 V −1

Pre-requisite summary

•  N-type MOS transistor SSM in strong inversion –  3 independent terminals

–  2-terminal (diode-like)

•  P-type MOS transistor SSM in strong inversion –  3 independent terminals

–  2-terminal (diode-like)

T2

g2, d2

s2

T3

g3

s3

d3

T4

s4

g4, d4

s1

gm1vgs1 rds1

d1 g1

d3

gm3vgs3 rds3

s3

g3

s2

g2, d2

1gm2

s4

g4, d4

1gm4

T1

d1

s1

g1


5

Outline





Characterization of a diode-connected NMOS Transistor

Vds & Vgs (V)

Ids (A)

2eff

oxndsat V

LW

2CµI =

Vgs


6


Veff (V) 0.5 1 2 Idsat (µA) 171 647 2380 δIds/δVgs (mA/V)

0.709 1.28 2.23

µnCox (A/V2) 1.42e-4 1.28e-4 1.12e-4

µnCox (A/V2) 1.37e-4 1.29e-4 1.19e-4

eff

moxneffoxn

gs

dsm

VLWg

CµVLW

CµVI

g =⇒=∂

∂=

µn.Cox = 112 to 142 µA/V2

!"

#$%

&= 22 effdsatoxn VLWICµ

0

5

10

15

20

25

30

35

40

45µnCox (µA/V2)


Average : 126 µA/V2

Standard-deviation : 24 µA/V2


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Characterization of rds (PMOS)

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.00E-‐01 1.00E+00 1.00E+01 1.00E+02 1.00E+03

r ds(ΩΩ)

Idsat (µA)

Characterization of rds (PMOS)

y = 1.31E+07x-‐9.52E-‐01R² = 9.91E-‐01

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.00E-‐03 1.00E-‐02 1.00E-‐01 1.00E+00 1.00E+01 1.00E+02 1.00E+03

r ds(ΩΩ)

Idsat/L (A/m)

)()(10.31,1 7

AImLrds

dsat

×≅⇒


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y = 0.5026x1.0419R² = 0.9915

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10

r ds(mod

èle, ΩΩ)

rds (mesure, ΩΩ)

rds modèle vs. rds mesure

Characterization of λλp

•  Standard deviation

•  Fixed length design (e.g. L=10µm)

è

)(76

)()(1,13 1

µmLmV

AIµmLr p

dsatds

−

=⇒×

≅ λ

1310.65,7 −−= Vpλ

( )[ ]02

avec 1Φ+−

=−+=effdseff

dseffdsdsatds VVL

kVVII λλa

r

qNεε0

ds2k =

%25±

Lab #1: Technology characterization

•  BSIM3v3 models –  /soft/DKits/Ams/HK_410/spectre/c35/cmos53.scs –  Identification of various models –  Analysis of ‘modn’ and ‘modp’ –  Find VTH0 (V), U0 (cm2/Vs) and Tox (m) –  Calculation of µ.Cox

•  Calculation of µ.Cox and rds by MOST characterization

TOX = ?

εε0 = 8.85e-12 F/m

εεr = 3.9

Cox =ε0εrTOX


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Outline





The step-by-step method

•  All the steps below will be easier and you will reduce the risk of error if you keep the initial circuit topography for your small-signal model…

•  Step 1: identify your input i.e. the magnitude that will vary during your small-signal analysis and keep-it unaltered anytime

•  Step 2: replace I and V sources by their small-signal model •  Step 3: replace each transistors by their small-signal model

including labels for g, d, s •  Step 4: add electrical connections as in your initial circuit •  Step 5: identify all required vgs and eliminate related voltage-

controlled current sources when vgs=0 •  Step 6: identify your output variable, eventually rearrange your

circuit and solve the obtained circuit


10

Outline





Your first Analog Design

T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Cf T16

Vout1 T11

Vout

T12

T1 Ids11

Voltage Reference


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Homework & Lab

•  Homework –  Design T1 to T4 for Vbias=0.6V and IT1=10µA –  Derive a small-signal model of the circuit to

determine sensitivity to Vdd of both Vbias and IT1 –  Compute these sensitivities

•  Lab –  Verify the biasing point using a ‘Operating Point’

simulation (both Vbias and IT1) –  Verify the sensitivity to Vdd of the biasing point using

a ‘DC’ simulation (both Vbias and IT1)

Outline






12


T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Cf T16

Vout1 T11

Vout

T12

T1 Ids11

Voltage Reference

Current Source

Homework & Lab

•  Homework –  Design T13 for IT13=50µA –  Derive a small-signal model of the circuit to

determine rout –  Compute rout

•  Lab –  Verify the biasing point using a ‘Operating Point’

simulation (IT13) –  Verify the output resistance using a ‘DC’ simulation


13

Outline






T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Cf T16

Vout1 T11

Vout

T12

T1 Ids11

Voltage Reference

Current Source

Common source

voltage amplifier


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Homework & Lab

•  Homework –  Derive a small-signal model of the circuit to

determine the voltage gain –  Compute the voltage gain –  Design T10 for a voltage gain of 500

•  Lab –  Verify the voltage gain using a ‘DC’ simulation –  Verify the voltage gain using a ‘AC’ simulation

Références

•  D. Johns and K. Martin, "Analog Integrated Circuit Design", John Wiley & Sons, Inc. 1997, ISBN 0-471-14448-7

•  P. Allen and D. Holberg, "CMOS Analog Circuit Design", 2nd Edition, 2002,Oxford University Press, ISBN 0-19-511644-5

•  B. Razavi, "Design of Analog CMOS Integrated Circuits", McGraw Hill, 2001, ISBN 0-07-238032-2

•  P. Gray, P. Hurst, S. Lewis,and R.G. Meyer, “Analysis and Design of Analog Integrated Circuits”, 4th Edition, John Wiley and Sons, 2001, ISBN 0-471-32168-0

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