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M2 EEA – Systèmes Microélectroniques Polytech’montpellier – ERII 3

Analog Integrated Circuits Chapter III

Current mirrors and current sources

Pascal Nouet / 2012-2013 [email protected]

http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html

Introduction

• Analog Integrated Circuits are based on elementary stages – Voltage references – Current mirrors – Current sources – Amplifier stages

• Main caracteristics of a current mirror – Current flow to Vss (ground) or from Vdd – Coefficient of recopy – Quality of recopy

• High output resistance • Range of output voltages (dynamic range)

Outline

• Elementary current mirror • Elementary stages for increased output

resistance – Degenerated source current mirror – Cascode current mirror

• Other elementary current mirrors • Elementary current sources • PMOS current sources

Current mirroring principle

• Biasing (Large Signal Analysis): – T1 is saturated Iin = Ids1 = f(Vgs1) = f(Veff1) – T2 must be saturated to deliver a constant current

• Veff2=Veff1 Output dynamic: Vds ≥ Veff

• Small-Signal Analysis Output resistance

Vs

Iin IS

T1 T2

ineffoxn

dsats IVL

WCµII === 22

vs

gm.vgs2 rds2

vgs2

iS

1/gm1

dsatds

s

s

Ir

iv

λ1

2 ==

Elementary current mirror: output resistance

Vs

Iin IS

T1 T2

Impact of Idsat

y = 0,0044x

0,00E+00

5,00E-02

1,00E-01

1,50E-01

2,00E-01

2,50E-01

3,00E-01

3,50E-01

4,00E-01

4,50E-01

5,00E-01

0,00E+00 2,00E+01 4,00E+01 6,00E+01 8,00E+01 1,00E+02

gds (µA/V)Linéaire (gds (µA/V))

Ids (µA) Vds (V)

Ids (A)

)()()(

1)/( 1 µAIVMr

VµAg dsatds

ds ⋅≅Ω

= −λ


Vs

Iin IS

T1 T2

Impact of transistor length

Vds (V)

Ids (A)

y = 0,093x + 2,718

0,00E+00

2,00E+00

4,00E+00

6,00E+00

8,00E+00

1,00E+01

1,20E+01

1,40E+01

0,00E+00 2,00E+01 4,00E+01 6,00E+01 8,00E+01 1,00E+02

rds (Mohms)

L (µm)

0)()()/( r

AIµmLµmVVr

dsat

eds +

⋅≅


Vs

Iin IS

T1 T2

Impact of transistor size (W/L)

Vds (V)

Ids (A)

0,0

0,5

1,0

1,5

2,0

2,5

3,0

3,5

4,0

4,5

0 10 20 30 40 50

rds (Mohms)

W/L

Elementary current mirror: summary

• Impact of Idsat – Output resistance is divided by two

when current is multiplied by two

• Impact of transistor size – Output resistance doubled when transistor length is

multiplied by two (constant W/L)

• Useful equations – Working with constant Veff

and transistor length

– General case rds α L

Vs

Iin IS

T1 T2

)()(1 1 AIVVI

rvi

dsatds

ds

dss

s ⋅≅∂∂

== −λ

0)()()/( r

AIµmLµmVVr

dsat

eds +

⋅≅

Outline




Degenerated source current mirror

• Large-Signal Analysis – T1 always saturated – Output dynamic saturation of T2

• Small-Signal Analysis – Output resistance

vs

Rs

vs2

iS

Rs

gm2.vgs2 rds2

vg2 1/gm1

Iin IS

T1 T2

Rs Rs

ineffoxn

dsat IVL

WCµI == 2

2

effinSS VIRV +>

( )smdss

S Rgriv

22 1+≅

Degenerated source current mirror

Impact of Rs

50µA IS

T1 T2

Rs Rs

y = 0,9914x + 3,4627

0,0

5,0

10,0

15,0

20,0

25,0

0 5 10 15 20 25

rout (MOhms)

Rs(kΩ)

( ) 10002121 22222 ≈=≅→++=effnneff

dsmsdsmdsout VIVIrgRrgrr

λλ

Outline




Cascode current mirror

• Large-Signal Analysis – T1 and T3 are saturated, T2 also – Output dynamic saturation of T4

• Small-Signal Analysis – Output resistance

Iin IS

T1 T2

T3 T4 vs

gm2.vgs2 rds2

vg2

iS

1/gm1

gm4.vgs4 rds4

vg4 1/gm3

vs2

vs4

ineffoxn

dsat IVL

WCµI == 2

2

efftnS VVV ⋅+> 2

424 dsdsmS

S rrgiv

≅

VS

indddd IIIII ==== 4321

Cascode current mirror

200µA IS

T1 T2

T3 T4

Impact of W/L

Vds (V)

Ids (A)

0

100

200

300

400

500

600

700

800

1 10 100

rout (MOhms)

W/L

Outline




Wilson current mirror

• Similar performance to cascode mirror

• Substrate bias effect:

Iin IS

T1 T2

T3 T4 vx

vgs1

ix

1/gm2

gm4.vgs4 rds4 vgs4 1/gm3

gm1.vgs1 rds1

ineffoxn

dsat IVL

WCµI == 2

2efftnS VVV ⋅+> 2 414 dsdsm

s

S rrgiv

≅

( ) 4144 dsdssms

S rrggiv

+≅⇒

indddd IIIII ==== 4321

PMOS Current Mirrors

• Every NMOS current mirror has a PMOS dual • Cracteristics are identical and easy to

transpose: Vsmin Vsmax, rout

IS

Iin

Vdd

T2 T1

T4 T3

IS

Iin

Vdd

T2 T1

T4 T3

IS

Iin

Vdd

T2 T1 IS

Iin

Vdd

T2 T1 RS RS

dsdsmout rrgr ≅dsout rr ≅

Non-symetrical mirrors

• Different ratio W/L may be used in the output branch (generally X>1 output current higher than reference current)

• Same Veff for all transistors means current proportionnal to W/L:

Vs

Iin IS

T1 T2

1 : X

Vs

Iin IS

T1 T2

T3 T4

1 : X

Iin IS

T1 T2

T3 T4 Vs

1 : X dsdsmout rrgr ≅dsout rr ≅ dsdsmout rrgr ≅

ins IXI ⋅≅

in2

neff2out

in2

neff1out

tneff2S

tneff1S

2Sin1S

I.XV2r

IV2r

VV.2V

VV.2VX

III

λ≅

λ≅

+>

+>

==

inn2out

inn1out

eff2Seff1S

2Sin1S

I.X1r

I1r

VVVVX

III

λ≅

λ≅

>>

==

;

;

Multiple outputs current mirrors

• One reference branch may be connected to as many output branches as recessary for the application

• Each output may deliver a different ratio of current • Each output may have a different output resistance

Iin

VS1

IS1

VS2

IS2

nL

W= n

LW

=nX

LW

=

nL

W= n

LW

=nX

LW

=

VS1 Iin IS1

nL

W= n

LW

=

IS2

nXL

W=

VS2

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50

Miroir simple

SD1

SD2

Cascode

Wilson

Overview of output resistance of elementary current mirors

)(ΩoutR

)(VVS

Outline


resistance • Other elementary current mirrors • Elementary current sources

– Resistance biasing – Transistor biasing – Impact of Vdd

– Impact of T°C

• PMOS current sources

From current mirrors towards current sources

• Analog Integrated Circuits are based on elementary stages – Voltage references – Current mirrors – Current sources – Amplifier stages

Vdd

R

Vs

Iin IS

T1 T2

I=f(V)

T1

Ibias Iout

Vdd

T2

Rp

V1

Current flowing through ground

or from Vdd

Ideal versus actual current sources

Is0

VS

I0

VS

IS

Vmin

ROUT

Vdd

Vdd

Output Resistance and dynamics

Sensitivity to Vdd and T°C

Power consumption

Rout

ISmin

Resistance biasing

• NMOS current sources

• Sizing – Output dynamics Veff

– Output current (Iout) W/L of T2 (T4) – X Reference current (Iin) W/L of T1 (T3), Rp

1 : X

T1

Ibias Iout

Vdd

T2

Rp Vout > Veff

V1

Iout

T1 T2

T3 T4

1 : X

Ibias

Vdd

Rp

> Vtn+2Veff

Iout

T1 T2

T3 T4

1 : X

Ibias

Vdd

Rp

> Vtn+2Veff

Output resistance calculation (e. g. Wilson Current Source )

vx

vgs1

ix

1/gm2

gm4.vgs4 rds4 vgs4 1/gm3

gm1.vgs1 rds1

( )

( ) ( ) ( )2

12

14

11

31

114

11

31

1

111

1)(.

1

m

xpm

m

xgsgs

gsgs

mdsp

pdsmppg

gsm

mdsp

dsp

giRg

giAvAv

Avv

grR

RrgRiRv

vg

grR

rRi

+−≅+−=+−=

−=++

−=−=

++=

Iout

T1 T2

T3 T4

1 : X

Ibias

Vdd

Rp

> Vtn+2Veff Rp

( )

( )

( ) ( ) dspmdsm

out

xdsm

mds

mx

gsmxdsm

xx

rRgrAg

r

irggAr

gv

vgirgiv

⋅+≅⋅++=

+++=

−+=

12

42

44

2

4442

221

11

Transistor biasing

1 : X

T1

Ibias Iout

Vdd

T2

Rp Vout > Veff

V1

Iout

T1 T2

T3 T4

1 : X

Ibias

Vdd

Rp

> Vtn+2Veff

Iout

T1 T2

T3 T4

1 : X

Ibias

Vdd

Rp

> Vtn+2Veff

Ibias

Vdd

Tp Ibias

Vdd

Tp

Ibias

Vdd

Tp

• NMOS Current Sources

– Output dynamics Veff

– Output current (Iout) W/L of T2 (T4) – X Reference current (Iin) W/L of T1 (T3), Tp

Current sources

• Elementary current sources – Resistance biasing – Transistor biasing – Impact of Vdd

– Impact of T°C

• Overview of advanced current sources • PMOS current sources

Outline




– Impact of T°C


Impact of Vdd

I0

VOUT

IS

Vmin

ROUT

Vdd

Vdd

Vout fixe

Resistance biasing

iout

gm2.v1 rds2 v1

Rp

1/gm1

vdd

)(

2

21

1

21

11

TTIII

VVR

VL

WCI

VVV

outbias

bias

ddp

effoxn

bias

tneff

==

−=

⋅⋅=

+=

µ

T1

Ibias Iout

Vdd

T2

Rp Vout=2V (>Veff1)

V1

( )

( ) dd

dd

outpm

ddm

out

out

dd

dd

outpm

ddm

out

out

out

out

pm

ddmmout

VV

IRgVg

II

Vv

IRgVg

Ii

II

Rgvgvgi

∆⋅

+=

∆

⋅+

==∆

+==

1

2

1

2

1212

1

1

1.

Transistor biasing

iout

gm2.v1 rds2 v1 1/gm1

vdd

1/gm3

( ))(

2

2

21

2

13

3

21

1

1

11

TTII

VVVLWC

I

VLWCI

VVV

outbias

tpddoxp

bias

effoxn

bias

tneff

==

−−⋅⋅=

⋅⋅=

+=

µ

µ

T1

Ibias Iout

Vdd

T2

Vout=2V (>Veff1) T3

V1

dd

dd

effeff

dd

out

out

dd

dd

effeff

dd

bias

out

out

out

effeff

bias

mm

mm

mm

ddmmmout

VV

VVV

II

Vv

VVV

Ii

II

VVI

gggg

ggvggvgi

∆⋅

+=

∆

⋅+

==∆

+=

+

+==

31

31

3131

32

31

3212

2

2

2

.

Impact of Vdd on Current Sources

Vdd (V)

Iout (A)

T1

Ibias Iout

Vdd

T2

Rp Vout=2V

T1

IbiasIout

Vdd

T2

Vout=2VT3

dd

dd

out

out

VV

II ∆

⋅=∆ 21,1

dd

dd

out

out

VV

II ∆

⋅=∆ 77,2


T1

Ibias Iout

Vdd

T2

Rp Vout=2V

dd

dd

out

out

VV

II ∆

⋅=∆ 21,1

Rp Vout=2V

Iout

T1 T2

T4

T3

Vdd

dd

dd

out

out

VV

II ∆

⋅=∆ 55,1

Vdd (V)

Iout (A)


8,00E+01

9,00E+01

1,00E+02

1,10E+02

1,20E+02

1,30E+02

1,40E+02

1,50E+02

2,90 3,00 3,10 3,20 3,30 3,40 3,50 3,60 3,70

Miroir simple et résistance

Miroir simple et transistor

Cascode ou wilson et résistance

Cascode ou Wilson et transistor

)(µAIout

)(VVdd

Outline




– Impact of T°C


Resistance biasing and temperature

• An increase in temperature reduces the saturation current of a transistor

T1

Ibias Iout

Vdd

T2

Rp Vout=2V (>Veff1)

V1

9,20E+01

9,40E+01

9,60E+01

9,80E+01

1,00E+02

1,02E+02

1,04E+02

1,06E+02

-40,00 -20,00 0,00 20,00 40,00 60,00 80,00

Polarisation par résistance

-0,08 %/°C

)(µAIout

)C.(Temp °

Resistance biasing and temperature

• Resistance may also change with temperature

T1

Ibias Iout

Vdd

T2

Rp Vout=2V (>Veff1)

V1

-0,08%/°C

( )T.TCR1RR 0pp +=

8,00E+01

8,50E+01

9,00E+01

9,50E+01

1,00E+02

1,05E+02

1,10E+02

1,15E+02

-40,00 -20,00 0,00 20,00 40,00 60,00 80,00

Résistance fixe

TCR=1e-3 /°C

-0,08 %/°C

-0,157 %/°C

)(µAIout

)C.(Temp °

Transistor biasing and temperature

• NMOS et PMOS exhibits same phenomenon

T1

Ibias Iout

Vdd

T2

Vout=2V (>Veff1) T3

V1

8,00E+01

8,50E+01

9,00E+01

9,50E+01

1,00E+02

1,05E+02

1,10E+02

1,15E+02

1,20E+02

-40,00 -20,00 0,00 20,00 40,00 60,00 80,00

Polarisation par R constantePolarisation par R avec TCR=1e-3 /°CPolarisation par PMOS

-0,08 %/°C

-0,157 %/°C

)(µAIout

)C.(Temp °

-0,2 %/°C

8,50E+01

9,00E+01

9,50E+01

1,00E+02

1,05E+02

1,10E+02

1,15E+02

-40,00 -20,00 0,00 20,00 40,00 60,00 80,00

Cascode avec R et TCR=1e-3 /°CPolarisation par R avec TCR=1e-3 /°CCascode pplarisé par PMOS

Cascode Source and temperature

• Feedback may improve results

-0,036 %/°C

-0,157 %/°C

)(µAIout

)C.(Temp °

0,036 %/°C

Rp Vout=2V

Iout

T1 T2

T4

T3

Vdd

Rp Vout=2V

Iout

T1 T2

T4

T3

Vdd

Ibias

Vdd

T3

Outline




– Impact of T°C


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