pll building blocks part 2 - ti training
TRANSCRIPT
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PLL Building Blocks Part 2 TI Precision Labs – Clocks and Timing
Presented by Dean Banerjee
Prepared by Liam Keese
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)fOUT
Phase lock loop (PLL) overview
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fOSC fPD
fN fVCO
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Input sources
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
fOSC
• Crystal oscillator (XO)
• Temperature compensated crystal oscillator (TCXO),
• Oven controlled crystal oscillator (OCXO),
• Clock output from another device
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R
Q
Q
RQ
Q1
fN
fR
1UP
DOWN
tRESET
+Vcc
OUTPUT
Source
Current
Sink
Current
Phase frequency detector/charge pump
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R DividerReference Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
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• High Impedance (tri-state) if output frequency/phase is correct (within tolerances)
• Sources Current if output frequency/phase is too low
• Sinks Current if output frequency/phase is too high
Phase Frequency Detector/Charge Pump Phase detector/charge pump operation
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Loop filter
• The loop filter is a low pass filter
– Has a dramatic effect on performance
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
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Brief overview of loop dynamics
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R Divider
1/D
Output DividerReference
Oscillator
1/N
1/R
VCOLoopFilterPhase
Detector/Charge Pump
N Divider
KPD Z(s)
Kvco/s
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Choosing loop bandwidth
• Choose optimal jitter loop bandwidth to be BWJIT to minimize area under the
curve
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Choosing loop bandwidth
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Design Goal Bandwidth
Minimize Jitter BW = BWJIT
Minimize Phase Noise at
offset < BWJIT
BW > BWJIT
Minimize Phase Noise at
offset > BWJIT
BW < BWJIT
Minimize Lock Time BW > BWJIT
Minimize Spurs BW < BWJIT
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To find more technical resources and search products, visit ti.com/clocks
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Short Quiz
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1. True or False:
The reference input frequency is provided by VCO.
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Short Quiz
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1. True or False:
The reference input frequency is typically fixed frequency and provided by a stable reference
source such as crystal oscillator.
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Short Quiz
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2. Choose one:
The phase detector will
(a) Sink and source current to the loop filter
(b) Sample the phase error between the R and N counter
(c) Provide the output frequency
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Short Quiz
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2. Choose one:
The phase detector will
(a) Sink and source current to the loop filter
(b) Sample the phase error between the R and N counter
(c) Provide the output frequency
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Short Quiz
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3. True or False:
Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.
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Short Quiz
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3. True or False:
Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.
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Short Quiz
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4. Choose all that apply:
When choosing a loop bandwidth, which of these tradeoff are correct?
a) To reduce lock time, increase the loop bandwidth
b) To reduce spurious noise, increase the loop bandwidth
c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth
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Short Quiz
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4. Choose all that apply:
When choosing a loop bandwidth, which of these tradeoff are correct?
a) To reduce lock time, increase the loop bandwidth
b) To reduce spurious noise, increase the loop bandwidth
c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth
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TI Information – Selective Disclosure