pixel hit merging, grouping etc

Pixel Hit Merging, Grouping etc.

Jan. 2005

Outline• Grouping adjacent hits in same column saves data

volume by factor of 1.5-2, as good as BCO ordering.• Hit grouping needs no FIFO, it is a lot simpler than

BCO ordering.• Reduced data volume requires smaller buffer while

doing BCO ordering and one-turn-per-highway scheme.

• Keep an eye open on instantaneous rate:– BCO ordering will increase instantaneous rate to L1

trigger.– Hit grouping will not.

• Merging 72 channels together in PDCB needs some thought.

Input of PDCBb04 b03 b02 b01 b00b09 b08 b07 b06 b05b14 b13 b12 b11 b10b15b20 b19 b18 b17 b16b23 b22 b21

Row Column BCO(7:0) ADC 1Hit24

1Status 000Sync24

0 0XXXInvalid coding:

1 1 1 X0

DCC et al

Module # Chip #

Added in PDCB:

Turn # (Expanded BCO)

Input to L1 Trigger (Pack 4 ADC Using 13 bits)

b04 b03 b02 b01 b00b09 b08 b07 b06 b05b14 b13 b12 b11 b10b15

1 1 1 10Idle:

Status etc.

00

BCO(7:0)

Row ColumnModule #Column Word:

=7

1 1 1 00BCO Word: 0Tn(1:0)

ADC Word:

1 1 1 10Status, Stn, hp. headers: 0-6

Timing Info etc. 1 1 1 0010-3Timing related info/headers:

0 0XXXInvalid Column coding:

1 1 1 X0

Column

ADC3 Chip #Hits ADC0ADC1ADC2

TSO Module: Receiving Data from PDCB

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAMP

2V

ME

P1

Buf

f

PTSMFPGA

Buf

fB

uff

OpticalReceiver

Inputs from 3 PDCB’s

To be merged to 32-bit RAM

Merging in TSO FPGA

BCO Word C1

ADC Word C1Column Word C1

BCO Word B1

ADC Word B1Column Word B1

BCO Word A1

ADC Word A1Column Word A1

BCO Word C2

ADC Word C2Column Word C2

BCO Word B2

ADC Word B2Column Word B2

BCO Word A2

ADC Word A2Column Word A2

BCO Word C1ADC Word C1 Column Word C1BCO Word B1ADC Word B1 Column Word B1BCO Word A1ADC Word A1 Column Word A1

BCO Word C2ADC Word C2 Column Word C2BCO Word B2ADC Word B2 Column Word B2BCO Word A2ADC Word A2 Column Word A2

Address to RAM

Data (32-bit) to RAM

3 Clock (125 MHz)cycles

3 Clock (125 MHz)cycles

How to Pack 4 ADC Using 13 bits


ADC3 Chip #M3

• There are 9 states for a sensor: not hit or ADC = 0-7.

• 4 ADC’s can not be packed in 12 bits, can be packed in 14 bits (4x3 + 2 bits # of hits), but we have only 13 bits.

• In theory, 13 bits can pack 4 items with 10 states each. So 4 ADC with 9 states each can be packed simply.

• There are several ways to pack the 4 hits.

ADC0ADC1ADC2M2M1

ADC3 Chip #1 ADC0ADC1ADC2

Chip #0 ADC0ADC1ADC2

0 Chip #

1

ADC0ADC10 1

Chip #

1

ADC0

11

M0

1

0 0 0

ADC3 Chip #Hits ADC0ADC1ADC2


Chip #0 ADC0ADC1ADC2

0 Chip #ADC0ADC101

Chip #

1

ADC0

1

0 0 1

Pixel Hit Grouping

BCO1

Row1 Column1Module #

1 1 1 000Tn(1:0)

Row1 Column1 BCO1 ADC0 1

Row1+1 Column1 ADC1 1

Row2 Column2 ADC0 1



BCO2


1 1 1 000Tn(1:0)



BCO2

Row2+4 Column2Module #

1 1 1 000Tn(1:0)

BCO2

BCO2

BCO2

BCO2

BCO2

BCO1

Module #

Module #

Module #

Module #

Module #

Module #

Module #

Chip #

Chip #

Chip #

Chip #

Chip #

Chip #

Chip #

• Payload for one hit:

– 4+3+7+5+8+3=30 bits

• Group of 2:

– 64/48=1.3

• Group of 3:

– 96/48=2

• Group of 4:

– 128/48=2.6

• Group of 2.5:– Data volume saving: 1.5

0 Chip #ADC0ADC101


Chip #ADC40 0 1

Hit Group Composer (3-Hit Version)

Row(7 bits)

Col(5 bits)

BCO(8 bits)

ADC(3 bits)

Row2

Col2

BCO2

ADC2

Row1

Col1

BCO1

ADC1

Row0

Col0

BCO0

ADC0

(BCO1==BCO0)(Col1==Col0)

(Row1==(Row0+1))

Used0

(!Used0)

Used1

(BCO2==BCO1)(Col2==Col1)

(Row2==(Row1+1))

Valid

Eq_3_hits

GT_1_hit

About 120 Logic Cells

Row(7 bits)

Col(5 bits)

BCO(8 bits)

ADC0,1,2(9 bits)

Not Affordable:One Hit Group Composer/Channel:

ShiftRegister

Ch. 0

120 Logic Cells each.72 Ch: 8640 LC(32% xc3s1500)

PhaseDetect

FrameDetect

Hit GroupComposer

HoldRegister

PhaseDetect

FrameDetect

Hit GroupComposer

Hit GroupComposerPhase

DetectFrameDetect

Ch. 1

Ch. 23

FIFO

Not Affordable:Even Just Registers and MUX

ShiftRegister

Ch. 0

72 Logic Cells / channel72 Ch: 5184 LC (19% xc3s1500)

PhaseDetect

FrameDetect

HoldRegister

PhaseDetect

FrameDetect

PhaseDetect

FrameDetect

Ch. 1

Ch. 23

FIFOHit GroupComposer

120 Logic Cells each.72 Ch: 3x120=360 LC: OKBut need to keep track of the“next hits”.

Delay Lines

Ch. 0

~160 Logic Cells / 24 channel72 Ch: ~500 LC (2% xc3s1500)

PhaseDetect

FrameDetect

BarrelShifter

PhaseDetect

FrameDetect

PhaseDetect

FrameDetect

Ch. 1

Ch. 23


XAP149

Bit 23

Bit 0

Delay Lines

Shift Reg. 24

Hit GroupComposer

Row, Col, BCO

Shift Reg. 24

ADC

Hit Grouping Logic

Used Word Pipe Used Word Pipe

Row, Col, BCO

ADC0

ADC1

ADC2

Hits

Valid

Ch. 0

Ch. 1

Ch. 23


Ch. 24

Ch. 47


Ch. 48

Ch. 71


FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

Supporting Slides• Details are shown in next a few slides.

Col (5-bits)Pixel hit data:

Some header records:

BCO header:

Half plane header:

Chip header:

0

Bit assignments (From DCC)

Row (7-bits) ADC

1 0000000 BCO – high order

BCO

BCO

1 0000001 0 StationR/L View

1 0000010 0 ModuleChip

BCO header:

Half plane header:

Chip header:

Pixel Data

Same Column Groups

Col (5-bits)0 Row (7-bits) ADC0

1 0000000 BCO – high order

BCO

BCO

1 0000001 0 StationR/L View

1 0000010 0 ModuleChip

Col (5-bits)0 Row+1 ADC1

Col (5-bits)0 Row+2 ADC2

Data Rates

Media # /hwy

Throughput capacities

Data Rates /hwy Safety factors

PDCB to TSO

2.5 Gbps fibers

120 240 Gbps 29.5 Gbps 8.1

TSO to PP 500 Mbps x 4 pairs

160 320 Gbps 19.7 Gbps 16.2

PP to ST/L1B

500 Mbps x 4 pairs

128 256 Gbps (19.7+14.7) Gbps 7.4

ST/L1B to/from BM/Worker

500 Mbps x 2 pairs each way

128 128 Gbps < (19.7/4) Gbps > 26

128 128 Gbps 200 MB/s > 64

BM to GL1 500 Mbps x 2 pairs each way

4 4 Gbps 47 MB/s > 10

Input to L1 Trigger (Simplified from Doc 3342)


1 1 1 10Idle:

Status etc.

00

ADC0

BCO(7:0)

Row ColumnModule #

Chip #

Data word 0:Hits 0 0ADC1ADC2

=7

1 1 1 00BCO & Turn: 0Tn(1:0)

Data word 1 (repeat?):

1 1 1 10Status, Stn, hp. headers: 0-6

Timing Info etc. 1 1 1 0010-3Timing related info/headers:

0 0XXXInvalid Column coding:

1 1 1 X0

Column

Pixel Hit Grouping

ADC0

BCO1


Chip #Hits=2 0 0ADC1

1 1 1 000Tn(1:0)

Row1 Column1 BCO1 ADC0 1


Row2 Column2 ADC0 1



ADC0

BCO2


Chip #Hits=3 0 0ADC1ADC2

1 1 1 000Tn(1:0)



ADC3

BCO2

Row2+3 Column2Module #


1 1 1 000Tn(1:0)

BCO2

BCO2

BCO2

BCO2

BCO2

BCO1

Module #

Module #

Module #

Module #

Module #

Module #

Module #

Chip #

Chip #

Chip #

Chip #

Chip #

Chip #

Chip #

• Payload for one hit:

– 4+3+7+5+8+3=30 bits

• Group of 2:

– 64/48=1.3

• Group of 3:

– 96/48=2

• Group of 4:

– 128/96=1.3

• Group of 2.5:– Data volume saving: 1.5

BCO Header, Column Header

ADC0

BCO1



1 1 1 000Tn(1:0)

ADC0



ADC3 Chip #Hits=2 0 0ADC4

• The types of the words can be recognized from lower 5 bits. So they can be used either as data or header.

• If the BCO is sorted by PDCB, the BCO word can be used as header.

• The Column word can also be used as a header. However, it is not recommended since the instantaneous rate will be too high.

• The easiest is three-word fix-size data stream as shown in previous slide.

ADC0

BCO1



1 1 1 000Tn(1:0)

ADC0



The TSO and PP Stage (Half Highway)

TSO TSO

PP PP PP PP PP PP PP PP

TSO TSOTSO

P2

From PDCB, 5x12 fibers, 2.5 Gb/s/fiber

To Segment Trackers, 8x8 cables, 1.5 Gb/s/cable

Supported Configuration:5x8, Half Highway

TSO Modules PP Modules TSO Modules PP ModulesCPU

P1

P2

The TSO Module

Optical RecZL60102

FPGAVME

Buf

fB

uff

Buf

f

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

• Serial data from optical receiver are sent to FPGA devices at 2.5 Gb/s per channel.

• Time stamp ordering is done in FPGA and RAM.

• Time stamp ordered data are sent to the backplane connector at 300 – 500 Mb/s per pair.

• The data are sent to the PP modules via backplane.

TSO Module

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAM

RAM

FPGA

RAMP

2V

ME

P1

Buf

f

PTSMFPGA

Buf

fB

uff

OpticalReceiver

BarrelShifter


4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

4567 0123

456 0123

45 70123

4 670123

5670123

4567012

456701 3

45670 23

4567 123

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4 5 6 71 2 3 4 5 6 70 1 2 3

4

5

6

0

1

2

3

4

5

7

0

1

2

3

4

6

7

0

1

2

3

5

6

7

0

1

2

3

4

5

6

7

0

1

2

4

5

6

7

0

1

3

4

5

6

7

0

2

3

4

5

6

7

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

Delay Lines

Delay Lines

pixel hit merging, grouping etc

Documents

hit grouping

hit group composerchannel

bco ordering

hitsadc0adc1adc2tso

bits 4x3

reduced data volume

l1 trigger pack

adc4001hit group composer