pipeline processors content/mca_304 advanced... · reservation table for first sequence sa, sb, sc,...

Pipeline

Processors

MCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal

Reservation Table

• Each functional evaluation can be representedusing a diagram called Reservation Table(RT).

• It is the space-time diagram of a pipelinecorresponding to one functional evaluation.

X axis – time units

Y axis – stages

Columns represent the evaluation time for a given function

Multiple checkmarks in a row, means repeated usage of the same stage in different cycles


Reservation Table

For first sequence Sa, Sb, Sc, Sb, Sc, Sa

called function A , we have

0 1 2 3 4 5

Sa A A

Sb A A

Sc A A


Reservation Table

For second sequence Sa, Sc, Sb, Sa, Sb, Sc

called function B, we have

0 1 2 3 4 5

Sa B B

Sb B B

Sc B B


3-Stage Non-Linear PipelineOutput A

Output BSa Sb Sc

Input

Reservation TableTime

Stag

e

0 1 2 3 4 5

Sa

Sb

ScMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal

Function A


3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa

Sa Sb ScInput Output B

Output A


Stag

e

0 1 2 3 4 5

Sa A

Sb




Output A


Stag

e

0 1 2 3 4 5

Sa A

Sb A




Output A


Stag

e

0 1 2 3 4 5

Sa A

Sb A

Sc AMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal



Output A


Stag

e

0 1 2 3 4 5

Sa A

Sb A A

Sc AMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal



Output A


Stag

e

0 1 2 3 4 5

Sa A

Sb A A

Sc A AMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal



Output A


Stag

e

0 1 2 3 4 5

Sa A A

Sb A A

Sc A AMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal

Function B


3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc


Output A


Stag

e

0 1 2 3 4 5

Sa B

Sb




Output A


Stag

e

0 1 2 3 4 5

Sa B

Sb

Sc BMCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal



Output A


Stag

e

0 1 2 3 4 5

Sa B

Sb B




Output A


Stag

e

0 1 2 3 4 5

Sa B B

Sb B




Output A


Stag

e

0 1 2 3 4 5

Sa B B

Sb B B




Output A


Stag

e

0 1 2 3 4 5

Sa B B

Sb B B

Sc B B


Latency Analysis

Latency: The number of time units (clock cycles) between twoinitiations of a pipeline is the latency between them.

A latency value k means that two initiations are separated by k clock cycles.

Collision: An attempt by two or more initiations to use thesame pipeline stage at the same time. Collision impliesresource conflicts b/w two initiations in the pipeline.

Some latencies cause collision, some not. Latencies that willcause collision are called Forbidden Latencies and thelatencies that will not cause collision are called PermissibleLatencies.


Latency Cycles

A latency sequence is a sequence of permissible

nonforbidden latencies between successive task

initiations.

A latency cycle is a latency sequence which

repeats the same subsequence indefinitely.


Latency Cycle

x1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

x1

x1

x1

x1

x1

x1

x2 x1

x2

x2

x2

x2

x2 x3

x2

x2

x3

x3

x3

x3

18

x3

Cycle Cycle

A latency sequence is a sequence of permissible nonforbidden latencies

between successive task initiations.

A latency cycle is a latency sequence which repeats the same subsequence

indefinitely.


Example

S1 S2 S3

YX


Reservation Tables for X & Y

X X X

X X

X X X

Y Y

Y

Y Y Y

S1

S2

S3

S1

S2

S3


Forbidden Latencies

To detect the forbidden latencies, check the

distance between two checkmarks in the

same row of the reservation table.


X after X

X1 X2 X1 X2 X1

X1 X2 X1 X2

X1 X2 X1 X2 X1

S1

S2

S3

2

X X X

X X

X X X

S1

S2

S3


X after X

X1 X2 X1 X1

X1 X1 X2

X1 X1 X1 X2

S1

S2

S3

5

X X X

X X

X X X

S1

S2

S3


X after X

X1 X2 X1 X1

X1 X1 X2 X2

X1 X1 X2X1

S1

S2

S3

4

X X X

X X

X X X

S1

S2

S3


X after X

X1 X1 X2 X1

X1 X1

X1 X1 X1

S1

S2

S3

7

X X X

X X

X X X

S1

S2

S3


Collision Vector

Combined set of permissible and forbidden latencies.

Forbidden Latencies: 2, 4, 5, 7

Collision vectorC = (Cm, Cm-1, …, C2, C1), m <= n-1

n = number of column in reservation table

The value of Ci = 1 if the latency i causes a collision; Ci = 0 if the latency i is permissible.

Collision Vector = 1 0 1 1 0 1 0


Y after Y

Y Y Y

Y Y

Y Y Y Y Y

S1

S2

S3

Y Y Y

Y

Y Y Y Y

S1

S2

S3


Collision Vector

Forbidden Latencies: 2, 4

Collision vector

C = (Cm, Cm-1, …, C2, C1), m <= n-1

n = number of column in reservation table

Ci = 1 if latency i causes collision, 0 otherwise

Collision Vector = 1 0 1 0


Collision Vector

x

x

x

x

x

x

Reservation Table

C = (? ? . . . ? ?)


Exercise – Find the collision vector

1 2 3 4 5 6 7

A X X X

B X X

C X X

D X


State Diagram

State diagrams can be constructed to specify the

permissible transitions among successive initiations.

The collision vector, corresponding to the initial state of

pipeline at time 1, is called the initial collision vector

(ICV).


State Diagram The next state of the pipeline at time t+p can be obtained by

using a bit-right shift register

• Initial CV is loaded into the register.

• The register is then shifted to the right.

– When a 0 emerges from the right end after p shifts, p is a

permissible latency.

– When a 1 emerges, the corresponding latency should be

forbidden latency.

• Logical 0 enters from the left end of the shift register.

• The next state after p shifts is obtained by bitwise-ORing

the initial CV with the shifted register contents.


Right Shift Register

The next state can be obtained with the help of an p-bit shift

register

0

0

1 Collision

Safe to allow an

initiation

Each 1-bit shift corresponds to increase in the latency by 1.

latency.


The Next State

The next state is obtained by bitwiseORing the initial collision vector with theshifted register

C.V. = 1 0 1 1 0 1 0 (first state)

0 1 0 1 1 0 1 C.V. 1-bit right shifted1 0 1 1 0 1 0 initial C.V.---------------- OR1 1 1 1 1 1 1


State Diagram for X

1 0 1 1 0 1 0

1 1 1 1 1 1 11 0 1 1 0 1 1

3

6 8+

6

8+

8+

3*

1


Group Activity 11 2 3 4

S1 X X

S2 X

S3 X

a. What are the forbidden latency ?

b. Draw the state transition diagram.

c. List all the simple cycles and greedy cycles.

d. Determine the minimal average latency (MAL).

e. Determine the throughput of this pipeline.


pipeline processors content/mca_304 advanced... · reservation table for first sequence sa, sb, sc,...

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