pic18fxx2 registers - university of...

File: PIC18F452 SFRs.doc Created: DCR, 06/03/2005 12:12:00

PIC18FXX2 Registers This document provides a concise summary of the names and bit definitions for the PIC18FXX2 Special Function Registers, Configuration Registers and Device ID Registers.

Hyperlinked Index Page Notation 2

Special Function Registers

Special Function Register Names 3 “Core” SFRs – Bit Names 4 “Peripheral” SFRs – Bit Names 5 CPU Related 6

WREG (Accumulator), STATUS (Flags) Program Counter 6

PCLATU, PCLATH, PCL Hardware Multiplier 7

PRODH, PRODL Stack Access 7

TOSU, TOSH, TOSL, STKPTR Table Pointer 8

TBLPTRU, TBLPTRH, TBLPTRL, TABLAT Interrupt System 9

INTCON, INTCON2, INTCON3, PIR1, PIR2, PIE1, PIE2, IPR1, IPR2Bank Select Register – for Banked (Direct) Addressing 16

BSR File Select Registers – for Indirect Addressing 16

INDF0, POSTINC0, POSTDEC0, PREINC0, PLUSW0, FSR0H, FSR0L, INDF1, POSTINC1, POSTDEC1, PREINC1, PLUSW1, FSR1H, FSR1L, INDF2, POSTINC2, POSTDEC2, PREINC2, PLUSW2, FSR2H, FSR2L

Timers 19 Timer0: TMR0H, TMR0L, T0CON 19 Timer1: TMR1H, TMR1L, T1CON 20 Timer2: TMR2, PR2, T2CON 21 Timer3: TMR3H, TMR3L, T3CON 22

Miscellaneous Control/Status Registers 23 OSCCON, LVDCON, WDTCON, RCON

Master Synchronous Serial Port (MSSP) 25 SSPBUF, SSPADD, SSPSTAT (SPI mode), SSPCON (SPI mode), SSPSTAT (I2C mode), SSPCON (I2C mode)

Analog to Digital Converter 30 ADRESH, ADRESL, ADCON0, ADCON1

Capture/Compare/PWM (CCP) Modules 32 CCP1: CCP1H, CCP1L, CCP1CON 32 CCP2: CCP2H, CCP2L, CCP2CON 33

USART Module 34 SPBRG, RCREG, TXREG, TXSTA, RCSTA

EEPROM 36 EEADR, EEDATA, EECON1, EECON2

I/O Ports 38 PortA: PORTA, LATA, TRISA 38 PortB: PORTB, LATB, TRISB 39 PortC: PORTC, LATC, TRISC 41 PortD: PORTD, LATD, TRISD 42 PortE: PORTE, LATE, TRISE 43

Configuration, Device Revision and Device ID Registers

Configuration Register Summary 45 CONFIG0H: Clock Configuration 45 CONFIG2L: Brown-out Detect and Power-on Reset 45 CONFIG2H: Watchdog Timer 46 CONFIG3H: CCP2 Multiplex 46 CONFIG5L: Code Protection Bits 46 CONFIG5H: EEPROM and Boot Block Code Protection Bits 47 CONFIG6L: FLASH Write Protection Bits 47 CONFIG6H: EEPROM/Boot Block/Configuration Register Write Protect Bits 47 CONFIG7L: Table Read Protection Bits 48 CONFIG7H: Boot Block Table Read Protection Bit 48

DEVID1: Device Revision and ID Register 1 48 DEVID2: Device ID Register 2 48

Notation The COURIER font denotes literal names of registers or bits. These names are also defined in the Microchip assembler and compiler include files. Bit names are denoted by angle brackets < > – for example, T0CON<TMR0ON> is the “Timer0 On” bit TMR0ON of the Timer0 Control special function register T0CON. A range of registers or bits is denoted by a colon : – for example, SSPCON1<SSPM3:SSPM0> are the 4 Synchronous Serial Port Mode bits SSPM3, SSPM2, SSPM1, SSPM0 of the Synchronous Serial Port Control1 special function register SSPCON1. A bit function that is asserted low (negative logic) is denoted by a hash mark #. For example, D/#A is the Data/notAddress bit of the SSPSTAT register. This is normally written using an overbar: D/A in datasheets. Readable/Writable Special function register bits may be Readable and/or Writable:

• R: Readable bit • U-0: Unimplemented bit – always reads as 0 • W: Writable bit

Reset Status Values are given below for each register following a Power-On (PO) or Brown-Out (BO) Reset, or a Master Clear (MCLR). Codes used are:

• 0: bit is cleared • 1: bit is set • q: bit value depends on condition. • u: bit value is unchanged by the reset. • x: bit value is unknown – it could be either 0 or 1

Configuration Bits Configuration register bits may be Readable and/or Programmable. Codes used are:

• C: bit resets to 1, but can subsequently be cleared • R: readable • P: programmable • U: unimplemented bit, read as ‘0’ • -n: value when device is un-programmed • u: unchanged from programmed state

Page numbers refer to the Microchip PIC18FXX2 Data Sheet 2002, document DS39564B. Shaded areas are not implemented, or not relevant to the particular mode.

Special Function Registers This section summarises the PIC18FXX2 special function registers, arranged in approximate numerical order of address, from 0xFFF to 0xF80, but modified to group the SFRs by their primary function.

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Table 1: PIC18F2XX Special Function Register Names

Address Name Address Name Address Name Address Name 0xFFF TOSU 0xFDF INDF2(3) 0xFBF CCPR1H 0xF9F IPR1

0xFFE TOSH 0xFDE POSTINC2(3) 0xFBE CCPR1L 0xF9E PIR1

0xFFD TOSL 0xFDD POSTDEC2(3) 0xFBD CCP1CON 0xF9D PIE1

0xFFC STKPTR 0xFDC PREINC2(3) 0xFBC CCPR2H 0xF9C —

0xFFB PCLATU 0xFDB PLUSW2(3) 0xFBB CCPR2L 0xF9B —

0xFFA PCLATH 0xFDA FSR2H 0xFBA CCP2CON 0xF9A —

0xFF9 PCL 0xFD9 FSR2L 0xFB9 — 0xF99 —

0xFF8 TBLPTRU 0xFD8 STATUS 0xFB8 — 0xF98 —

0xFF7 TBLPTRH 0xFD7 TMR0H 0xFB7 — 0xF97 —

0xFF6 TBLPTRL 0xFD6 TMR0L 0xFB6 — 0xF96 TRISE(2)

0xFF5 TABLAT 0xFD5 T0CON 0xFB5 — 0xF95 TRISD(2)

0xFF4 PRODH 0xFD4 — 0xFB4 — 0xF94 TRISC

0xFF3 PRODL 0xFD3 OSCCON 0xFB3 TMR3H 0xF93 TRISB

0xFF2 INTCON 0xFD2 LVDCON 0xFB2 TMR3L 0xF92 TRISA

0xFF1 INTCON2 0xFD1 WDTCON 0xFB1 T3CON 0xF91 —

0xFF0 INTCON3 0xFD0 RCON 0xFB0 — 0xF90 —

0xFEF INDF0(3) 0xFCF TMR1H 0xFAF SPBRG 0xF8F —

0xFEE POSTINC0(3) 0xFCE TMR1L 0xFAE RCREG 0xF8E —

0xFED POSTDEC0(3) 0xFCD T1CON 0xFAD TXREG 0xF8D LATE(2)

0xFEC PREINC0(3) 0xFCC TMR2 0xFAC TXSTA 0xF8C LATD(2)

0xFEB PLUSW0(3) 0xFCB PR2 0xFAB RCSTA 0xF8B LATC

0xFEA FSR0H 0xFCA T2CON 0xFAA — 0xF8A LATB

0xFE9 FSR0L 0xFC9 SSPBUF 0xFA9 EEADR 0xF89 LATA

0xFE8 WREG 0xFC8 SSPADD 0xFA8 EEDATA 0xF88 —

0xFE7 INDF1(3) 0xFC7 SSPSTAT 0xFA7 EECON2 0xF87 —

0xFE6 POSTINC1(3) 0xFC6 SSPCON1 0xFA6 EECON1 0xF86 —

0xFE5 POSTDEC1(3) 0xFC5 SSPCON2 0xFA5 — 0xF85 —

0xFE4 PREINC1(3) 0xFC4 ADRESH 0xFA4 — 0xF84 PORTE(2)

0xFE3 PLUSW1(3) 0xFC3 ADRESL 0xFA3 — 0xF83 PORTD(2)

0xFE2 FSR1H 0xFC2 ADCON0 0xFA2 IPR2 0xF82 PORTC

0xFE1 FSR1L 0xFC1 ADCON1 0xFA1 PIR2 0xF81 PORTB

0xFE0 BSR 0xFC0 — 0xFA0 PIE2 0xF80 PORTA

Notes 1: Unimplemented registers will always read as ‘0’. 2: This register is not available on PIC18F2X2 devices. 3: This is not a physical register.

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Table 2: “Core” Special Function Registers – Related to CPU and Addressing

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR

Details on page:

TOSU — — — Top-of-Stack upper Byte (TOS<20:16>) ---0 0000 37 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 37 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 38 PCLATU — — — Holding Register for PC<20:16> ---0 0000 39 PCLATH Holding Register for PC<15:8> 0000 0000 39 PCL PC Low Byte (PC<7:0>) 0000 0000 39 TBLPTRU — — bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 58 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 58 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 58 TABLAT Program Memory Table Latch 0000 0000 58 PRODH Product Register High Byte xxxx xxxx 71 PRODL Product Register Low Byte xxxx xxxx 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 75 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 76 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 77 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a 50 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a 50 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a 50 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a 50 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register). Offset by value in WREG. n/a 50 FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 50 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50 WREG Working Register xxxx xxxx n/a INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a 50 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a 50 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a 50 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a 50 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register). Offset by value in WREG. n/a 50 FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50 FSR1L xxxx xxxx 50 BSR — — — — Bank Select Register ---- 0000 49 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a 50 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a 50 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a 50 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a 50 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register). Offset by value in WREG. n/a 50 FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50 STATUS — — — N OV Z DC C ---x xxxx 52

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Notes 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and will always read as '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

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Table 3: “Peripheral” Special Function Registers – Control Peripherals

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR

Details on page:

TMR0H Timer0 Register High Byte 0000 0000 105 TMR0L Timer0 Register Low Byte xxxx xxxx 105 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 103 OSCCON — — — — — — — SCS ---- ---0 21 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 191 WDTCON — — — — — — — SWDTE ---- ---0 203 RCON IPEN — — R I TO PD POR BOR 0--1 11qq 53, 28, 84 TMR1H Timer1 Register High Byte xxxx xxxx 107 TMR1L Timer1 Register Low Byte xxxx xxxx 107 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 107 TMR2 Timer2 Register 0000 0000 111 PR2 Timer2 Period Register 1111 1111 112 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 111 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 125 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 134 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 126 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 127 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 137 ADRESH A/D Result Register High Byte xxxx xxxx 187,188 ADRESL A/D Result Register Low Byte xxxx xxxx 187,188 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 181 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 182 CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 121, 123 CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 121, 123 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 117 CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 121, 123 CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 121, 123 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 117 TMR3H Timer3 Register High Byte xxxx xxxx 113 TMR3L Timer3 Register Low Byte xxxx xxxx 113 T3CON RD16 CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 113 SPBRG USART1 Baud Rate Generator 0000 0000 168 RCREG USART1 Receive Register 0000 0000 175, 178, 180 TXREG USART1 Transmit Register 0000 0000 173, 176, 179 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 166 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 167 EEADR Data EEPROM Address Register 0000 0000 65, 69 EEDATA Data EEPROM Data Register 0000 0000 69 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 65, 69 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 66 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 83 PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 79 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 81 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 82 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 78 PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 80 TRISE(3) IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 98 TRISD(3) Data Direction Control Register for PORTD 1111 1111 96 TRISC Data Direction Control Register for PORTC 1111 1111 93 TRISB Data Direction Control Register for PORTB 1111 1111 90 TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 87 LATE(3) — — — — — Read PORTE Data Latch, Write PORTE Data Latch ---- -xxx 99 LATD(3) Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 95 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 93 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 90 LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 87 PORTE(3) Read PORTE pins, Write PORTE Data Latch ---- -000 99 PORTD(3) Read PORTD pins, Write PORTD Data Latch xxxx xxxx 95 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 93 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 90 PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 87

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Notes 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear (‘0’).

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CPU Related

WREG: Working Register (Accumulator) 0xFE8

R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The WREG bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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STATUS: Status (Flags) Register 0xFD8

p. 52 U-0 U-0 U-0 R/W R/W R/W R/W R/W

Bit Names - - - N OV Z DC C

bit 7 bit 0 PO/BO Reset - - - x x x x x MCLR Reset - - - u u u u u bit 4 N: Negative bit.

1: Result was negative 0: Result was positive

bit 3 OV: Overflow bit. 1: Overflow of bit 7 occurred during signed arithmetic operation 0: No overflow occurred

bit 2 Z: Zero bit. 1: Result of operation was zero 0: Result of operation was not zero

bit 1 DC: Digit Carry bit. 1: Carry-out from the 4th low order bit of result occurred 0: No carry from the 4th low order bit of result occurred

bit 0 C: Carry bit. 1: Carry-out from the MSB of result occurred on addition (OR No borrow occurred on subtraction) 0: Carry from the MSB of result did not occur on addition (OR Borrow occurred on subtraction)

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Program Counter (PC) Register – 21 bits

PCLATU: Program Counter Latch Register, Upper Byte 0xFFB

PCLATH: Program Counter Latch Register, High Byte 0xFFA

PCL: Program Counter Register, Low Byte 0xFF9

p. 39 R/W R/W R/W Byte Names PCLATU PCLATH PCL 0xFFB 0xFFA 0Xff9 PO/BO Reset --- 0 0000 0000 0000 0000 0000 MCLR Reset --- 0 0000 0000 0000 0000 0000 The PC register is a 21-bit register that stores the address of the next program instruction to be fetched.

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Hardware Multiplication

Product of Multiplication Register – 16 bits

PRODH: Product of Multiplication Register, High Byte 0xFF4

PRODL: Product of Multiplication Register, Low Byte 0xFF3

p. 71 R/W R/W Bit Names PRODH PRODL 0xFF4 0xFF3 PO/BO Reset xxxx xxxx xxxx xxxx MCLR Reset uuuu uuuu uuuu uuuu The PRODH:PRODL register is a 16-bit register that receives the result of an 8x8 hardware multiply.

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Stack Access

Top Of Stack (TOS) Register – 21 bits

TOSU: Top Of Stack Upper Register (TOS<20:16>) 0xFFF

TOSH: Top Of Stack Higher Register (TOS<15:8) 0xFFE

TOSL: Top Of Stack Lower Register (TOS<7:0>) 0xFFD

p. 37 R/W R/W R/W Byte Names TOSU TOSH TOSL 0xFFF 0xFFE 0xFFD PO/BO Reset --- 0 0000 0000 0000 0000 0000 MCLR Reset --- 0 0000 0000 0000 0000 0000

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STKPTR: Return Stack Pointer Register 0xFFC

p. 38 R/W R/W U-0 R/W R/W R/W R/W R/W Bit Names STKFUL STKUNF - STKPTR4 STKPTR3 STKPTR2 STKPTR1 STKPTR0 bit 7 bit 0 PO/BO Reset 0 0 - 0 0 0 0 0 MCLR Reset 0 0 - 0 0 0 0 0 bit 7 STKFUL: Stack Full Flag bit.

Note: Can only be cleared by user software or a POR. 1: Stack is full (31 entries) or has overflowed. 0: Stack has not become full or has overflowed.

bit 6 STKUNF: Stack Overflow Flag bit. Note: Can only be cleared by user software or a POR.

1: Stack underflow has occurred. 0: Stack has not underflowed.

bit 5 Not implemented – reads as 0. bit 4-0 STKPTR4:STKPTR0: Stack pointer value bits. This 5-bit field contains the hardware stack pointer value, between 0 and 31 inclusive.

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Table Pointer

Table Pointer (TBLPTR) Register – 22 bits

TBLPTRU: Table Pointer Register, Upper Byte 0xFF8

TBLPTRH: Table Pointer Register, High Byte 0xFF7

TBLPTRL: Table Pointer Register, Low Byte 0xFF6

p. 58 R/W R/W R/W Byte Names TBLPRTU TBLPRTH TBLPRTL 0xFF8 0xFFA7 0XFF6 PO/BO Reset -- 00 0000 0000 0000 0000 0000 MCLR Reset -- 00 0000 0000 0000 0000 0000 The TABLPTR register is a 22-bit register used to hold a (21-bit) program memory address during transfers between program memory and data RAM. Note: Set bit 21 to enable access to the device configuration bits.

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TABLAT: Table Latch Register 0xFF5

p. 58 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The TABLAT bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 The TABLAT register is an 8-bit register used to hold data during transfers between program memory and data RAM. It is the ONLY register that is accessible from both Program Memory and Data Memory.

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Interrupt System

INTCON: Interrupt Control Register 0xFF2

p. 75 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names GIE /

GIEH PEIE / GIEL

TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 x MCLR Reset 0 0 0 0 0 0 0 u bit 7 GIE/GIEH: Global Interrupt Enable bit.

When RCON<IPEN> = 0: 1: Enables response to all unmasked interrupts.

0: Disables response to all interrupt requests. When RCON<IPEN> = 1 1: Enables response to high-priority interrupts.

0: Disables response to all high-priority interrupts. bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit.

When RCON<IPEN> = 0: 1: Enables response to all unmasked peripheral interrupt requests.

0: Disables response to any peripheral interrupt request. When RCON<IPEN> = 1 1: Enables response to all low-priority interrupts. 0: Disables response to all low-priority interrupts.

0: Low priority. bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit.

1: Enables the Timer0 overflow interrupt. 0: Disables the Timer0 overflow interrupt.

bit 4 INT0IE: INT0 External Interrupt Enable bit. 1: Enables the INT0 external interrupt. 0: Disables the INT0 external interrupt.

bit 3 RBIE: RB Port Change Interrupt Enable bit. 1: Enables the RB port change interrupt. 0: Disables the RB port change interrupt.

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit. 1: Timer0 register has overflowed. Note: Clear this bit in software. 0: Timer0 register did not overflow.

bit 1 INT0IF: INT0 External Interrupt Flag bit. 1: An INT0 external interrupt occurred. Note: Clear this bit in software. 0: An INT0 external interrupt did not overflow.

bit 0 RBIF: RB Port B Change Interrupt Flag bit. 1: At least on of the Port B pins RB7:RB4 changed state. Note: Clear this bit in software. 0: None of the Port B pins RB7:RB4 changed state.

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INTCON2: Interrupt Control Register 2 0xFF1

p. 76 R/W R/W R/W R/W U-0 R/W U-0 R/W Bit Names RBPU INTEDG0 INTEDG1 INTEDG2 - T0IP - RBIP bit 7 bit 0 PO/BO Reset 1 1 1 1 - 1 - 1 MCLR Reset 1 1 1 1 - 1 - 1 bit 7 RPBU: PORTB Pull-up Resistor Enable bit. Note: Negative logic.

1: All PORTB pull-up resistors are disabled. 0: PORTB pull-up resistors are enabled by individual port latch values.

bit 6 INTEDG0: External Interrupt0 Edge Select bit. 1: Interrupt on rising edge. 0: Interrupt on falling edge.



bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1: High priority. 0: Low priority.

bit 0 RBIP: RB Port Change Interrupt Priority bit 1: High priority. 0: Low priority.

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INTCON3: Interrupt Control Register 3 0xFF0

p. 77 R/W R/W U-0 R/W R/W U-0 R/W R/W Bit Names INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF bit 7 bit 0 PO/BO Reset 1 1 - 0 0 - 0 0 MCLR Reset 1 1 - 0 0 - 0 0 bit 7 INT2IP: INT2 External Interrupt Priority bit.

1: High priority. 0: Low priority.

bit 6 INT1IP: INT1 External Interrupt Priority bit. 1: High priority. 0: Low priority.



bit 1 INT2IF: INT2 External Interrupt Flag bit. 1: An INT2 external interrupt request has occurred. Clear in software before enabling interrupt response. 0: An INT2 external interrupt has not been requested.

bit 0 INT1IF: INT1 External Interrupt Flag bit. 1: An INT1 external interrupt request has occurred. Clear in software before enabling interrupt response. 0: An INT1 external interrupt has not been requested.

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PIR1: Peripheral Interrupt Request (Flag) Register 1 0xF9E

p. 79 R/W R/W R R R/W R/W R/W R/W Bit Names PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 PSPIF: Parallel Slave Port Interrupt Flag bit. Note: Must always be 0 on 18F2X2 devices.

1: A PSP read or write has taken place. Clear this bit in software following a PSP R/W. 0: No read or write has occurred.

bit 6 ADIF: A/D Converter Interrupt Flag bit 1: An A/D conversion has completed. Clear this bit in software following an A/D conversion. 0: No A/D conversion has occurred.

bit 5 RCIF: USART Receive Interrupt Flag bit 1: The USART receive buffer, RCREG, is full. This bit is cleared when RCREG is read. 0: The USART receive buffer is empty.

bit 4 TXIF: USART Transmit Interrupt Flag bit 1: The USART transmit buffer, TXREG, is empty. This bit is cleared when TXREG is written. 0: The USART receive buffer is full.

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1: The transmission or reception is complete. Clear this bit in software following a SSP event. 0: Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture Mode: 1: A TMR1 register capture has occurred. Clear this bit in software.

0: NoTMR1 register capture has occurred. Compare Mode: 1: A TMR1 register compare match capture has occurred. Clear this bit in software.

0: No TMR1 register compare match capture has occurred. PWM Mode: Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1: TMR2 to PR2 match has occurred. Clear this bit in software following a TMR2 to PR2 match event. 0: No TMR2 to PR2 match has occurred.

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1: TMR1 register has overflowed. Clear this bit in software following a TMR1 overflow. 0: TMR1 register has not overflowed.

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PIR2: Peripheral Interrupt Request (Flag) Register 2 0xFA1

p. 79 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names - - - EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 PO/BO Reset - - - 0 0 0 0 0 MCLR Reset - - - 0 0 0 0 0 bit 4 EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit.

1: The Write operation is complete. Clear this bit in software, so that another (future) write operation completion can be detected.

0: The Write operation is in progress, or has not been started. bit 3 BCLIF: Bus Collision Interrupt Flag bit.

1: A bus collision has occurred. Clear this bit in software, so that another (future) bus collision can be detected.

0: No bus collision has occurred. bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit.

1: A low voltage condition has occurred. Clear this bit in software, so that another (future) low voltage condition can be detected.

0: The device voltage is above the Low Voltage Detect trip point. bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit.

1: TMR3 register has overflowed. Clear this bit in software, so that another overflow can be detected. 0: TMR3 register has not overflowed.

bit 0 CCP2IF: CCP2 Interrupt Flag bit. Capture Mode: 1: A TMR1 register capture has occurred. Clear this bit in software.

0: NoTMR1 register capture has occurred. Compare Mode: 1: A TMR1 register compare match capture has occurred. Clear this bit in software.

0: No TMR1 register compare match capture has occurred. PWM Mode: Unused in this mode

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PIE1: Peripheral Interrupt Enable Register 1 0xF9D

p. 80 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 PSPIE: Internal Reference Voltage Stable bit.

1: Enables the PSP read/write interrupt. 0: Disables the PSP read/write interrupt.

bit 6 ADIE: A/D Conversion Interrupt Enable bit. 1: Enables the PSP read/write interrupt. 0: Disables the PSP read/write interrupt.

bit 5 RCIE: USART Receive Interrupt Enable bit. 1: Enables the UART receive interrupt. 0: Disables the UART receive interrupt.

bit 4 TXIE: USART Transmit Interrupt Enable bit. 1: Enables the UART transmit interrupt. 0: Disables the UART transmit interrupt.

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit. 1: Enables the MSSP interrupt. 0: Disables the MSSP interrupt.

bit 2 CCP1IE: CCP1 Interrupt Enable bit. 1: Enables the CCP1 interrupt. 0: Disables the CCP1 interrupt.

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit. 1: Enables the TMR2 to PR2 match interrupt. 0: Disables the TMR2 to PR2 match interrupt.

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit. 1: Enables the TMR1 overflow interrupt. 0: Disables the TMR1 overflow interrupt.

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PIE2: Peripheral Interrupt Enable Register 2 0xFA0

p. 81 U-0 U-0 U-0 R/W R/W R/W R/W R/W Bit Names - - - EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 PO/BO Reset - - - 0 0 0 0 0 MCLR Reset - - - 0 0 0 0 0 bit 4 EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit.

1: Enabled. 0: Disabled.

bit 3 BCLIE: Bus Collision Interrupt Enable bit. 1: Enabled. 0: Disabled.

bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit. 1: Enabled. 0: Disabled.

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit. 1: TMR3 Overflow Interrupt Enabled. 0: TMR3 Overflow Interrupt Disabled.

bit 0 CCP2IE: CCP2 Interrupt Enable bit. 1: CCP2 Interrupt Enabled. 0: CCP2 Interrupt Disabled.

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IPR1: Peripheral Interrupt Priority Register 1 0xF9F

p. 82 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit. Note: Must always be 1 on 18F2X2 devices.


bit 6 ADIP: A/D Converter Interrupt Priority bit 1: High priority. 0: Low priority.

bit 5 RCIP: USART Receive Interrupt Priority bit 1: High priority. 0: Low priority.

bit 4 TXIP: USART Transmit Interrupt Priority bit 1: High priority. 0: Low priority.

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1: High priority. 0: Low priority.

bit 2 CCP1IP: CCP1 Interrupt Priority bit 1: High priority. 0: Low priority.

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1: High priority. 0: Low priority.


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IPR2: Peripheral Interrupt Priority Register 2 0xFA2

p. 83 U-0 U-0 U-0 R/W R/W R/W R/W R/W Bit Names - - - EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 PO/BO Reset - - - 1 1 1 1 1 MCLR Reset - - - 1 1 1 1 1 bit 4 EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit


bit 3 BCLIP: Bus Collision Interrupt Priority bit 1: High priority. 0: Low priority.

bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit. 1: High priority. 0: Low priority.


bit 0 CCP2IP: CCP2 Interrupt Priority bit 1: High priority. 0: Low priority.

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Bank Select Register – for (Banked) Direct Addressing

BSR: Bank Select Register 0xFE0

p. 49 U-0 U-0 U-0 U-0 R/W R/W R/W R/W Bit Names - - - - BSR3 BSR2 BSR1 BSR0 bit 7 bit 0 PO/BO Reset - - - - 0 0 0 0 MCLR Reset - - - - 0 0 0 0 bit 3-0 BSR3:BSR0: Bank select bits. This 4-bit field contains the upper 4 bits of the 12-bit data RAM address, allowing one of 16 banks of

256 data RAM addresses to be selected. back to Index

File Select Registers – for Indirect Addressing

INDF0 0xFEF INDF0 is associated with using FSR0 for indirect addressing of data memory. INDF0 has the value of FSR0. It is not a physical register. See p. 50.

POSTINC0 0xFEE POSTINC0 is associated with using FSR0 for indirect addressing of data memory. POSTINC0 is the value of FSR0 post-incremented. It is not a physical register.

POSTDEC0 0xFED POSTDEC0 is associated with using FSR0 for indirect addressing of data memory. POSTDEC0 is the value of FSR0 post-decremented. It is not a physical register.

PREINC0 0xFEC PREINC0 is associated with using FSR0 for indirect addressing of data memory. PREINC0 is the value of FSR0 pre-incremented. It is not a physical register.

PLUSW0 0xFEB PLUSW0 is associated with using FSR0 for indirect addressing of data memory. PLUSW0 is the value of FSR0 offset (increased) by the value in WREG. It is not a physical register. See p. 50.

FSR0: File Select Register 0 (Indirect Data Memory Address Pointer 0, 12 bits)

FSR0H: High Byte (4 bits) 0xFEA

FSR0L: Low Byte (8-bits) 0xFE9

p. 50 R/W R/W Byte Names FSR0H FSR0L 0xFEA 0xFE9 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR1 = FSR1H:FSR1L register is a read or write to the data memory address pointed to by the FSR1 register.

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INDF1 0xFE7 INDF1 is associated with using FSR1 for indirect addressing of data memory. INDF1 has the value of FSR1. It is not a physical register. See p. 50.

POSTINC1 0xFE6 POSTINC1 is associated with using FSR1 for indirect addressing of data memory. POSTINC1 is the value of FSR1 post-incremented. It is not a physical register.

POSTDEC1 0xFE5 POSTDEC1 is associated with using FSR1 for indirect addressing of data memory. POSTDEC1 is the value of FSR1 post-decremented. It is not a physical register.

PREINC1 0xFE4 PREINC1 is associated with using FSR1 for indirect addressing of data memory. PREINC1 is the value of FSR1 pre-incremented. It is not a physical register.

PLUSW1 0xFE3 PLUSW1 is associated with using FSR1 for indirect addressing of data memory. PLUSW1 is the value of FSR1 offset (increased) by the value in WREG. It is not a physical register. See p. 50.


FSR1H: High Byte (4 bits) 0xFE2

FSR1L: Low Byte (8-bits) 0xFE1

p. 50 R/W R/W Byte Names FSR1H FSR1L 0xFE2 0xFE1 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR1 = FSR1H:FSR1L register is a read or write to the data memory address pointed to by the FSR1 register.

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INDF2 0xFDF INDF2 is associated with using FSR2 for indirect addressing of data memory. INDF2 has the value of FSR2. It is not a physical register. See p. 50.

POSTINC2 0xFDE POSTINC2 is associated with using FSR2 for indirect addressing of data memory. POSTINC2 is the value of FSR2 post-incremented. It is not a physical register.

POSTDEC2 0xFDD POSTDEC2 is associated with using FSR2 for indirect addressing of data memory. POSTDEC2 is the value of FSR2 post-decremented. It is not a physical register.

PREINC2 0xFDC PREINC2 is associated with using FSR2 for indirect addressing of data memory. PREINC2 is the value of FSR2 pre-incremented. It is not a physical register.

PLUSW2 0xFDB PLUSW2 is associated with using FSR2 for indirect addressing of data memory. PLUSW2 is the value of FSR2 offset (increased) by the value in WREG. It is not a physical register. See p. 50.


FSR2H: High Byte (4 bits) 0xFDA

FSR2L: Low Byte (8-bits) 0xFD9

p. 50 R/W R/W Byte Names FSR2H FSR2L 0xFDA 0xFD9 PO/BO Reset ---- xxxx xxxx xxxx MCLR Reset ---- uuuu uuuu uuuu This register is used for indirect addressing of the data memory. A read or write to the FSR2 = FSR2H:FSR2L register is a read or write to the data memory address pointed to by the FSR2 register.

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Timer0

TMR0H: Timer0 Module High Byte Register 0xFD7

p. 105 R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names The TMR0H bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset u u u u u u u u

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TMR0L: Timer0 Module Low Byte Register 0xFD6


Bit Names The TMR0L bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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T0CON: Timer0 Module Control Register 0xFD5


Bit Names TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1 bit 7 TMR0ON: Timer0 On/Off Control bit.

1: Enables Timer0. 0: Stops Timer0.

bit 6 T08BIT: Timer0 8-bit/16-bit Control bit. 1: Timer0 is configured as an 8-bit timer/counter. 0: Timer0 is configured as a 16-bit timer/counter.

bit 5 T0CS: Timer0 Clock Source Select bit. 1: Transition on T0CKI pin. 0: Internal instruction cycle clock output (CLKO).

bit 4 T0SE: Timer0 Source Edge Select bit. 1: Increment on high-to-low transition on T0CKI pin. 0: Increment on low-to-high transition on T0CKI pin.

bit 3 PSA: Timer0 Prescaler Assignment bit. 1: TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0: Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits. This 3-bit field selects one of the eight Timer0 prescale values (input clock divisor values), between 2

and 256. See datasheet. back to Index

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Timer1

TMR1H: Holding Register for the MSB of the 16-bit Timer1 Register

0xFCF


Bit Names The TMR1H bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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TMR1L: Holding Register for the LSB of the 16-bit Timer1 Register

0xFCE



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T1CON: Timer1 Module Control Register 0xFCD

p. 107 R/W U-0 R/W R/W R/W R/W R/W R/W

Bit Names RD16 - T1CKPS1 T1CKPS0 T1OSCEN #T1SYNC TMR1CS TMR1ON bit 7 bit 0 PO/BO Reset 0 - 0 0 0 0 0 0 MCLR Reset u - u u u u u u bit 7 RD16: 16-bit Read/Write Mode Enable bit.

1: Enables register Read/Write of Timer1 in one 16-bit operation. 0: Enables register Read/Write of Timer1 in two 8-bit operations.

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits. This 2-bit field selects one of the four Timer1 prescale values (input clock divisor values), between 1

and 8. See datasheet. bit 3 T1OSCEN: Timer1 Oscillator Enable bit.

1: Timer1 Oscillator is enabled. 0: Timer1 Oscillator is shut-off.

Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 #T1SYNCH: Timer1 External Clock Input Synchronization Select bit.

Note: Negative logic. When TMR1CS = 1: 1: Do not synchronize external clock input.

0: Synchronize external clock input. When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit. 1: External clock from pin RC0/T1OSO/T1CKI (on the rising edge). 0: Internal clock (FOSC/4).

bit 0 TMR1ON: Timer1 On bit. 1: Enables Timer1. 0: Stops Timer1.

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Timer2

TMR2: Timer2 Module Register 0xFCC


Bit Names The TMR2 bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0

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PR2: Timer2 Period Register 0xFCB


Bit Names The PR2 bits are not individually named. bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1

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T2CON: Timer2 Module Control Register 0xFCA


Bit Names - TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 PO/BO Reset - 0 0 0 0 0 0 0 MCLR Reset - 0 0 0 0 0 0 0 bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits. This 2-bit field selects one of the four Timer1 postscale values (output divisor values), between 1 and

16. See datasheet. bit 2 TMR2ON: Timer2 On bit.

1: Timer2 is On. 0: Timer2 is Off.

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits. This 2-bit field selects one of the three Timer2 prescale values (input clock divisor values): 1, 4 or 16.

See datasheet. back to Index

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Timer3

TMR3H: Holding Register for the MSB of the 16-bit Timer3 Register

0xFB3


Bit Names The TMR3H bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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TMR3L: Holding Register for the LSB of the 16-bit Timer3 Register

0xFB2



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T3CON: Timer3 Module Control Register 0xFB1


Bit Names RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 #T3SYNC TMR3CS TMR3ON bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset u u u u u u u u bit 7 RD16: 16-bit Read/Write Mode Enable bit.

1: Enables register Read/Write of Timer3 in one 16-bit operation. 0: Enables register Read/Write of Timer3 in two 8-bit operations.

bit 6, 3 T3CCP2, T3CCP1: Timer3 and Timer1 to CCPx Enable bits. This 2-bit field configures the clock sources (Timer1 or Timer3) that are used as timebases for CCP1

and CCP2. See datasheet. bit 5, 4 T3CKPS1, T3CKPS0: Timer3 Input Clock Prescale Select bits. This 2-bit field selects one of the four Timer3 prescale values (input clock divisor values): 1, 2, 4 or 8.

See datasheet. bit 2 #T3SYNCH: Timer3 External Clock Input Synchronization Select bit.

Note: Not usable if the system clock comes from Timer1 or Timer3. Note: Negative logic. When TMR3CS = 1: 1: Do not synchronize external clock input.

0: Synchronize external clock input. When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit. 1: External clock input from Timer1 oscillator or T1CKI pin, on the rising edge after the first falling edge. 0: Internal clock (FOSC/4).

bit 0 TMR3ON: Timer3 On bit. 1: Enables Timer3. 0: Stops Timer3.

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Miscellaneous Control Registers

OSCCON: Oscillator Control Register 0xFD3

p. 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W Bit Names - - - - - - - SCS PO/BO Reset - - - - - - - 0 MCLR Reset - - - - - - - 0 bit 0 SCS: System Clock Switch bit.

1: Switch to Timer1 oscillator/clock pin 0: Use primary oscillator/clock input pin

Note: System Clock Switch bit is enabled only if CONFIG1H<OSCSEN> = 0 and T1CON<T1OSCEN> = 1 back to Index

LVDCON: Low Voltage Detect Control Register 0xFD2

p. 191 U-0 U-0 R R/W R/W R/W R/W R/W Bit Names - - IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 PO/BO Reset - - 0 0 0 1 0 1 MCLR Reset - - 0 0 0 1 0 1 bit 5 IVRST: Internal Reference Voltage Stable bit

1: LVD logic will generate the interrupt flag at the specified voltage range 0: LVD logic will not generate the interrupt flag – do not enable the LVD interrupt

bit 4 LVDEN: Low Voltage Detect Power Enable bit 1: Enables LVD, powers up LVD circuit 0: Disables LVD, powers down LVD circuit

bit 3-0 LVDL3:LVDL0: Low Voltage Detection Level bits This 4-bit field sets the range of voltage within which a low voltage level is detected. See datasheet.

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WDTCON: Watchdog Timer Control Register 0xFD1

p. 203 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W

Bit Names - - - - - - - SWDTEN bit 7 bit 0 PO/BO Reset - - - - - - - 0 MCLR Reset - - - - - - - 0 bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit

1: Watchdog Timer is on 0: Watchdog Timer is off if CONFIG2H<WDTEN> = 0

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RCON: Reset Control Register 0xFD0

p. 53, 28, 84 R/W U-0 U-0 R/W R/W R/W R/W R/W Bit Names IPEN - - RI TO PD POR BOR bit 7 bit 0 PO/BO Reset 0 - - 1 1 1 q q MCLR Reset 0 - - q q q u u bit 7 IPEN: Interrupt Priority Enable bit

1: Enable priority levels on interrupts 0: Disable priority levels on interrupts (PIC16CXX compatibility mode)

bit 4 RI: Not RESET Instruction Flag bit. Note: Negative logic.

1: The RESET instruction was not executed 0: The RESET instruction was executed, causing a device RESET. Set this bit in software after a

RESET occurs, so that execution of another (future) RESET instruction can be detected. bit 3 TO: Not Watchdog Time-out Flag bit.

Note: Negative logic. 1: After power-up, or by execution of the CLRWDT or SLEEP instructions. 0: A WDT time-out has occurred

bit 2 PD: Not Power-down Detection Flag bit. Note: Negative logic.

1: After power-up, or by execution of the CLRWDT instruction 0: By execution of the SLEEP instruction

bit 1 POR: Not Power-on Reset Status bit. Note: Negative logic.

1: A Power-on Reset has not occurred 0: A Power-on Reset has occurred. Set this bit in software after a POR occurs, so that another (future)

POR event can be detected. bit 0 BOR: Not Brown-out Reset Status bit.

Note: Negative logic. 1: A Brown-out Reset has not occurred 0: A Brown-out Reset has occurred. Set this bit in software after a BOR occurs, so that another (future)

BOR event can be detected. back to Index

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MSSP Module

SSPBUF: Synchronous Serial Receive/Transmit Buffer 0xFC9


Bit Names The SSBUF bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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SSPADD: MSSP Address Register 0xFC8


Bit Names The SSPADD bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 Note: Holds the slave device address when the MSSP is configured in I2C Slave mode. Note: When the MSSP is configured in I2C Master mode, the low 7 bits act as the baud rate generator reload value.

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SSPSTAT: MSSP Status Register (in SPI Mode) 0xFC7

p. 126 R/W R/W R R R R R R

Bit Names SMP CKE D/#A P S R/#W UA BF bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 SMP: Sample bit.

In SPI Master mode: 1: Input data sampled at end of data output time.

0: Input data sampled at middle of data output time. In SPI Slave mode: 1: Illegal.

0: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SMBus Select bit.

When CKP = 1: 1: Data transmitted on falling edge of SCK.

0: Data transmitted on rising edge of SCK. When CKP = 0: 1: Data transmitted on rising edge of SCK.

0: Data transmitted on falling edge of SCK. bit 5 D/#A: Data / #Address bit. Not used in SPI mode. bit 4 P: Stop bit. Not used in SPI mode. bit 3 S: Start bit. Not used in SPI mode. bit 2 R/#W: Read / #Write bit Information. Not used in SPI mode. bit 1 UA: Update Address. Not used in SPI mode. bit 0 BF: Buffer Full Status bit. (Receive mode only).

In SPI Receive mode: 1: Receive complete, SSPBUF is full.

0: Receive not complete, SSPBUF is empty.

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SSPCON1: MSSP Control Register1 (in SPI Mode) 0xFC6


Bit Names WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 WCOL: Write Collision Detect bit. (Transmit mode only)

1: The SSPBUF register was written to while it is still transmitting the previous word. Clear this bit in software after a collision occurs, so that another (future) collision can be detected.

0: No collision. bit 6 SSPOV: Receive Overflow Flag bit..

In SPI Slave mode: 1: A new byte was received while the SSPBUF register was still holding the previous data. In case of

overflow, the previous data in the SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid SSPOV being set. Clear this bit in software after an overflow occurs, so that another (future) overflow can be detected.

0: No overflow. In SPI Master mode: Note: In SPI Master mode, the overflow bit is not set since each new reception (and transmission) is

initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit.

1: Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins. 0: Disables serial port and configures these pins as I/O port pins.

bit 4 CKP: Clock Polarity Select bit. 1: IDLE state for clock is a high level. 0: IDLE state for clock is a low level.

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode bits. This 4-bit field sets the MSSP to one of the six SPI operating modes. See datasheet. Note: Only SSPCON1 is used in SPI mode – SSPCON2 is not used.

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SSPSTAT: MSSP Status Register (in I2C Mode) 0xFC7

p. 135 R/W R/W R R R R R R

Bit Names SMP CKE D/#A P S R/#W UA BF bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 SMP: Slew Rate Control bit.

In I2C Master or Slave mode: 1: Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0: Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SMBus Select bit.

In I2C Master or Slave mode: 1: Enable SMBus specific inputs

0: Disable SMBus specific inputs bit 5 D/#A: Data / #Address bit.

In I2C Master mode: Reserved. In I2C Slave mode: 1: Indicates that the last byte received or transmitted was data.

0: Indicates that the last byte received or transmitted was address. bit 4 P: Stop bit.

1: Indicates that a STOP bit has been detected last. Note: This bit is cleared on RESET and when SSPEN is cleared.

0: STOP bit was not detected last. bit 3 S: Start bit.

1: Indicates that a start bit has been detected last. Note: This bit is cleared on RESET and when SSPEN is cleared.

0: START bit was not detected last. bit 2 R/#W: Read / #Write bit Information (I2C mode only).

In I2C Slave mode: Note: The R/#W bit holds the R/#W bit information following the last address match. This bit is only valid from the address match to the next I2C START, STOP, or #ACK bit. 1: Read.

0: Write. In I2C Master Mode: Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. 1: Transmit is in progress.

0: Transmit is not in progress. bit 1 UA: Update Address (10-bit Slave mode only).

1: Indicates that the user needs to update the address in the SSPADD register. 0: Address does not need to be updated.

bit 0 BF: Buffer Full Status bit. In I2C Transmit mode: 1: Receive complete, SSPBUF is full.

0: Receive not complete, SSPBUF is empty. In I2C Receive mode: 1: Data transmit in progress (does not include the I2C #ACK and STOP bits), SSPBUF is full

0: Data transmit complete (does not include the I2C #ACK and STOP bits), SSPBUF is empty.

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SSPCON1: MSSP Control Register1 (in I2C Mode) 0xFC6


Bit Names WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 WCOL: Write Collision Detect bit.

In I2C Master Transmit mode: 1: A write to the SSPBUF register was attempted while the I2C conditions were not valid for a

transmission to be started. Clear this bit in software after a collision occurs, so that another (future) collision can be detected.

0: No collision. In I2C Slave Transmit mode: 1: The SSPBUF register was written to while it was still transmitting the previous word. Clear this bit in

software after a collision occurs, so that another (future) collision can be detected.

0: No collision. In I2C Receive mode (Master or Slave modes): This is a “don’t care” bit in I2C Receive mode.

bit 6 SSPOV: Receive Overflow Flag bit. In I2C Receive mode: 1: A byte is received while the SSPBUF register is still holding the previous byte. Clear this bit in software

after an overflow occurs, so that another (future) overflow can be detected.

0: No overflow. In I2C Transmit mode: This is a “don’t care” bit in I2C Transmit mode.

bit 5 SSPEN: Synchronous Serial Port Enable bit. 1: Enables the serial port and configures the SDA and SCL pins as the serial port pins.

Note: When enabled, the SDA and SCL pins must be properly configured as input or output.

0: Disables serial port and configures these pins as I/O port pins. bit 4 CKP: SCK Release Control bit.

In I2C Slave mode: 1: Release clock.

0: Holds clock low (clock stretch), used to ensure data setup time. In I2C Master mode: This is a “don’t care” bit in I2C Master mode.

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode bits. This 4-bit field sets the MSSP to one of the six I2C operating modes. See datasheet.

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SSPCON2: MSSP Control Register2 (I2C Mode only) 0xFC5


Bit Names GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 bit 7 GCEN: General Call Enable bit (Slave mode only)

1: Enable interrupt when a general call address (0000h) is received in the SSPSR. 0: General call address disabled.

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only). 1: Acknowledge was not received from slave. 0: Acknowledge was received from slave.

bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only). 1: Not Acknowledge. 0: Acknowledge.

bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only). 1: Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0: Acknowledge sequence IDLE. bit 3 RCEN: Receive Enable bit (Master mode only).

1: Enables Receive mode for I2C. 0: Receive IDLE.

bit 2 PEN: STOP Condition Enable bit (Master mode only). 1: Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0: STOP condition IDLE.

bit 1 RSEN: Internal Reference Voltage Stable bit 1: Initiate Repeated START condition on SDA and SCL pins.

Automatically cleared by hardware.

0: Repeated START condition IDLE. bit 0 SEN: Write Collision Detect bit.

In I2C Master mode: 1: Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.

0: START condition IDLE. In I2C Master mode: 1: Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled).

0: Clock stretching is enabled for slave transmit only. (Legacy mode). Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Note: SSPCON2 is not used in SPI mode.

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A/D Module

ADRESH: A/D Result High Register 0xFC4

p. 187 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The ADRESH bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u The ADRESH and ADRESL registers contain the result of the A/D conversion. See datasheet.

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ADRESL: A/D Result Low Register 0xFC3

p. 187 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The ADRESL bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u The ADRESH and ADRESL registers contain the result of the A/D conversion. See datasheet.

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ADCON0: A/D Control Register 0 0xFC2

p. 187 et seq. R/W R/W R/W R/W R/W R/W U-0 R/W Bit Names ADCS1 ADCS0 CHS2 CHS1 CHS0 GO - ADON bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 - 0 MCLR Reset 0 0 0 0 0 0 - 0 bit 6-7 ADCS1:ADCS0: A/D Conversion Clock Select bits. A 3-bit field sets the A/D conversion clock frequency. Bit 2 is ADCON1<ACDS2>.See datasheet. bit 3-5 CHS2:CHS0: Analog Channel Select bits This 3-bit field selects the analog channel. Note: do not select any unimplemented channel. bit 2 GO/#DONE: A/D Conversion Status bit. Note: this bit is active only when ADON = 1. 1: A/D conversion in progress. Setting this bit initiates an A/D conversion; bit is cleared in hardware when

conversion completes. 0: A/D conversion not in progress. bit 0 ADON: A/D On bit 1: A/D converter module is powered-up. 0: A/D converter module is disabled, and consumes no power.

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31 of 48

ADCON1: A/D Control Register 1 0xFC1

p. 187 et seq. R/W R/W U-0 U-0 R/W R/W R/W R/W Bit Names ADFM ADCS2 - - PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 PO/BO Reset 0 0 - - 0 0 0 0 MCLR Reset 0 0 - - 0 0 0 0 bit 7 ADFM: A/D Result Format Select bit

1: Right-justified. The 10-bit A/D result is right-justified in ADRESH:ADRESL 0: Left-justified. The 10-bit A/D result is left-justified in ADRESH:ADRESL

bit 6 ADCS2: A/D Conversion Clock Select bit. A 3-bit field sets the A/D conversion clock frequency. Bits 0-1 are ADCON0<ACDS1:ADCS0>. bit 0-3 PCFG3:PCFG0: A/D Port Configuration Control bits. This 4-bit field configures various combinations of the PORTA bits as analog inputs or digital I/Os. The

analog reference voltage is also configured. See datasheet. back to Index

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Capture/Compare/PWM Module 1 (CCP1)

CCPR1H: Capture/Compare/PWM Register1 High 0xFBF

p. 121 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The CCPR1H bits are not individually named.

bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u This register is the high byte of the 16-bit CCPR1 register.

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CCPR1L: Capture/Compare/PWM Register1 Low 0xFBE

p. 121 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The CCPR1L bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u This register is the low byte of the 16-bit CCPR1 register.

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CCP1CON: CCP1 Control Register 0xFBD

p. 117 et seq. U-0 U-0 R/W R/W R/W R/W R/W R/W Bit Names - - DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 PO/BO Reset - - 0 0 0 0 0 0 MCLR Reset - - 0 0 0 0 0 0 bit 4-5 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0

Capture Mode: Unused in this mode Compare Mode: Unused in this mode PWM Mode: Bit 1 and bit 0 of the 10-bit PWM duty cycle. The upper eight bits (DC1B9:DC1B2) are in CCPR1L.

bit 0-3 CCP1M3:CCP1M0: CCP1 Mode Select bits This 4-bit field configures the CCP1 mode – disabled, various compare modes, various capture

modes, and PWM mode. See datasheet. back to Index

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Capture/Compare/PWM Module 2 (CCP2)

CCPR2H: Capture/Compare/PWM Register2 High 0xFBC

p. 121 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The CCPR2H bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u This register is the high byte of the 16-bit CCPR2 register.

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CCPR2L: Capture/Compare/PWM Register2 Low 0xFBB

p. 121 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The CCPR2L bits are not individually named. bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u This register is the low byte of the 16-bit CCPR2 register.

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CCP2CON: CCP2 Control Register 0xFBA

p. 117 et seq. U-0 U-0 R/W R/W R/W R/W R/W R/W Bit Names - - DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 PO/BO Reset - - 0 0 0 0 0 0 MCLR Reset - - 0 0 0 0 0 0 bit 4-5 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0

Capture Mode: Unused in this mode Compare Mode: Unused in this mode PWM Mode: Bit 1 and bit 0 of the 10-bit PWM duty cycle. The upper eight bits (DC2B9:DC2B2) are in CCPR2L.

bit 0-3 CCP2M3:CCP2M0: CCP2 Mode Select bits This 4-bit field configures the CCP2 mode – disabled, various compare modes, various capture

modes, and PWM mode. See datasheet. back to Index

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Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

SPBRG: USART Baud Rate Generator Register 0xFAF


Bit Names The SPBRG bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 Note: The SPBRG register controls the period of a free running 8-bit timer. See Datasheet Tables 16-3, 16-4.

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RCREG: USART Receive Data Register 0xFAE

p. 175, 178, 180. R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names The RCREG bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0

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TXREG: USART Transmit Data Register 0xFAD

p. 173, 176, 179. R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names The TXREG bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0

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TXSTA: USART Transmit Status and Control Register 0xFAC

p. 166 R/W R/W R/W R/W U-0 R/W R R/W

Bit Names CSRC TX9 TXEN SYNC - BRGH TRMT TX9D bit 7 bit 0 PO/BO Reset 0 0 0 0 - 0 1 0 MCLR Reset 0 0 0 0 - 0 1 0 bit 7 CSRC: Clock Source Select bit.

Asynchronous mode: Don’t care. Synchronous mode: 1: Master mode (clock generated internally from BRG).

0: Slave mode (clock from external source). bit 6 TX9: 9-bit Transmit Enable bit.

1: Selects 9-bit transmission. 0: Selects 8-bit transmission.

bit 5 TXEN: Transmit Enable bit. 1: Transmission enabled. 0: Transmission disabled.

bit 4 SYNC: USART Mode Select bit. 1: Synchronous mode. 0: Asynchronous mode.

bit 2 BRGH: High Baud Rate Select bit. Asynchronous mode: 1: High speed.

0: Low speed. Synchronous mode: Not used in this mode.

bit 1 TRMT: Transmit Shift Register Status bit. 1: TSR Empty. 0: TSR Full.

bit 0 TX9D: 9th bit of Transmit Data. When TX9 = 1. User defined – Can be a parity bit or an address/data bit.

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RCSTA: USART Receive Status and Control Register 0xFAB

p. 167 R/W R/W R/W R/W R/W R R R

Bit Names SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 x MCLR Reset 0 0 0 0 0 0 0 x bit 7 SPEN: Serial Port Enable bit.

1: Serial port enabled – configures RX/DT and TX/CK pins as serial port pins. 0: Serial port disabled.

bit 6 RX9: 9-bit Receive Enable bit. 1: Selects 9-bit reception. 0: Selects 8-bit reception.

bit 5 SREN: Single Receive Enable bit. Asynchronous mode: Not used in this mode. Synchronous mode: 1: Enables single receive.

Note: This bit is cleared automatically after reception is complete.

0: Disables single receive. bit 4 CREN: Continuous Receive Enable bit.

Asynchronous mode: 1: Enables receiver.

0: Disables receiver. Synchronous mode: 1: Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0: Disables continuous receive. bit 3 ADDEN: Address Detect Enable bit.

Asynchronous mode, 9-bit (RX9 = 1): 1: Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set.

0: Disables address detection, all bytes are received, and ninth bit can be used as parity bit. bit 2 FERR: Framing Error bit.

1: Framing error (can be updated by reading RCREG register and receive next valid byte). 0: No framing error.

bit 1 OERR: Overrun Error bit. 1: Overrun error (can be cleared by clearing bit CREN). 0: No overrun error.

bit 0 RX9D: 9th bit of Received Data. When RX9 = 1. User defined – Can be a parity bit or an address/data bit.

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EEPROM

EEADR: Data EEPROM Address Register 0xFA9

p. 65, 69 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The EEADR bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 This register holds the 8-bit data EEPROM address to be read from or written to.

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EEDATA: Data EEPROM Data Register 0xFA8

p. 69 R/W R/W R/W R/W R/W R/W R/W R/W Bit Names The EEDATA bits are not individually named. bit 7 bit 0 PO/BO Reset 0 0 0 0 0 0 0 0 MCLR Reset 0 0 0 0 0 0 0 0 This register holds the 8-bit data that has been read from, or is to be written to, the data EEPROM address EEADR.

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EECON1: EEPROM Control Register 1 0xFA6

p. 66 R/W R/W U-0 R/W R/W R/W R/W R/W

Bit Names EEPGD CFGS - FREE WRERR WREN WR RD bit 7 bit 0 PO/BO Reset x x - 0 x 0 0 0 MCLR Reset u u - 0 u 0 0 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit.

1: Access program FLASH memory. 0: Access data EEPROM memory.

bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit. 1: Access Configuration or Calibration Registers 0: Access Program FLASH or Data EEPROM memory

bit 4 FREE: FLASH Row Erase Enable bit. 1: Erase the program memory row addressed by TBLPTR on the next WR command. This bit is cleared

on completion of the row erase.

0: Perform write only. bit 3 WRERR: EEPROM Write Error Flag bit.

1: A write operation terminated prematurely. (A MCLR or WDT Reset occurred during self-timed programming in normal operation.)

0: The write operation completed. bit 2 WREN: EEPROM Write Enable bit.

1: Allows write cycles. 0: Inhibits write to the EEPROM.

bit 1 WR: Write Control bit. 1: Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The

operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.)

0: Write cycle is complete. bit 0 RD: Read Control bit.

1: Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0: Does not initiate an EEPROM read cycle. back to Index

EECON2: EEPROM Control Register 2 0xFA7

p. 65, 69 R-0/W R-0/W R-0/W R-0/W R-0/W R-0/W R-0/W R-0/W

Bit Names - - - - - - - -

bit 7 bit 0 Reset - (EECON2 is not a physical register) Note: EECON2 is not a physical register. It is used only during a EEPROM write, when a required sequence must be written to EECON2. See p. 67.

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I/O Ports PORTA: 7-bit Bi-directional Port 0xF80

p. 87 et seq. U-0 R/W R/W R/W R/W R/W R/W R/W

Bit (Pin) Name - RA6 RA5 RA4 RA3 RA2 RA1 RA0 - OSC2 AN4 - AN3 AN2 AN1 AN0 - CLKO SS TOCKI VREFP VREFM - - - - LVDIN - - - - - bit 7 bit 0 PO/BO Reset - x 0 x 0 0 0 0 MCLR Reset - u 0 u 0 0 0 0 RA6: TTL level input/CMOS output pin 6.

OSC2: Oscillator crystal output (in Crystal Oscillator clock mode only). pin 6 (bit 6)

CLKO: Clock output at ¼ the frequency of OSC1 (in RC clock mode only). RA5: TTL level input/CMOS output pin 5. AN5: Analog input channel 5. SS: SPI slave select Schmitt trigger digital input. Note: Negative logic.

pin 5 (bit 5)

LVDIN: Low voltage detect analog input. RA4: Schmitt trigger digital input (CMOS levels) or open drain output pin 4. pin 4

(bit 4) TOCKI: External TTL clock input for Timer0. RA3: TTL level input/CMOS output pin 3. AN3: Analog input channel 3 pin 3

(bit 3) VREFP: A/D analog reference voltage (high) input. RA2: TTL level input/CMOS output pin 2. AN2: Analog input channel 2 pin 2

(bit 2) VREFM: A/D analog reference voltage (low) input. RA1: TTL level input/CMOS output pin 1. pin 1

(bit 1) AN1: Analog input channel 1. RA0: TTL level input/CMOS output pin 0. pin 0

(bit 0) AN0: Analog input channel 0. Note: All input pins have TTL input buffers except for pin 4 which has a Schmitt trigger input buffer. Note: Output pin 4 is open-drain. Note: I/O pins have diode protection to VDD and VSS.

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LATA: Data Output Latch Register, PORTA 0xF89

p. 87 et seq. U-0 R/W R/W R/W R/W R/W R/W R/W Bit Names - LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 PO/BO Reset - x x x x x x x MCLR Reset - u u u u u u u

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TRISA: Data Direction Register, PORTA 0xF92

p. 87 et seq. U-0 R/W R/W R/W R/W R/W R/W R/W Bit Names - TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 PO/BO Reset - 1 1 1 1 1 1 1 MCLR Reset - 1 1 1 1 1 1 1 any bit TRISAn: RAn Direction Control bit, n ∊ [0-6].

1: Set this bit as an input (includes bits used as A/D inputs). 0: Set this bit as an output.

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PORTB: 8-bit Bi-directional Port 0xF81

p. 90 et seq. R/W R/W R/W R/W R/W R/W R/W R/W

Bit (Pin) Name RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

PGD PGC PGM - INT3 INT2 INT1 INT0

- - - - CCP2 - - -

bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u RB7: TTL level input/CMOS output pin (with interrupt-on-change). TTL level input/CMOS output pin 1. pin 7 (bit 7) PGD: Serial programming data input, with Schmitt trigger.

RB6: TTL level input/CMOS output pin (with interrupt-on-change). pin 6 (bit 6) PGC: Serial programming clock input, with Schmitt trigger.

RB5: TTL level input/CMOS output pin (with interrupt-on-change). pin 5 (bit 5) PGM: Low-voltage in-circuit serial programming enable input, with Schmitt trigger. pin 4 (bit 4) RB4: TTL level input/CMOS output pin (with interrupt-on-change).

RB3: TTL level input/CMOS output pin. INT3: External interrupt 3, with Schmitt trigger input. pin 3

(bit 3) CCP2: CCP2 input/output when CONFIG3H<CCP2MX> = 1 RB2: TTL level input/CMOS output pin. pin 2

(bit 2) INT2: External interrupt 2, with Schmitt trigger input. RB1: TTL level input/CMOS output pin. pin 1

(bit 1) INT1: External interrupt 1, with Schmitt trigger input. RB0: TTL level input/CMOS output pin. pin 0

(bit 0) INT0: External interrupt 0, with Schmitt trigger input. Note: All pins have an internal software programmable weak pull-up. Note: All input/output pins have TTL buffers, except when configured as special-purpose inputs, when they have Schmitt trigger input buffers as noted above. Note: All I/O pins have diode protection to VDD and VSS.

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40 of 48

TRISB: Data Direction Register, PORTB 0xF93

p. 90 et seq. U-0 R/W R/W R/W R/W R/W R/W R/W Bit Names TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1 any bit TRISBn: RBn Direction Control bit, n ∊ [0-7].

1: Set this bit as an input. 0: Set this bit as an output.

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LATB: Data Output Latch Register, PORTB 0xF8A

p. 90 et seq. R/W R/W R/W R/W R/W R/W R/W R/W Bit Names LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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PORTC: 8-bit Bi-directional Port 0xF82


Bit Names RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RX TX SDO SDI SCK - T1OSI T1OSO DT CK - SDA SCL CCP1 CCP2 T1CKI bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u RC7: TTL level input/CMOS output port pin 7.

RX: USART asynchronous receive. pin 7 (bit 7)

DT: USART synchronous data. RC6: TTL level input/CMOS output port pin 6. TX: USART asynchronous transmit. pin 6

(bit 6) CK: USART synchronous clock. RC5: TTL level input/CMOS output port pin 5. pin 5

(bit 5) SDO: Synchronous serial port data output. RC4: TTL level input/CMOS output port pin 4. SDI: Synchronous serial data input, SPI mode. pin 4

(bit 4) SDA: Synchronous serial data I/O, I2C mode. RC3: TTL level input/CMOS output port pin 3. SCK: Synchronous serial clock, SPI mode. pin 3

(bit 3) SCL: Synchronous serial clock, I2C mode. RC2: TTL level input/CMOS output port pin 2. pin 2

(bit 2) CCP1: CCP1 input/output. RC1: TTL level input/CMOS output port pin 1. T1OSI: Timer1 oscillator input. pin 1

(bit 1) CCP2: CCP2 input/output when CONFIG3H<CCP2MX> = 0 RC0: TTL level input/CMOS output port pin 0. T1OSO: Timer1 oscillator output. pin 0

(bit 0) T1CKI: Timer1 clock input.

Note: All input pins have a Schmitt trigger input buffer. Note: I/O pins have diode protection to VDD and VSS.

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LATC: Data Output Latch Register, PORTC 0xF8B


Bit Names LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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TRISC: Data Direction Register, PORTC 0xF94


Bit Names TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1 any bit TRISCn: RCn Direction Control bit, n ∊ [0-7].


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PORTD: 8-bit Bi-directional Port 0xF83


Bit Names RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0

bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u RD7: TTL level input/CMOS output port pin 7. pin 7 (bit 7) PSP7: Parallel slave port bit 7.

RD6: TTL level input/CMOS output port pin 6. pin 6 (bit 6) PSP6: Parallel slave port bit 6.






RD0: TTL level input/CMOS output port pin 0. pin 0 (bit 0) PSP0: Parallel slave port bit 0. Note: Input buffers are Schmitt trigger when in I/O port mode, but TTL in PSP mode.. Note: I/O pins have diode protection to VDD and VSS.

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LATD: Data Output Latch Register, PortD 0xF8C


Bit Names LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

bit 7 bit 0 PO/BO Reset x x x x x x x x MCLR Reset u u u u u u u u

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TRISD: Data Direction Register, PortD 0xF95

R/W R/W R/W R/W R/W R/W R/W R/W

Bit Names TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

p. 95 et seq. bit 7 bit 0 PO/BO Reset 1 1 1 1 1 1 1 1 MCLR Reset 1 1 1 1 1 1 1 1 any bit TRISDn: RDn Direction Control bit, n ∊ [0-7].


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PORTE: 3-bit Bi-directional Port 0xF84

p. 99 et seq. U-0 U-0 U-0 U-0 U-0 R/W R/W R/W

Bit Names - - - - - RE2 RE1 RE0

- - - - - #CS #WR #RD

- - - - - AN7 AN6 AN5

bit 7 bit 0 PO/BO Reset - - - - - 0 0 0 MCLR Reset - - - - - 0 0 0 RE2: TTL level input/CMOS output port pin.

#CS: Chip select control input in PSP mode. Note: Negative logic. 1: Device is not selected. 0: Device is selected.

pin 2 (bit 2)

AN7: Analog input. RE1: TTL level input/CMOS output port pin. #WR: Write control input in PSP mode. Note: Negative logic.

1: Not a write operation. 0: Write operation. Writes to PORTD register if device is selected.

pin 1 (bit 1)

AN7: Analog input. RE0: TTL level input/CMOS output port pin. #RD: Read control input in PSP mode. Note: Negative logic.

1: Not a read operation. 0: Read operation. Reads from PORTD register if device is selected.

pin 0 (bit 0)

AN7: Analog input. Note: Input buffers are Schmitt trigger. Note: I/O pins have diode protection to VDD and VSS.

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LATE: Data Output Latch Register, PORTE 0xF8D

p. 99 et seq. U-0 U-0 U-0 U-0 U-0 R/W R/W R/W

Bit Names - - - - - LATE2 LATE1 LATE0

bit 7 bit 0 PO/BO Reset - - - - - x x x MCLR Reset - - - - - u u u

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TRISE: Data Direction Register, PORTE 0xF96

p. 99 R R R/W R/W U-0 R/W R/W R/W

Bit Names IBF OBF IBOV PSPMODE - TRISE2 TRISE1 TRISE0

bit 7 bit 0 PO/BO Reset 0 0 0 0 - 1 1 1 MCLR Reset 0 0 0 0 - 1 1 1 bit 7 IBF: Input buffer full status bit.

1: A word has been received and is waiting to be read. 0: No word has been received.

bit 6 OBF: Output buffer full status bit. 1: The output buffer still holds a previously written word. 0: The output buffer has been read.

bit 5 IBOV: Input buffer overflow detect bit. 1: A write occurred before a previously received word had been read. Clear this bit in software after an

overflow occurs, so that another (future) overflow can be detected.

0: No overflow occurred.. bit 4 PSPMODE: Parallel Slave Port Mode Select bit.

1: Parallel Slave Port mode. 0: General purpose I/O mode.

bit 2 TRISE2: RE2 Direction Control bit. 1: Set this bit as an input. 0: Set this bit as an output.



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Configuration and Device ID Registers This section provides a concise summary of the PIC18FXX2 configuration registers, arranged in approximate numerical order of address, from 0x300001 to 0x30000D. The Device ID registers are at addresses 0x3FFFFE` and 0x3FFFFF.

Table 4: Configuration and Device ID Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value

0x300001 CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111

0x300002 CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111

0x300003 CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111

0x300005 CONFIG3H — — — — — — — CCP2MX ---- ---1

0x300006 CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1

0x300008 CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111

0x300009 CONFIG5H CPD CPB — — — — — — 11-- ----

0x30000A CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111

0x30000B CONFIG6H WRTD WRTB WRTC — — — — — 111- ----

0x30000C CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111

0x30000D CONFIG7H — EBTRB — — — — — — -1-- ----

0x3FFFFE DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

0x3FFFFF DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0100

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CONFIG0H: Configuration Register 1 High 0x300001

p. 196 U-0 U-0 R/P U-0 U-0 R/P R/P R/P Bit Names - - #OSCSEN - - FOSC2 FOSC1 FOSC0 bit 7 bit 0 PO/BO Reset - - 1 - - 1 1 1 MCLR Reset - - ? - - ? ? ? bit 5 #OSCEN: Oscillator System Clock Switch Enable bit

1: Oscillator system clock switch option is disabled (main oscillator is source). 0: Oscillator system clock switch option is enabled (oscillator switching is enabled).

bit 2-0 FOSC2:FOSC0: Oscillator Selection bits. This 3-bit field configures the oscillator mode. See datasheet.

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CONFIG2L: Configuration Register 2 Low 0x300002

p. 197 U-0 U-0 R/P U-0 R/P R/P R/P R/P Bit Names - - - - BORV1 BORV0 BOREN #PWRTEN bit 7 bit 0 PO/BO Reset - - - - 1 1 1 1 MCLR Reset - - - - ? ? ? ? bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits. This 2-bit field sets the value of VDD at which a brown-out reset (BOR) may occur – See datasheet. bit 1 BOREN: Brown-out Reset Enable bit

1: Brown-out Reset enabled. 0: Brown-out Reset disabled.

bit 0 #PWRTEN: Power-up Timer Enable bit. Note: negative logic. 1: PWRT disabled. 0: PWRT enabled.

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p. 197 U-0 U-0 R/P U-0 R/P R/P R/P R/P Bit Names - - - - WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 PO/BO Reset - - - - 1 1 1 1 MCLR Reset - - - - ? ? ? ? bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits This 3-bit field sets the value of VDD at which a brown-out reset (BOR) may occur – See datasheet. bit 0 WDTEN: Watchdog Timer Enable bit

1: WDT enabled. 0: WDT disabled (control is given to the SWDTEN bit)

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p. 198 U-0 U-0 R/P U-0 U-0 R/P R/P R/P Bit Names - - - - - - - - bit 7 bit 0 PO/BO Reset - - - - - - - - MCLR Reset - - - - - - - - bit 0 CCP2MX: CCP2 Multiplex (Mux)bit System Clock Switch Enable bit

1: CCP2 input/output is multiplexed with PORTC<1> 0: CCP2 input/output is multiplexed with PORTB<1>

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CONFIG5L: Configuration Register 5 Low 0x300008

p. 199 U-0 U-0 U-0 U-0 R/C R/C R/C R/C Bit Names - - - - CP3 CP2 CP1 CP0 bit 7 bit 0 PO/BO Reset - - - - 1 1 1 1 MCLR Reset - - - - ? ? ? ? bit 3 CP3: Code Protection bit

1: Block 3 (006000-007FFFh) not code protected 0: Block 3 (006000-007FFFh) code protected

bit 2 CP2: Code Protection bit 1: Block 2 (004000-005FFFh) not code protected 0: Block 2 (004000-005FFFh) code protected



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p. 199 R/C R/C U-0 U-0 U-0 U-0 U-0 U-0 Bit Names CPD CPB - - - - - - bit 7 bit 0 PO/BO Reset 1 1 - - - - - - MCLR Reset ? ? - - - - - - bit 7 CPD: Data EEPROM Code Protection bit

1: Data EEPROM not code protected. 0: Data EEPROM code protected.

bit 6 CPB: Boot Block Code Protection bit 1: Boot Block (000000-0001FFh) not code protected. 0: Boot Block (000000-0001FFh) code protected.

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CONFIG6L: Configuration Register 6 Low 0x30000A

p. 199 U-0 U-0 U-0 U-0 R/C R/C R/C R/C Bit Names - - - - WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 PO/BO Reset - - - - 1 1 1 1 MCLR Reset - - - - ? ? ? ? bit 3 WRP3: Write Protection bit

1: Block 3 (006000-007FFFh) not write protected 0: Block 3 (006000-007FFFh) write protected

bit 2 WRP2: Write Protection bit 1: Block 2 (004000-005FFFh) not write protected 0: Block 2 (004000-005FFFh) write protected



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CONFIG6H: Configuration Register 6 High 0x30000B

p. 200 R/C R/C R U-0 U-0 U-0 U-0 U-0 Bit Names WRTD WRTB WRTC - - - - - bit 7 bit 0 PO/BO Reset 1 1 1 - - - - - MCLR Reset ? ? - - - - - - bit 7 WRTD: Data EEPROM Write Protection bit

1: Data EEPROM not write protected. 0: Data EEPROM write protected.

bit 6 WRT: Boot Block Write Protection bit 1: Boot Block (000000-0001FFh) not write protected. 0: Boot Block (000000-0001FFh) write protected.

bit 6 WRTC: Configuration Register Write Protection bit 1: Configuration Registers (300000-3000FFh) not write protected. 0: Configuration Registers (300000-3000FFh) write protected.

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CONFIG7L: Configuration Register 7 Low 0x30000C

p. 201 U-0 U-0 U-0 U-0 R/P R/P R/P R/P Bit Names - - - - EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 PO/BO Reset - - - - 1 1 1 1 MCLR Reset - - - - ? ? ? ? bit 3 EBTR3: Table Read Protection bit

1: Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks. 0: Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks.

bit 2 EBTR2: Table Read Protection bit 1: Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks. 0: Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks.



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CONFIG7H: Configuration Register 7 High 0x30000D

p. 201 U-0 R/P U-0 U-0 U-0 U-0 U-0 U-0 Bit Names - EBTRB - - - - - - bit 7 bit 0 PO/BO Reset - 1 - - - - - - MCLR Reset - ? - - - - - - bit 6 EBTR0: Boot Block Table Read Protection bit.

1: Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks. 0: Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks.

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DEVID1: Device ID Register 1 0x3FFFFE

p. 202 R R R R R R R R Bit Names DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits. These 3 bits are used with DEVID2<DEV10:DEV3> to identify the device part number. bit 4-0 REV4:REV0: Revision ID bits. This 5-bit field is used to identify the device revision.

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DEVID2: Device ID Register 2 0x3FFFFF

p. 202 R R R R R R R R Bit Names DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits. These 7 bits are used with DEVID1<DEV2:DEV0> to identify the device part number.

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