philips l05hdtm training manual
TRANSCRIPT
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PHILIPS TECHNICAL TRAINING
L05HD TRAINING MANUAL
PHILIPS CONSUMER ELECTRONICS64 PERIMETER CENTER EASTPO BOX 467300ATLANTA, GA 31146-7300
MM032205
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TABLE OF CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
AUXILIARY POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MAIN POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DEFLECTION SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
TV SIGNAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DEFLECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
VIDEO SIGNAL FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CRT DRIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SIDE JACK PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TROUBLESHOOTING TO PANEL LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
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Introduction
The L05HD TV chassis is designed for the model year 2005. This set is High Definition readywith an NTSC tuning system. To receive the ATSC channels a set top box is required.
This design is used in large screen sizes of 27 and 30 inch with the 27-inch having a 4:3aspect ration and the 30 inch version having a 16:9 aspect ratio. There are three types ofCRTs used which are the 100 degrees, 110 degrees, and wide screen version.
The standard architecture consists of a Main panel (called the family board), a Picture Tubepanel, a Side I/O panel, a HDMI panel, a HD panel, and a Top Control panel. The panelsconsists primarily of conventional components with some surface mounted devices.
The functions for 1fH video and audio processing is performed in one IC (TDA1200xx, IC7200), the Hercules chip. This chip is located on the solder side of the main panel.
The functions for the HD signals and 1fH to 2fH conversion is performed on the HD panel.Except for switching, OSD, Closed Caption, Text, and A/D conversion, the bulk of the pro-
cessing is performed by the Trident chip, IC 7201.
The L05HD chassis has two signal processing sections, one for the 1fH (NTSC), and one for2fH (HD) processing. Whatever signal is applied to the set, it is displayed on the CRT in a1080i format.
The NTSC tuning system features 181 channels with on-screen display. The main tuningsystem uses a tuner, a microcomputer, and a memory IC mounted on the main panel. Themicrocomputer communicates with the memory IC, Remote Receiver, Tuner, Signal process-ing IC, and HD processing section. The Memory IC retains the settings for favorite stations,customer-preferred settings, and circuit settings. The circuit settings can be accessed by theservice technician via the Service Alignment mode.
The On-screen graphics and Closed Caption decoding are done within IC 7206 located onthe HD panel. They are added to the main signal in the Display Processor, 7221, located onthe HD panel.
Customer Operation
The L05 customer menu is similar to the L04 customer menu. The L05HD does not havePicture-in-Picture.
Press the Menu button to make a selection. Press the Cursor up-down buttons on theremote to highlight the desired selection. Press the right Cursor button to make the selection.
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Press the Menu button on the remote and press the Cursor up-down button to obtain thefollowing screens.
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VOL
1
3
5
67
24
MainPictureSoundFeaturesInstall
TimerRotationAutoLockActive ControlDigi. Pic. Demo
FeaturesTimerStart TimeStop TimeChannelActivateDisplay
Access Code- - - -
AutoLockBlock ChannelSetup CodeClear AllBlock AllMovie RatingTV Rating
Of fStop T imeChannelActivateDisplay
Access CodeXXXXIncorrect
New Code- - - -
Confirm CodeXXXX
TimerRotationAutoLockActive ControlDigi. Pic. Demo
Access CodeXXXX
FeaturesT imer
RotationAutoLockActive ControlDigi. Pic. Demo
FeaturesT imer
RotationAutoLockActive ControlDigi. Pic. Demo
FeaturesT imer
RotationAutoLockActive ControlDigi. Pic. Demo
FeaturesT imer
RotationAutoLockActive ControlDigi. Pic. Demo
FeaturesTimerRotationAutoLockActive ControlDigi. Pic. Demo
24
Setting up the access code.
1. Press the Menu button on the remoteto display the on-screen menu.
2. Press the Cursor up or down buttonsuntil the word features are highlighted.
3. Press the Cursor right button to displaythe features menu options.
4. Press the Cursor up or down buttonsuntil the words autolock are highlighted.
5. Press the Cursor right button. Thescreen will read, Access Code ----
6. Using the number buttons, enter 0, 7,
1, 1. XXXX will appear as you pressthe buttons.
Incorrect code will appear on the screen.Enter 0711 again.
7. The screen will ask you to enter a newcode. Enter any 4 digit code.
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Power Supply Block (Figure 1)
The Power supplies are both located on the Family board. The supplies are divided into twosections, the Auxiliary and Main section. A single filter and rectifier circuit supplies bothsections. The Auxiliary supply operates in a low power mode when the load is reduced. Inthe standby mode, the 3.3 and 6 volt supplies are operating. The 3.3 volt supply providespower to the processor section of the Hercules. The 6 volt supply provides power to the IRreceiver. The Main supply is switched Off via the Standby line.
When the set is turned On, the "B" line from the Hercules processor goes High switching7547 which turns 7535, 7509, and 7545 On. The +3V3A, +6VA, +12VA, and +8VA suppliesare then switched On. The load placed on the Aux Power supply will cause it to switch to thefull power mode. At the same time, the STBY line switches Low turning the Main SMPSsupply On. The supply produces a +6 volt, +140 volt, -16 volt, and +16 volt supplies.
The +Vaudio (+16 volt) supply switches on the degauss relay.
FIGURE 1 - POWER SUPPLY BLOCKPage 4
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Auxiliary Power Supply (Figure 2)
IC 7510 is the heart of the Auxiliary Power supply. In the Standby mode, VIA the currentsensing and Control circuits, a low power condition is detected by the IC. The IC then goesinto a Burst Mode operation to reduce the power used by the circuit. In the Burst Mode, thesupply will operate at approximately 25 kHz. In full power operation the frequency will beapproximately 66 kHz.
When power is first applied to the set, Start up is supplied to the IC by the internal Start-Upcurrent through Pin 14. Startup voltage is also applied to the IC to Pin 2 by the AC_IN linewhich is tied to the neutral side of the AC line. During normal operation, power is supplied tothe IC by the HOT windings, Pins 1 and 2, of transformer 5504. Output drive from Pin 11 isapplied to the Gate of Transistor 7525. Voltage developed across the current sensing resis-tors in the Source of 7525 provides current sense information to the IC. When 7525 isswitched Off, the voltage on Pin 1 of 5504 goes High. This winding supplies the operatingvoltage the power supply circuit. It also turns Transistor 7567 On causing the Gate of 7525 tostay Low as long as Pin 1 of 5504 is High. This prevents 7525 from turning On until the fieldof 5504 has collapsed.
Regulation is accomplished by monitoring the +3 volt supply. This voltage is fed to Shuntregulator 7542 which controls the current through opto-isolator 7516. Shunt Regulator 7542begins conducting when Pin 3 of the IC reaches 2.5 volts. At this point current flows throughthe opto-isolator, 7516. The transistor inside 7516 turns On applying a control voltage to Pin6 of 7510. If a problem should develop in the feedback circuit causing an excessive voltageon Pin 6, Transistor 7549-2 will turn On, switching Transistor 7532 On. This will a voltage tothe Demag circuit on Pin 7 causing the IC to latch Off. The IC will stay latched until power isremoved and reapplied to the set.
In the Standby mode, the "B" control line from the Hercules Processor is Low. Only the +3,+3V3, and +6 volt supplies are present. When the set is turned On, the "B" line will go High,turning Transistors 7509, 7545, and 7535 On. This will switch On the +8VA, +12VA, +8V,+3V3A, +6VA, and +5V supplies.
In normal operation, voltage from Pin 12 of 5504 is rectified by 6540 to produce a negativevoltage which prevents Transistor 7561 from turning On. If AC is removed from the set, thisnegative voltage will disappear. The voltage across the filter capacitors on the +3V line willturn 7561 On. The Power Down line will then go Low signaling the processor to shut the setdown.
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K
A R E F
Vcc
Gnd
Ctrl
START-UPCURRENT SOURCE
VALLEY
START-UPCURRENT SOURCE
CURRENTSENSING
OUTPUTDRIVER
OVERPOWER
LOGICCONTROLCIRCUIT
MAXIMUMON-TIME
PROTECTION
VOLTAGECONTRLLEDOSCILLATOR
OVERTEMPERATUREPROTECTIOM
POWER-ONRESET
SUPPLYMANAGEMENT
FREQUENCY
PROTECTION
CONTROL
INPUTCONTROLCIRCUIT
BURSTDETECTOR
Drain
HVS
Sense
Demag
Driver
*
0V
300K
S
20V
I564
0H
6
E15V8
15V9
1 0 V
1M5
470U
2522
470p
3599
*
1V3
9
TEA1507
---JMP
3V4C
E
158V
C4V5
3V4
E0V
B
REGION
354027VRF-HD
---
---
*
JMP
AUXILIARY POWER SUPPLY
1V5
2
G
*
0V1
3V4
3 m 3
7
3
E
158V
0V
E
B
C
B
3V7
Microcontro
11
2V5
C
9V
15V8
0V6B
8 V 1
3 3 0 K
B15V8
To 1533 O
Source Sele
*
0V
*
D
14
B0V
E
C
0V
0V7
*
*
*
C
*0V
E
B
C0V6
8V
9V
*
95309534
NAFTA30WSRF-HD
------------
SIZE
354835513566452345404548455145664585552365537535951595249529
---
---
Vaux_GND
100MHZ 120RBAS316
SI2307DS-E3---------------
---
---
------------
JMP---
JMP---
---100MHZ 120RBAS316
SI2307DS-E3---------------
Vaux_GN
Vaux_
Vaux_GND
I537
I594
6 5 1 2
B Z X 3 8 4 - C 1 8
2 2 u
2 5 1 0
2591
1n0
470p
2539
3 5 6 8
4 7 K
1n0
2524
I536
I556
I532
Vaux_GND
I526
B A V 2 1 W S
6 5 3 7
2 5 9 0
1 0 n
2 5 7 5
B Z X 3 8 4 - C 1 5
6 5 4 9
BAV21WS
6532
6545
SB340L-7010
2 5 2 6
1 0 0 n
Vaux_GND1
1 0 K
3 5 9 3
1 0 0 0 m
A
T 1 5 3 2
I558
I512
I 5 5 4
4 5 8 5
I553
Vaux_GND
5678
15341234
220R
3563 6540
BAS316
2K2
3536
Vaux_GND
2586
330p
B A S 3 1 6
6 5 3 1
BC857B7532
I533
RGP10D
6533
3 3 K
5521
3 5 9 2
IMX1
12
MainSupplyGndA
7549-2
HEATSINK0088
B A S 3 1 6
6 5 3 4
3 5 8 7
2 K 2
2 5 8 0
1 0 n
I 5 0 9
3 5 3 2
3 5 2 9
1 K 2
BAV21WS
6538
3 5 3 8
2 5 2 3
1 n 0
6546
STPS10L60D
HEATSINK0083
1 2
5523
4551
I538
I599
I563
I592
3 5 2 8
4 M 7
3 5 3 5
4 R 7
I557
100n
2520
SB340L-701
6544
IMX17549-1
Vaux
3 5 9 4
2 2 K
I510
Vaux_GND
4523
I565
3 5 3 4
3 5 3 3
14
3 2
7516TCET1103(G)
Vaux_GND1
Vaux_GND
3 5 8 8
4 7 0 K
1n0
2538
7575PDTC143ZT
2579
10n
I593
5527
3525
4 7 n
2 5 2 1 2588
1 m 0
2 5 3 6
Vaux_GND1
I539
I568
680R
3542
3549
270R
Vaux_GND
BC857B
3 5 8 3
5 K 6
7585
3 5 9 6
1 0 K
2 5 2 5
4 7 0 p
2 5 8 5
1 u 0
SARS03
6550
2578
1n0
2 5 4 4
2 n 2
I540
F581
I595
2 5 8 2
1 0 0 n
3 5 2 7
4 7 K
Vaux_GN
7567BC847B
3 5 9 5
1 0 0 K
7525
1 0 u
2 5 8 3
3 5 3 9
1 K 0
3550
220K
7510
3 K 3
3 5 6 7
9
10
11
12
2
4
5
6 7
8
SS28411-00
5504
1
3543
10K
STPS10L60D
6552
56K
3530
I590
I529
2 5 2 8
4 7 0 n
I528
I531
3 5 8 9
1 0 K
Vaux_GND13551
4R7
6539
SB340L-7010
7576BC847BW
I560
I597
3526
3597
47K
6 8 p
2 5 9 2
2
1
3
3 5 3 1
1 K 0
T L 4 3 1 C Z - A P
7 5 4 2
I530
B A S 3 1 6
6 5 3 6
3 5 9 8
+3V3AVDC
AC_IN
VCC
1.27V On1.45V Off
15.5 On11.5 Off
21 On11.8 Off
F I G
U R E 2 -A
U X I L I A R Y P
OWE R
S U P P L Y
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Main power supply (Figure 3)
The Main Power supply provides the VBAT (141 volt), and Audio voltage supplies. This sup-ply is switched Off during the Standby mode. During Standby the STBY_Con line is Highwhich turns Transistor 7573 On. This causes the opto-isolator 7513 to turn On hard. Thisplaces a higher voltage on the control Pin of IC 7511 causing the IC to shut down. Theoperating voltage from the Auxiliary supply keeps a small voltage on Pin 2 of 7511 to preventit from cycling On and Off. Output from Pin 11 of 7511 drives FET 7512 which drivesTransformer 5512. When Pin 2 of 5512 goes High, Transistor 7514 is switched On turning7512 Off. This is to prevent 5512 from becoming saturated.
When the set is turned On, the STBY_Con line goes Low switching 7573 Off. The VBATsupply is the reference voltage for regulation. Since this voltage is missing during startup, theShunt Regulator 7571 is turned Off. The voltage on Pin 6 of 7511 goes Low, which turns thedrive from the IC On. When the set is On during normal operation, the supply voltage on Pin2 of the IC is supplied by Pin 2 of Transformer 5512. When the VBAT supply reaches thecorrect voltage, Pin 3 of the Shunt Regulator 7571 reaches 2.5 volts switching it On. Thisswitches the opto-isolator On to provide a regulation feedback path.
Transistor 6551 provides a power on ramping ofthe VBAT supply.
7512 drive test points.
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- T V
-T
+ T R s
R h
K
A R E F
Vcc
Gnd
Ctrl
START-UPCURRENT SOURCE
VALLEY
START-UPCURRENT SOURCE
CURRENTSENSING
OUTPUTDRIVER
OVERPOWER
LOGICCONTROLCIRCUIT
MAXIMUMON-TIME
PROTECTION
VOLTAGECONTRLLEDOSCILLATOR
OVERTEMPERATUREPROTECTIOM
POWER-ONRESET
SUPPLYMANAGEMENT
FREQUENCY
PROTECTION
CONTROL
INPUTCONTROLCIRCUIT
BURSTDETECTOR
Drain
HVS
Sense
Demag
Driver
9V3
*
HOT GROUND
D
R E S
15V5
HOT
G
*TUNER IF
Front Interface Panel
6
*
FOR MAINS 120V AC 170V (177V)
1 0 0 n
*
*14
*
* R E S
(For
TEA1506T/N1
2V3
..V.. Normal Operation
POWER SUPPLY
*
0V
T4E.250V
Lightning Protection
VbatAUDIO OUTPUT
1572
"$"
Provision For
15V6
COLD
0 R 1
3
7
*
16V4
2506
33n
R E S
LKS1AF
0V
DEGAUSSING COIL
*
9
SETMAIN RANGE
REGION
For ITV only*
Provision For
R E S
0V
0V
AC Main PlugOr
From 1505 Of
For EMC
470P
*
157725065500950295049506
2
*
*
297V
*
COLD GROUND
(..V..) Standy Mode
F o r
I T V O n l y
1 n 5
TO 1013 OF
RES
8V2
295V
1 n 5
*
2V3
Protection)
*
2V2
RES
16V4
RES
*
R G P 1 0 D
Lightning Protection
"$"
S
11
0V
Lightning
*
95779572
5V
1502PFC5000
1546
AC_IN
2
1
3
B A S 3 1 6
6 5 1 4
6551
STPS10L60D
6564
I525
I543
100n
2516
4 7 K
3 5 4 1
I542
5561
6563
I584
I583
3579
2K2
5564
1 4
2 3
45
81
DMF2405H60
I501
5502
I513
9506
I561
3 5 0 0
3 M 3
3 5 1 6
2 5 0 5
5
8
9
13
14
15
16
17
182
3
4
5512
10
11
12
1 M 5
3 5 0 4
2 5 0 3
2 n 2
I502
1K0
3515
F503
I527
Audio_Gnd
2 5 0 2
PFC50001501
12
3 M 3
1505
F506
3 5 0 1
22u
5563
AUDIO_GND2
1510
2 5 7 4
1500
9513
9512
3509
2R0 2 n 2
2 5 0 4
I522
9 5 1 1
TCET1103(G)7513
14
3 2
3508
220R
7512
2 2 u 2 5
1 1 5 0 V 470p
2565
F541
I562
3 5 2 0
I582
I521
I581 I552
I580
1
3
2
7 5 7 1
T L 4 3 1 C Z - A P
2
15071
3523
3
2
1
4 R 5 4
R 5
2 5 4 1
4 7 u
2 5 V
9503
2 5 0 8
1 0 0 n
1 N 5 0 6 2
5551
6 5 7 5
3502
I505
F509
3 5 1 9
1 5 K
9510
MainSupplyGnd
47K
3522
2518
10n
I515
I508
7511
I511
15n
2571
2542
F501
3 5 2 4
4 7 K
9505
F504
3 K 3
3 5 2 1
BC857B7541
1 n 0
2 5 1 7
3571
F502
MainSupplyGndA
I551
9500
2 5 1 5
4 7 0 p
5 5 1 1
F500
I573
2K2
3513
I520
I519
F507
6 5 1 1
I514
AUDIO_GND1
Vaux_GND1
F 5 1 0
6562
9563
F508
F542
2 5 1 2
3 M 3
3 5 0 6
4 R 7
3 5 1 1
I506
I579
2551
1n0
2 5 0 1
1 0 0 p
2 5 1 9
I571
5562
3 5 0 5
2570
2 5 0 7
3 5 1 0
7514BC847B
3 5 1 7
3 3 0 K
2 R 0
1 K 2
I524
I572
3 5 1 2
I517
B Z X 3 8 4 - C 1 2
6 5 4 1
2 3
5500
1 4
2 5 1 4
I523
2561
1n0
3518
9502
Vaux_GND1
3K3
9501
1 4
2 3
I518
DMF2405H60
5501
1503
3
4
1
2
AUDIO_GND2
4 7 0 n
I 5 0 7
2 5 0 0
1 4
9504
6500
2
355061 4
2 3
12
DMF35
1504
3 5 1 4
3503
DSP-301N
2 5 0 9
2 5 1 3
4 7 0 p
1545
I516
5513
1u0
VCC
+Vaudio
VDC
14 On2.8 Off
0.6VOff1.3VOn
F I G
U R E
3 -MA I N P
OWE R
S U P P L Y
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Deflection
Sync (Figure 4)
Whatever signal is applied to the L05 chassis, it will display the picture in a 1080i format.This means that the Line or Horizontal frequency is always 33.75 kHz. The Vertical or Framerate is 60 Hz.
Vertical Sync is output from the Trident IC 7201 on Pin 35. The signal is buffered byTransistor 7203 before being fed to the TV display processor and TV Microcontroller. In thesame manner Horizontal Sync is output on Pin 34 and is buffered by Transistor 7204.
AD
PSRESETADDRSEL
ALEWRRD
SDSC
INT
IRSET
HFLB
VPROTHSYNC
VSYNC BGR
VM
76543210
T3T3
T2
T2
2V5
1V5
2V2
T3
2V5
2V52V52V5
3V30V2V42V42V42V4
3V3V
3V3
1V3
2V4
0V
0VT1,T5
T2
T3T3
T1,T
T3
T2,T5
T2,T5
T2
T3
T3
T3T2
2V52V5
Sets w/o PP
T3T1,T
T
T
T1,T
2V5
*
T1,T5
0V
0V
0V
0V
* *
*
3V
T
2V5
T3
2V52V52V51V92V52V50V2V5
3V3
2V5
2V5
2V5
2V5
2V5
V2
220R
F208
3203
26
37
35
176
2836
34
180
31
6
27
177
5
179178
171170169168167
166165
4
175
29
6930 DPTVSVP
& DDPDAC
CPU
7201-2
172
560R
3221
AGND5
F287
2 2 2 5
1 0 0 n
7203BC847B
BC847B7204
2 2 1 7
1 0 0 n
1 0 0 n
2 2 2 0
4203
2 2 2 4
1 0 0 n
F207
3229
180R
3 2 2 8
2 2 0 R
3223
100R
220R3207
4202
2 2 3 9
1 0 0 n
2 2 1 9
1 0 0 n
2 2 2 2
1 0 0 n
7201-46930 DPTVSVP
3 2 2 5
1 K 0
F288
150R
32278
2
9
3
3
0
987
1
43210
4204
1 0 0 n
2 2 2 1
3202 10K
4n72246
6 8 p
2 2 4 2
3204 220R
1K0
3284
27p
2240100R
3224
3 2 3 0
7 5 R
F290F289
16V 22u
2263
3283
1K0
1u0
2241
2 2 2 6
1 0 0 n
2 2 1 8
1 0 0 n2247
4n7
BC857B7202
11 12
4209
10
1 0 0 n
2 2 2 3
220R3208 10K
3222
2 2 4 3
6 8 p
3206 220R
220R3205
HSYNC
+5V
+5V
CAPD17CAPD16
CAPD23CAPD22CAPD21CAPD20CAPD19CAPD18
SVM_PP
3
VM
RD
VSYNC
SDA_OUT
+8V
PSMALEWR
SVM_ROT
DPTV_RDPTV_GDPTV_B
SCL_OUT
RESET
HS_9883
VS_9883
CLK_9883
VCC3
+3V3
VCC3
FIGURE 4 - SYNC
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TV Signal Processor (Figure 5)
Red, Green, and Blue from the Trident IC is input on Pins 30, 31, and 32 of 7221, TV DisplayProcessor. The RGB/YUV matrix changes the signal to a YUV signal before feeding it to aColor level control circuit. The signal is fed to the RGB insertion circuits where the OSD isinserted. The signal is then fed to a White Point and Brightness Control circuit and then tothe CRT panel. The White Point and Output Amplifier have the Drive controls and Cutoff con-trols. Input from the ABL line on Pin 43 makes adjustments in the brightness levels to adjustfor changes in beam current. The Cutoffpulses from the CRTs are fed to Pin 44 to the Cathode Calibration circuit. The CathodeCalibration circuit adjusts the cutoff levels of the CRT to maintain the correct gray scale track-ing. When the set is first turned On, a calibration pulse is output on the RGB lines. TheCathode Calibration circuit monitors this pulse on the Cutoff line to set the Black level and themaximum drive voltage for the cathode. Once the Calibration has taken place, the OutputAmplifier switches to the RGB drive signal as the output. Horizontal and Vertical Sync is fedto 7600 on Pins 23 and 24. IC 7600 processes the sync to provide the geometry for the pic-ture. Horizontal drive is output to the sweep circuit on Pin 8. Vertical drive is output on Pins 1and 2. East West drive is output on Pin 3. Sandcastle (SCO) is output on Pin 9. Horizontal
Feedback (HFB) from the sweep circuit is fed into the Phase Loop to phase correct theHorizontal drive. IC 7221 is controlled by the Hercules Processor on the Family Board via theI2C buss on Pins 10 and 11. Transistors 7226 and 7227 levels shifts the I2C buss levelbetween 5 and 3.3 volts. Geometry and Drive settings are stored in the Memory IC locatedon the Family Board.
Deflection (Figure 6)
Horizontal drive from 7221 is fed to Transistor 7404 located on the Family board. This drivecircuit has two power sources. During startup, it is powered by the +6 volt supply. Once theHigh Voltage circuit is running, it is powered by Pin 9 of the IFT. 7404 drives Transformer5402 which drives the HOT (Horizontal Output Transistor). The HOT drives the IFT and theHorizontal Deflection Coil. The IFT is powered by the VBAT (141 volt) supply.
The IFT produces High voltage, Focus voltage and G2 voltage to drive the CRT. In addition,a 200 volt supply is produced to drive the CRT panel, a +14 and -14 volt supply for theVertical output, Filament voltage, +200 volt VideoSupply, and a +12V_lot supply.
Transistor 7408 monitors the IFT secondary to sense the presence of over voltage. If theHigh Voltage goes High, the voltage on Pin 6 of the IFT will go High. When the voltage ondiode 6480 exceeds 15 volts, transistor 7408 will turn On. If 7408 turns On, it will turn 7407On causing the x_ray protect line to go Low. The Processor will then shut the set down. Inaddition the EW_DRIVE circuit is monitored. If the EW_DRIVE fails, transistor 7406 will turnOn constantly placing a dc voltage on the source. This will turn 7407 On.
IC 7451 is the Vertical Output IC. It is powered by the +14 and -14 volt supply from the IFT.The Vertical pulse is rectified by 6458, keeping the V_PROTN line High. If the vertical outputshould fail, the V_PROTN line will go Low. The Hercules processor will then shut the setdown.
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FIGURE 5 - TV SIGNAL PROCESSOR Page 11
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Set Control (Figure 7)
The L05HD has two microprocessors, The Hercules located on the Family board and the TVController located on the Trident board.
The Hercules, 7200, provides control for the entire set. During standby, the Hercules and theRemote sensor are powered by the 3.3 volt supply. The customer communicates with theHercules via the Remote sensor and Power switch located on the Front Control panel. Thepower supplies are switched On via the STBY-CONT and B lines. The TV Controller is resetby the C control line. The I2C bus communicates with the EEPROM 7601, Tuner 1000, TVController 7206, Trident 7201, A/D 7210, TV Display Processor, 7221, and HDMI panel.
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HERCULES PROCESSOR
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FIGURE 7 - CONTROLPage 14
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AV1, AV2, CVI (480i), Side, and Tuner selections are made by the Hercules chip. SelectedCVBS (Composite Video) from one of these inputs is fed to the Trident panel which selectsbetween the output of the Hercules, CVI (480p, 720p, 1080i), and the HDMI panel. The CVIinput is shared by the Hercules and the HD section.
The L05HD has the following inputs in addition to the tuner RF:
AV1 is a Composite video input. CVI (Component Video input) can accept 480i, 480p, 720p, or 1080i. AV2 accepts Composite video (CVBS) or S-Video. Side accepts Composite video (CVBS) or S-Video. HDMI (High Definition Multimedia Interface) accepts 480p, 720p, or 1080i video andaudio in a digital TMDS format.
Detailed Signal flow (Figure 9)
The output of the Tuner is fed to the SAW filter, 1002, and then to 7200, Hercules, on Pins
104 and 105. The SVHS (YC) signals are combined inside 7200. IC 7200 selects betweenAV1, AV2, Side, and Tuner composite video. The selected composite video is output on Pin65. Video buffered by Transistor 7211 is fed to IC 7206 located on the Trident panel whichextracts Closed Caption text and Teletext information. This IC also generates the OSD (OnScreen Display). Video buffered by 7212 is fed to the Trident IC which has an internal 3-DComb Filter and A/D converter. IC 7201 rescales the picture to 1080i.
Component video is inserted into the YPbPr input located on the Family board. The HDMIpanel converts the HDMI signal into an analog YPbPr format. Both of these signals are fed tothe Switch, 7205 which selects between the two. The selected signal is fed to IC 7210 whichperforms an A/D conversion. This 24 bit signal is fed to 7201. The Scaler (Trident IC) con-verts the signal to a 1080i format as well as performing picture enhancement functions.DRAM ICs 7215, 7216, 7217, and 7218 stores picture data for the Scaler as it is beingprocessed. And internal D/A conversion circuit outputs the 1080i signal is an RGB format onPins 27, 28 and 29. Horizontal and Vertical sync is output on Pins 34 and 35.
The RGB signal from the Scaler is fed to the TV Display Processor, 7221. RGB is outputfrom this IC to the CRT panel. Horizontal and Vertical drive is output to the Family board.
TV Display Processor (Refer to Figure 5)
IC 7221 is used in a large number of Philips chassis for a long period of time. RGB in insert-ed in Pins 30, 31, and 32. This signals are converted to a YUV format before being fed to theColor level control. RGB from 7206 is inserted on Pins 35, 36, 37, and 38. The signal thengoes to a Brightness and Controls control circuit. RGB to the CRT panel is output on Pins40, 41, and 42. During warm up, a cathode calibration signal is fed to the CRT panel on theRGB lines. This signal is then fed back to
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FIGURE 9 - DETAILED VIDEO SIGNAL FLOW BLOCK Page 17
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CRT panel (Figure 10)
RGB is fed to the CRT panel on connector 1331. The CRT panel for the L05HD has a singlechip CRT drive circuit. RGB is fed to 7330 on Pins 1, 2, and 3. Signal is output to the CRTon Pins 7, 8, and 9. BC_INFO or Cutoff on Pin 5 is fed back to the TV Signal Processor onthe Trident panel. The IC is powered by a 200 volt supply on Pin 6.
DC operating voltages for the CRT panel are located on connector 1351. The Filament volt-age is located on Pin 2. The 200VA voltage on Pin 5 powers 7330. The VBAT voltage onPin 3 and the +12V_LOT voltage on Pin 6 powers the SVM circuit.
SVM (Figure 11)
There are two coils on the deflection coil in addition to the Vertical and Horizontal winding.The SCAVEM coil (Scan Velocity Modulation) sharpens the edges between light and darktransitions.
The SVM_ROT signal drives both the SCAVEM and the Rotation coil. The SCAVEM circuit ispowered by the Vbatt and +12V_LOT supplies. Capacitor 2376 blocks the dc Rotation signalto prevent it from entering the SCAVEM circuit. Capacitor 2381 blocks the higher frequencySCAVEM signal to prevent it from affecting the Rotation drive.
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SVM Coil
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Blue
Green
Red
7V
THERMALPROTECTION
IN1
IN2
IN3
GND
BC1
OUT3
OUT2
OUT13k77
3k77
3k77
3k75
3k75
3k75
188k7
188k7
188k7
Vdd
Vdd
Vdd
Vref
Vref
Vref
Vref2.5V
BC1
BC2
BC3
A1
A2
A3
From 1202 of
R
AQUADAGWIRE
2V5
1 0 n
* **
B
2V5
*
I357
I355
6V
156V
1n5
V
2V5
156V
156V
CRT Sockets
*
G
CRT PANEL
Line + Frame
200V
**
* *
47n
T 0 C R T S O C K E T
From 1401 of
of Trident Panel
Deflection
*
3 3 5 7
F351
F356
D?TYPE
6 3 3 2
B A V 2 1
I337
2 3 3 0
1 0 0 n
3334
1K0
F339
4334
2 3 3 4
I339
F334
I332
3 n
3
2 3 5 3
4 3 3 0
6 8 0 p
2 3 5 2
3 3 2 9
1 0 0 R
4 3 2 9
F340
I333
I335
I331
1K0
3332
1 0 0 R
3 3 2 8
F354
F338
I334
I336
6 3 3 1
B A V 2 1
100R
3335
3333
100R
1332
I330
I351
2350
2 3 3 3
1 n
0
9 3 6 0
F335
HEATSINK0330
2 3 3 1
1 0 n
F332
4 3 2 8
1K0
3336
3337
F353
F352
3 3 3 0
1 0 0 R
2351
10u
3 3 5 4
1 K 5
2332
F341
1 0 0 R
3 3 6 0
B A V 2 1
6 3 3 3
I340
F333
I338
9337
I353
7
100R
3331
123456
1351
89
I352
F331
1
101112
567
89
1254
101112
567
12561
3351
100R
345
7330
1
2
3
4
5
6
7
8
9
1331
12
10R
3356
G N D
_ C R T
Filament
+12V_LOT
+200VA
BC_INFO
EHTinfo
+200VA
EHTinfo
Vbatt
SVM_ROT
B1
REGIONSET
NAFTA27VRF-HD
3328332933303337336043284329
---------------
JMPJMP
43309337
JMP---
9360 JMP
F I G
U R E 1 0 -
C R T P A N E L
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0 V 5
1 R 8
T O
7 V 8
B
8 K 2
4 7 V 3
C
7 V 5
*
*
* 9 6 V
E
7 V 5
2 V 3
B
E
2 S C 3 4 2 1
C
E C
B
1 V 7
7 V 2
0 V
T O
*
9 7 V 3
R O T A T I O N C O I L
* *
E
B
E
*
B
C E
3 V 8
6 V 7
8 V 2
1 0 V 8
6 V 8
1 2 V 8
S C A V E M C O I L
7 V 2
4 7 V 2
B 1
2 2 n
*
2 S A 1 3 5 8
*
3 3 6 7
I 3 6 5
9 3 6 1
3 3 7 3
1 6 V 1 0 u
2 3 9 0
2 3 9 1
1 0 0 n
4 0 0 V
2 3 6 4
4 n
7
3 3 8 9
3 3 R
F 3 8 2
3 3 8 2
6 K 8
4 n
7
U D Z S - 6 V 8
2 3 6 5
6 3 8 1
I 3 6 3
7 3 6 2
B C 8 5 7 B
B C 8 4 7 B
7 3 7 6
F 3 8 1
I 3 6 7
I 3 6 4
2 3 8 5
2 3 8 9
2 3 6 8
1 u
0
5 3 3 1
1 0 R
3 3 6 2
1 5 0 K
3 3 9 0
1 5 0 K
3 3 9 1
6 8 0 K
3 3 9 3
2 2 K
3 3 9 2
F 3 6 2
3 3 8 7
2 3 6 2
1 n 0
1 0 n
2 3 8 7
B C 8 4 7 B
7 3 6 1
F 3 6 3
I 3 4 8
8 K 2
3 3 7 2
I 3 8 0
I 3 6 1
3 3 6 5
1 0 R
I 3 6 6
3 3 6 8
8 2 0 R
3 3 0 R
3 3 7 6
5 3 6 1
F 3 6 1
+ 1 2 V
_ L O T
4
M O D E
2
O U T +
7
O U T -
S V R
6
1V C C
7 3 6 4
T D A 8 9 4 1 P
8 G N D
3
I N +
5
I N -
1 3 8 1
1 2 3
7 3 3 1
1 K 8 3 3 7 5
I 3 4 4
I 3 4 5
I 3 4 2
I 3 4 3
I 3 4 1
2 3 8 3
1 0 0 n
3 3 R
3 3 8 8
3 3 6 3
8 2 0 R
3 3 6 9
1 0 R
2 3 6 7
1 0 u 1 0 0 V
2 2 0 R
3 3 7 7
2 3 6 1
4 7 n 2 5 0 V
3 3 7 1
4 7 0 R
I 3 7 1
2 2 u
2 3 6 3
3 3 6 6
6 8 K
F 3 6 0
1 0 0 V
2 3 7 6
1 0 0 n
I 3 4 7
3 3 6 1
6 8 0 R
1 R 8
3 3 6 4
1 3 6 1
1 2 3
I 3 6 2
I 3 4 6
4 3 3 1
2 3 8 1
1 0 0 n
6 8 K
1 N 4 1 4 8
6 3 6 1
3 3 7 0
I 3 7 2
2 3 8 4
1 0 0 n
2 3 8 2
7 3 6 3
6 K 8
3 3 8 1
I 3 6 0
3 3 9 4
6 K 8
+ 1 2 V
_ L O T
I 3 6 9
I 3 8 1
I 3 6 8
V b a
t t
+ 1 2 V
_ L O T
S V M
_ R O T
R E G I O N
S E T
N A F T A
2 7 V R F - H
D
4 3 3 1
5 3 3 1
5 3 6 1
9 3 6 1
- - -
1 U 0 P M 1 0
1 0 0 M H Z 5 0 R
- - -
FIGURE 11 - SVM AND ROTATIONPage 20
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Audio (Figure 12)
All audio processing and control is performed by the Hercules IC 7200 located on the mainboard.
Audio is included in the HDMI bit-stream. Digital audio from 7002 is fed to IC 7011, AudioDAC. Audio from 7011 is fed to IC 7050, switch, which has only one input since the secondinput is not used in the HD version. The output of 7050 is fed to the Hercules IC located onthe Main board. Audio for the CVI input should be inserted into AV1. Audio is output from theHercules on Pins 68 and 69 to the Audio Amplifier, IC 7990. This is a two channel 20 wattamplifier.
Audio output
Main audio is output on Pins 68 and 69 and fed to the audio amplifier 7990. The audio ampli-fier is a dual 10 watt amplifier. It is powered by the +VAUDIO and -VAUDIO supplies. Theseare +16 and -16 volts. To mute the amplifier, the VOL_MUTE line goes Low switching tran-sistor 7992 Off switching transistor 7991 On. The output of the amplifier is fed to the Side
Jack panel.
Monitor audio is output on Pins 66 and 67 of 7200. These outputs are muted by theSTBY_CONT and POWER DOWN lines. The POWER DOWN line is High during normaloperation. As the set powers off, this line goes Low, switching 7993 Off. Transistor 7104then switches On to mute the output. The STBY_CONT line goes High when the set is
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FIGURE 13 - AUDIO OUTPUTPage 22
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*
*
4 7 0 p F
4 7 0 p F
HEADPHONE
ECO SUB
TO
TO
SPEAKERS
I166
I168
3157123
1279
6
7
8
9
12321
2
3
4
5
I162
I163
2 1 8 1
1 u
I170
I169
I171
3 9 K
3 1 6 1
12345
1254
2 1 7 6
2 1 7 8F154
3156
1278
1234
turned Off turning 7994 On, muting the output. Capacitor 2999 delays the turn-on of 7993 toprevent a pop in the speaker at set turn On.
Side Jack panel (Figure 14)
The output of the audio amplifier is fed to the Headphone Jack located on the Side Jackpanel. The output to the speakers is switched Off when a headphone plug is inserted.
Finding the defective panel (Figures 15 and 16)
When troubleshooting the set, the defective panel requiring replacement or additional repairmust be located. The Power supplies, Deflection, 1fH inputs, and Audio outputs are locatedon the Family board. The 2fH, CRT drive, and Deflection drive circuits are located on theTrident board.
If the set turns On without a picture or sound, first check the power supplies located on the
Family board. If the set comes On, then shuts Off, there may be a problem with the shut-down circuits which are located on the Family board. If the picture is missing, but sound andhigh voltage are present, the problem may be located on the Trident panel.
FIGURE 14 - SIDE JACK PANEL
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SIDEA/V PANEL +HEADPHONE
D
CRT PANEL(component view) B
TOP CONTROL PANELE
AHEADPHONE
RIGHT (RED)
LEFT (WHITE)
CVBS (YELLOW)
1010
CRT PANELB
MONOCARRIER
3P
REDBLACK
RIGHT
SPEAKER
GREY
ORANGE
FRAMEROTATION
COIL
AQUADAG
DEGAUSSING COIL
SCAVEMCOIL
CRT16:9
12112P
5 P
5P
7 P
1693
7 P
1207
1005
7 P
1252
2P1451
3 P
1682
2P
1401
5 P1254
3 P1280
4 P
12781280
5P1351
3P1361
3P1381
1504
LOT
T U N E R
1352
1335
CRTSOCKET
3P
COMPAIRCONNECTOR
TRIDENT PANELT
1223 4 P
1250 1 2 P
1251 1 0 P
12025P
1250
1 2 P
1251
1 0 P
5P1340
12064P
153312P
12216P
12207P1228
6 P
1222
6 P
6 P1228
4 P1206
1 2 P
1533
3 P
1281
1336
2P
1404
BLUE BROWN
F I G
U R E 1 5 -
C ON N E
C T
OR I N T E R
C ON N E
C T
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FIGURE 16 - WIRING INTERCONNECT Page 25
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Page 26
SERVICE POSITION
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Abbreviation list
Description
1080i 1080 visible lines, interlaced1080p 1080 visible lines, progressive scan480i 480 visible lines, interlaced480p 480 visible lines, progressive scanADC A/D Analogue to Digital ConverterAFC Automatic Frequency Control: control signal used to tune to the correct
frequencyAGC Automatic Gain Control: algorithm that controls the video input of the
feature boxAM Amplitude ModulationAV Audio VideoC-FRONT Chrominance front inputCBA Circuit Board Assembly (or PWB)ComPair Computer aided rePair
CSM Customer Service ModeCVBS Composite Video Blanking and SynchronizationCVBS-EXT CVBS signal from external source (VCR, VCD, etc.)CVBS-INT CVBS signal from TunerCVBS-MON CVBS monitor signalCVBS-TER-OUT CVBS terrestrial outDAC Digital to Analogue ConverterDFU Directions For Use: owner's manualDNR Dynamic Noise ReductionDRAM Dynamic RAMDSP Digital Signal ProcessingDTS Digital Theatre SoundDVD Digital Video DiscEEPROM Electrically Erasable and Programmable Read Only MemoryEPLD Electronic Programmable DeviceEXT EXTernal (source), entering the set by cinches (jacks)FBL Fast Blanking: DC signal accompanying RGB signalsFLASH FLASH memoryFM Field Memory / Frequency ModulationFMR FM RadioFRC Frame Rate ConverterFRONT-C Front input chrominance (SVHS)FRONT-DETECT Front input detectionFRONT-Y_CVBS Front input luminance or CVBS (SVHS)H H_sync to the moduleHD High DefinitionHDMI High Definition Multimedia InterfaceHP HeadPhoneI2C Integrated IC busI2S Integrated IC Sound bus
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IC Integrated CircuitIF Intermediate FrequencyInterlaced Scan mode where two fields are used to form one frame. Each field contains
half the number of the total amount of lines. The fields are written in 'pairs',causing line flicker.
IR Infra RedIRQ Interrupt ReQuestLast Status The settings last chosen by the customer and read and stored in RAM or in the
NVM. They are called at start-up of the set to configure it according the cus-tomers wishes
LCD Liquid Crystal DisplayLED Light Emitting DiodeLINE-DRIVE Line drive signalLVDS Low Voltage Differential Signalling, data transmission system for high speed
and low EMI communication.MPEG Motion Pictures Experts GroupNVM Non Volatile Memory: IC containing TV related data (for example, options)OSD On Screen Display
Progressive Scan Scan mode where all scan lines are displayed in one frame at the sametime, creating a double vertical resolution.RAM Random Access MemoryRC Remote Control transmitterRC5 Remote Control system 5, the signal from the remote control receiverRGB Red, Green, and Blue. The primary colour signals for TV. By mixing
levels of R, G, and B, all colors (Y/C) are reproduced.RGBHV Red, Green, Blue, Horizontal sync, and Vertical syncROM Read Only MemorySAM Service Alignment ModeSIF Sound Intermediate FrequencySC SandCastle: two-level pulse derived from sync signalsSCL CLock Signal on I2C busSDA DAta Signal on I2C busSDRAM Synchronous DRAMSIF Sound Intermediate FrequencySTBY STandBYVGA Video Graphics ArrayXTAL Quartz crystalYPbPr Component video (Y= Luminance, Pb/Pr= Colour difference signals)Y/C Luminance (Y) and Chrominance (C) signalY-OUT Luminance-signal
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