philadelphia university faculty of engineering · 2013. 11. 6. · 10) half adder consists of....

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Philadelphia University Faculty of Engineering D Final Course Title: Logic Ci Course No: 630261 Lecturer: Dr. Qadri Information for candidates 1. This exam paper contains 7 que 2. The marks for parts of question Advices to candidates You should attempt all sub question Basic notions: The aims of the questions in this pass category represent the minimum understa Basic Logic Gates, Boolean Expression Simplific Question 1 Multiple Choice Identify the choice that best completes th 1) One of the following numbers is a) 1234 b) 10000 2) Conversion of hexadecimal numb a) 451 b) 151 3) Subtract (1010) 2 from (1101) a) (0101) 2 b) (1001) 2 4) The signed-magnitude binary rep a) 11111011 b) 11011000 5) In Boolean algebra A+ AB =---- a) AB b) A 6) Applying DeMorgan's Law to f a) ( f A B = + b) ( f A B = + 7) If the hex number 4C is applied t a) 4C b) CD 8) 8421 code is also called as. a) Gray cod b) ASCII co Student Name: Student Number: Dept. of Computer Engineering l Exam, Second Semester: 2010/2011 ircuits Date: Time Allowed: i Hamarsheh No. Of Pages: estions totaling 50 marks are shown in round brackets. ns. You should write your answers s part are to evaluate the required minimal student knowl anding of basic concepts: Digital Systems, Binary Numb cation, Karnaugh Maps, and Combinational Sequential C he statement or answers the question. illegal in base 4: c) 3320 d) 111111 ber (69) 16 to octal equivalent will give c) 251 d) 351 ) 2 using 1st complement --- c) (0011) 2 d) (1100) 2 presentation of the number +27 is 1 c) 00011011 0 d) None of the abov --------- c) A+B d) B ( 29 AB C DE = + + will result in: ( C D E + c) ( ( f A B C D E = + + + ( C D E + d) ( ( f A B C D E = + + + to eight NOT gates, the output would have the va c) FF d) B3 de c) BCD code ode d) excess 3-code : 09/06/2011 2 hours 6 s clearly. ledge and skills. Answers in the ber Systems, Boolean Algebra, Circuits. (15 marks) ve E E alue of:

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Page 1: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

Philadelphia University Faculty of Engineering

Dept. of Computer EngineeringFinal

Course Title: Logic CircuitsCourse No: 630261 Lecturer: Dr. Qadri Hamarsheh

Information for candidates

1. This exam paper contains 7 question2. The marks for parts of question are shown in round brackets.

Advices to candidates You should attempt all sub questions

Basic notions: The aims of the questions in this part are to evaluate the required minimal student knowledge and skills. pass category represent the minimum understanding of basic conceptBasic Logic Gates, Boolean Expression Simplification, Karnaugh Maps Question 1 Multiple Choice Identify the choice that best completes the

1) One of the following numbers is illegal in a) 1234 b) 10000

2) Conversion of hexadecimal number a) 451 b) 151

3) Subtract (1010)2 from (1101)a) (0101)2 b) (1001)2

4) The signed-magnitude binary representation of the number +27 isa) 11111011b) 11011000

5) In Boolean algebra A+ AB =-----------a) AB b) A

6) Applying DeMorgan's Law to f A B C D E

a) (f A B C D E= + +b) (f A B C D E= + +

7) If the hex number 4C is applied to eight a) 4C b) CD

8) 8421 code is also called as. a) Gray codeb) ASCII code

Student Name:

Student Number:

Dept. of Computer Engineering Final Exam, Second Semester: 2010/2011

Logic Circuits Date: Time Allowed:

Qadri Hamarsheh No. Of Pages:

questions totaling 50 marks The marks for parts of question are shown in round brackets.

sub questions. You should write your answers clearlyThe aims of the questions in this part are to evaluate the required minimal student knowledge and skills.

pass category represent the minimum understanding of basic concepts: Digital Systems, Binary Number Systems, Boolean Algebra, Boolean Expression Simplification, Karnaugh Maps, and Combinational Sequential Circuits

Identify the choice that best completes the statement or answers the question.

One of the following numbers is illegal in base 4: c) 3320 d) 111111

Conversion of hexadecimal number (69)16 to octal equivalent will give c) 251 d) 351

(1101)2 using 1st complement --- c) (0011)2 d) (1100)2

magnitude binary representation of the number +27 is 11111011 c) 00011011 11011000 d) None of the above

----------- c) A+B d) B

( )f A B C D E= + + will result in:

) ( )f A B C D E= + + c) ( )(f A B C D E= + + +

) ( )f A B C D E= + + d) ( )(f A B C D E= + + +

is applied to eight NOT gates, the output would have the value of:c) FF d) B3

Gray code c) BCD code ASCII code d) excess 3-code

Student Number:

09/06/2011 2 hours 6

write your answers clearly. The aims of the questions in this part are to evaluate the required minimal student knowledge and skills. Answers in the

Digital Systems, Binary Number Systems, Boolean Algebra, Circuits.

(15 marks)

None of the above

)f A B C D E= + + +

)f A B C D E= + + +

gates, the output would have the value of:

Page 2: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

9) Which of the gates shown in Figures would have an output of logic zero?

a) A and D b) B and D

10) Half adder consists of. ---------- and a) XOR and ANDb) XOR and NOT

11) To add or subtract the following two binary numbers Adder/Subtractor contains at least:

a) 2 full adderb) 4 full adders

12) The JK flip-flop is in its set mode when input J = a) J = 1 and K = 0b) J = 1 and K = 1

13) The figure shown below is -------

a) An S-R latchb) A T flip flop

14) A ripple counter is a(n) ---------- a) asynchronousb) synchronous

15) A Register is a group of ----------a) OR and ANDb) Flip-flops

Which of the gates shown in Figures would have an output of logic zero?

c) A, B, C d) None of them

and ---------- Gates

XOR and AND c) XOR and OR XOR and NOT d) None of above

To add or subtract the following two binary numbers 10001101 and

contains at least: 2 full adder c) 6 full adders 4 full adders d) 8 full adders

flop is in its set mode when input J = -------.and input K -------.

J = 1 and K = 0 c) J = 0 and K = 0 J = 1 and K = 1 d) J = 0 and K = 1

-------

R latch c) A JK flip flop

A T flip flop d) A D flip flop

device asynchronous c) Combinational synchronous d) None of them

----------gates

OR and AND c) OR flops d) None of these

and 10001110, we need

Page 3: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

Question 2 a) Write the Boolean expression for the logic circuit

b) Draw the truth table for the logic circuit

Write the Boolean expression for the logic circuit

Solution

Draw the truth table for the logic circuit in question 2.a

Solution

(5 marks) Write the Boolean expression for the logic circuit (2 marks)

(3 marks)

Page 4: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

Question 3 Consider the truth table with four variables

Do the following a) Write unsimplified minterm expression

b) simplify by using a Karnaugh map

variables

Write unsimplified minterm expression

Solution

Karnaugh map

Solution

(5 marks)

(2 marks)

(3 marks)

Page 5: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

Familiar and Unfamiliar Problems Solving: The aim of the questions in this part is to evaluate that the student has some basic knowledge of the key aspects of the lecture material and can attempt to solve familiar and unfamiliar problems of Combinational and Sequential Circuits and Analysis of Sequential Circuits. Question 4 (5 marks)

Implement the logic function f using a single multiplexer; assume that the inputs and their complements are available at the input of the multiplexer.

( ) ( ), , 2, 3, 4, 7f x y z = ∏ Solution

Question 5 (5 marks) Write characteristic equations for each type of flip-flop (JK, SR, D and T); draw in your answer the characteristic tables for each type.

Solution

Page 6: Philadelphia University Faculty of Engineering · 2013. 11. 6. · 10) Half adder consists of. ----- and a) XOR and AND b) XOR and NOT 11) To add or subtract the following two binary

Question 6 (5 marks) A sequential circuit has three � flip-flops �, � and �, and one input �. The circuit is described by the following input equations:

�� � ���� � ��� � ��� � ����� �� � � �� � �

a) Derive the state table for the circuit. (2.5 marks)

b) Draw two state diagrams, one for � � 0 and the other for � � 1. (2.5 marks) Question 7 (10 marks) Using the following table (Gray Code), do the following: Design 3-bit Up/Down Synchronous Gray Code Counter (using JK flip-flops) and one external input Y, When � , the Counter works Up, and when � �, the Counter works Down

Decimal number Gray Code Inputs G2 G1 G0

0 0 0 0 1 0 0 1 2 0 1 1 3 0 1 0 4 1 1 0 5 1 1 1 6 1 0 1 7 1 0 0

GOOD LUCK