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Phase I InterviewEE121DB

SEMICONDUCTOR DESIGN

Ulisses Barraza

Wei Zhao

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MESHGENERATION

DEVICECHARACTERISTICS

DISCUSSIOEXPERIA

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MESH

Gate Work Function=4.014eV

4m

2m

1.8m

0.34m 0.34m0.25m

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Device Characteristics

NMOS ID-VG PMOS LOG(ID)-VG

VD=0.1V

Vth0.5V

VD=-0.1V

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Device Characteristics

NMOS ID-VG PMOS LOG(ID)-VG

VD=0.1VVD=1.5V

VD0.9V

VD=1.5V

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Device Characteristics

Simulation Extraction

At VD=0.1V:

Vth=0.5046V

0.1A/m at 0.4124V

At VD=1.5V:

0.1A/m at 0.4030V

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DEVICE CHARACTERISTICS

TRANSCONDUCTANCE

DEVICE CHARACTERISTICS

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DEVICE CHARACTERISTICSPolysilicon Work Function and Doping

NMOS -Must Ensure that the Fermi-level is below the intrinlevel in the polysilicon gate.

Eg-Si=1.1eV (Ec-Ei)=(Ei-Ev)=Eg-Si/2

N-type EF,N Eg/2 P-type Gate

P-type equivalent Work Function= 4.05eV+( 4.05ev-4.014eV)

Vth=1.064 V

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P type Polysilicon work function: 5.195V

is larger than

Id vs Vg Characteristic:

Vd=-0.1V

1

2

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When Vd=-1.5V

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Using MOS.PARA function

At low Vd=-0.1V(no saturation) S_lin (linear slope): 1.6385E-06 (A/um-V) at Vg= -0.8750

Vth (intercept) : -0.5784 (V) from Vg= -0.8750 (V

Vth_sat (intercept) : -0.4544 (V) from Vg= -0.6125

S_sub (subthr slope): 87.58 (mV/dec) at Vg= -0.4250

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Using TV2D to extract gate voltage

By using probe function, when Vd=-1.5VVg=-0.62V corresponding to 0.1A/m

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When Vd=-0.1V, Vg=-0.62