phase error compensation of chirp signal generator...
TRANSCRIPT
Phase Error Compensation of Chirp Signal Generator Implemented on Direct Digital Synthesizer
Heein Yang and Jae-Hyun Kim Ajou University
E-mail {kfcddong, jkim}@ajou.ac.kr
Abstract
As the synthetic aperture radar (SAR) system
requires high-resolution, chirp signal generator that can provide wide-bandwidth signal is also needed . Direct digital synthesizer (DDS) accumulates phase signal of chirp and synthesizes it with amplitude. It can generate the signal with wide-bandwidth, however due to the truncation spurs in DDS system the spectrum purity is not guaranteed. In this paper, DDS chirp signal generator with phase compensation block is proposed and the simulation result shows that proposed method can eliminate the phase offset ideally. Keywords: Synthetic aperture radar, chirp signal generator, direct digital synthesizer, frequency accumulator, phase error 1. Introduction
Synthetic aperture radar (SAR) is a kind of active sensor that provides high-resolution images of target by using microwave signal called chirp. Chirp signal is a linear frequency modulated signal its frequency increases or decreases linearly according to time. The reason why SAR uses chirp signal is that it has large bandwidth and the radar system with wide bandwidth can achieve the high-resolution due to equation (1).
2 2Bc cr τ= = (1
) where c, τ , and B are speed of light, pulse width of signal and signal bandwidth respectively. Accordingly, SAR system requires the chirp signal generator that can generate signal with wide-bandwidth. Direct digital synthesizer (DDS) is a solution that can generate the signal with wide-bandwidth but it has phase error on signal plot than spectrum purity gets lowered. This paper proposes the error compensation method for DDS chirp signal generator.
2. Structure of DDS signal generator
The signal characteristic of chirp signal can be
derived as ( ) ( )2exps t j Kt tπ β= + (2)
where K is sweep rate of chirp signal that defines swept frequency range.
The structure of DDS signal generator is shown in Figure 1. DDS consists of constant source as input, frequency and phase accumulators, and look-up table (LUT) [1]. Chirp signal generation procedure as follows.
( ) 2
2t t tαφ β γ= + + (3)
Register++ Register++++ ++ LUT:
constant source
: frequency offset : phase offset
Chirp pulse output
Frequency accumulator
Phase accumulator
Figure 1. Structure of DDS signal generator.
Figure 2. Signal plot of chirp signals.
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Table 1: Simulation parameters
Contents Features Center frequency 1.27 GHz Bandwidth 288 MHz Pulse width 3.6 sμ Bits 16 bits
where α , β , and γ are constant source, frequency offset, and phase offset respectively. As the chirp signal has phase of 2nd order polynomial, chirp signal generator first calculates the phase, then matches the phase address to amplitude in LUT. Accumulator consists of feedback loop and register and it accumulates the input signal with the clock source. Therefore the output of frequency accumulator will be ramp and in the same way phase accumulator will draw out 2nd order curve output. Figure 2. Shows the time domain signals between ideal and DDS signal generators. The signal phase of DDS is shifted from the center point and it degrades spectrum purity.
3. Error compensation procedure
To eliminate the phase error in DDS chirp signal, we define the phase error term as equation (4).
error ideal DDSφ φ φ= − (4)Therefore we extract the actual phase value of ideal and DDS signals and model the phase error. Additionally, compensated phase error is defined as
compensated DDS error idealφ φ φ φ= + = (5)Equation (5) indicates the compensated phase is identical to ideal signal phase. Phase error errorφ has been shown in 1st order polynomial and it means that β in equation (3) should be adjusted. Because β determines the starting frequency value (center frequency) and the signal in Figure 2 is simulated in baseband. Consequently frequency offset error due to truncation exists in conventional DDS chirp signal generator and if we add the coefficient of errorφ to frequency offset the phase error will be eliminated ideally.
4. Simulation results
Table 1 shows the simulation environment in this paper. Figure 3 is presented to verify that proposed DDS compensates the phase error of chirp signal in time domain. Proposed DDS signal perfectly traces ideal signal and phase error is compensated. It has been introduces that DDS has bad spectrum purity due to
phase error from truncation. However thanks to frequency offset adjusting the output of proposed DDS is identical to ideal chirp waveform and it is assumed that it can enhance the spectrum purity also. 5. Conclusion
In this paper, phase error in conventional DDS has been investigated and phase error has been modeled to polynomial. By adjusting the frequency offset value, proposed DDS could enhance the signal output in time. Consequently proposed DDS has the same signal characteristic with ideal chirp signal. Acknowledgement
This research was supported by NSL (National Space Lab) program through the National Research Foundation of Korea funded by the Ministry of Education, Science and Technology (2012-0009092) and KARI (Korean Aerospace Research Institute) though the Ministry of Science, ICT and Future Planning.
References [1] A. Samarah, “A Novel Approach for Generating Digital Signals Using FPGA Technology for Synthetic Aperture Radar Applications”, Ph. D Thesis, pp. 13-55. [2] H. Yang, S. B. Ryu, H. C. Lee, S. G. Lee, S.S. Yong, and J. H. Kim, “Implementation of DDS Chirp Signal Generator of FPGA”, Proc. in ICTC 2014, October, 2014. [3] J. Tierney, “A Digital Frequency Synthesizer”, Audio and Electronics, IEEE Trans. on, vol. 19, no. 1, pp. 48-57. 1971.
Figure 3. Time domain chirp signals of ideal, DDS, and proposed DDS.
ICEIC 2015
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